CN104051006A - Method and device for reducing bit line leakage current in floating gate memory - Google Patents
Method and device for reducing bit line leakage current in floating gate memory Download PDFInfo
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- CN104051006A CN104051006A CN201310077030.8A CN201310077030A CN104051006A CN 104051006 A CN104051006 A CN 104051006A CN 201310077030 A CN201310077030 A CN 201310077030A CN 104051006 A CN104051006 A CN 104051006A
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Abstract
The invention discloses a method and a device for reducing a bit line leakage current in a floating gate memory. The method includes a following step: when an operation is carried out to a memory array of the floating gate memory, applying a positive voltage to a substrate end of a non-selected memory unit, wherein the operation includes programming, reading and/or verification, and further the positive voltage is provided by a peripheral circuit, is more than 0V and not more than 3V and is preferably 1V or the positive voltage is provided by an operation voltage and is 1.8V or 3.3V. By means of the method and the device for reducing the bit line leakage current in the floating gate memory, a coupling influence of a selected unit on a adjacent non-selected unit during a programming operation, a reading operation and various verification operations can be reduced, the bit line (BL) leakage current can be reduced, system power consumption can be reduced and accuracies of reading and verification can be enhanced.
Description
Technical field
The present invention relates to technical field of data storage, relate in particular to a kind of method and device thereof that reduces floating-gate memory bit line leakage current.
Background technology
Remove/programming that floating-gate memory is non-volatile owing to having, erasable, and lower-cost feature, be therefore widely used.Floating-gate memory EEPROM, NAND Flash and the NOR Flash of main flow at present.
The technique basis of floating-gate memory is CMOS technique, and therefore floating-gate memory is the same with other CMOS integrated circuit has experienced the process that characteristic dimension is constantly dwindled.In this process, memory cell area constantly dwindles, and has brought memory capacity and close wide the improving constantly of storage.And the progress of encapsulation technology, the employing of multi-chip package technology (MutiChip Package, MCP), further increases the monolithic capacity of floating-gate memory.In feature size downsizing, occur storing long numeric data in a storage unit, further improve the capacity of storage.
In floating-gate memory, exist programming, read and the operator scheme such as checking, in these several operator schemes, all can occur the not selected cell of coupling influence of selected cell, make not selected cell in faint opening, increase the leakage current of bit line direction.
In prior art, floating-gate memory operator scheme as shown in Figure 1, in the storage array of floating-gate memory, each word line WL connects the grid end of each memory cell transistor in each memory word, each bit line BL connects the drain terminal of each memory cell transistor in each bank bit, and source connects the source according to all memory cell transistors in the P trap of floating-gate memory.Floating-gate memory principle of operation is: for the unit of choosing, on its word line WL He on bit line BL, all apply corresponding voltage; And for selected cell not, on word line WL, applying 0 voltage, bit line BL is floating empty; The source of all unit is received together jointly, and the common ground that is connected with the P trap (P-well) at array place.
There is certain defect in this traditional method of operating, due to coupling, the floating boom of selected cell can not be subject to the impact of adjacent selected cell word line WL and bit line BL voltage, rise to a positive potential, make not selected cell in faint conducting state, increase BL leakage current, after chip density significantly improves, this effect is further obvious, reads and the accuracy of verification operation strengthening to have reduced in system power dissipation, even affects chip reliability.
Summary of the invention
The object of the invention is to propose a kind of method and device thereof that reduces floating-gate memory bit line leakage current, when can improving the precision of storer, increase the reliability of chip.
For reaching this object, the present invention by the following technical solutions:
Reduce a method for floating-gate memory bit line leakage current, be included in when the storage array of floating-gate memory is operated, apply a positive voltage in the substrate terminal of not choosing storage unit, wherein said operation comprises programming, reads and/or verifies.。
Further, described positive voltage provides by peripheral road road, and described positive voltage is greater than 0 volt and be not more than 3 volts.
Further, described positive voltage is 1 volt.
Or described positive voltage provides by operating voltage, described positive voltage size is 1.8 volts or 3.3 volts.
According to same design of the present invention, the present invention also provides a kind of device that reduces floating-gate memory bit line leakage current, comprise voltage applying unit, for in the time that the storage array of floating-gate memory is operated, apply a positive voltage in the substrate terminal of not choosing storage unit, wherein said operation comprises programming, reads and/or verifies.
Further, described positive voltage provides by peripheral road road, and described positive voltage is greater than 0 volt and be not more than 3 volts.
Further, described positive voltage is 1 volt.
Or described positive voltage provides by operating voltage, described positive voltage size is 1.8 volts or 3.3 volts.
According to same design of the present invention, the present invention also provides a kind of floating-gate memory, comprises the device that reduces floating-gate memory bit line leakage current as above.
The present invention is by applying a positive voltage in the substrate terminal of not choosing storage unit, with respect to legacy memory method of operating, can reduce programming, read and when various verification operation selected cell for the coupling influence of adjacent not selected cell, can reduce bit line BL leakage current, system power dissipation can be reduced, the accuracy that reads and verify can be promoted.
Brief description of the drawings
Fig. 1 is floating-gate memory operator scheme schematic diagram in prior art;
Fig. 2 is word line WL coupling influence schematic diagram in prior art;
Fig. 3 is prior art neutrality line BL coupling influence schematic diagram;
Fig. 4 is the operator scheme schematic diagram described in the specific embodiment of the invention one.
Embodiment
Current, along with reducing of characteristic dimension, the array density of floating-gate memory enlarges markedly, and coupling effect more highlights.In traditional floating-gate memory operator scheme, the operation of selected cell, the impact that can make adjacent not selected cell be coupled, increases the leakage current in bit line direction.Mainly be divided into following two large classes:
1, the impact of adjacent selected word line WL.As shown in Figure 2, in the storage array of floating-gate memory, each word line WL connects the grid end of each memory cell transistor in each memory word, and each bit line BL connects the drain terminal of each memory cell transistor in each bank bit, and source connects the source according to all memory cell transistors in the P trap of floating-gate memory.Floating-gate memory programming, read and various verification operation in, can apply a positive voltage at the grid end of selected cell, and adjacent not selected cell can apply a no-voltage at grid end conventionally.Due to coupling, between the word line WL of the consecutive storage unit in Fig. 2 and floating boom (floating gate), can there is a coupling capacitance C who can not ignore, this makes not selected cell floating boom can not keep 0 current potential, but rises to a positive potential and keep always.When array density is larger, selected cell WL voltage rises when very fast, and coupling effect can be comparatively obvious, and now selected cell can be in a kind of faint conducting state, and this will directly cause bit line direction leakage current to increase.
2, the adjacent impact of choosing bit line BL.As shown in Figure 3, in the storage array of floating-gate memory, each word line WL connects the grid end of each memory cell transistor in each memory word, and each bit line BL connects the drain terminal of each memory cell transistor in each bank bit, and source connects the source according to all memory cell transistors in the P trap of floating-gate memory.Floating-gate memory programming, read and various verification operation in, can apply a positive voltage at the drain terminal of selected cell, and adjacent not selected cell, drain terminal connects identical bit line BL voltage, grid end ground connection conventionally.Due to coupling, between adjacent bit lines BL in Fig. 3 and floating boom (floating gate), can there is a coupling capacitance C who can not ignore, this makes the grid end of selected cell not can be subject to the impact of selected cell drain terminal, rises to a positive potential and keep within a period of time.When array density is larger, selected cell bit line BL voltage rises when very fast, and coupling effect can be comparatively obvious, and now selected cell can be in a kind of faint conducting state, and this will directly cause bit line direction leakage current to increase.Because the upper linkage unit of same bit line BL is more, leakage current will be multiplied.
Because the electric leakage in bit line direction can increase the power consumption that system is unnecessary, after electric leakage increases to a certain degree, can affect and read and the accuracy of various verification operations, even there is " soft programming " phenomenon, therefore, reduce bit line BL leakage current most important in floating-gate memory system.
Further illustrate technical scheme of the present invention below in conjunction with accompanying drawing and by embodiment.
Fig. 4 is prior art neutrality line BL coupling influence schematic diagram, as shown in Figure 4, in the storage array of floating-gate memory, each word line WL connects the grid end of each memory cell transistor in each memory word, each bit line BL connects the drain terminal of each memory cell transistor in each bank bit, and source connects the source according to all memory cell transistors in the P trap of floating-gate memory.Compared with traditional mode of operation, in the time that storage array is operated, in the storage unit of choosing, apply corresponding operating voltage, and for unchecked storage unit, in its substrate terminal, on P trap (P-well), apply a positive voltage, it is poor that equivalence reduces the gate source voltage of selected cell not, offset thus coupling effect to the not impact of selected cell, reduce the leakage current in bit line BL direction.
Adopt the method adopting in this invention, on the P trap (P-well) of selected cell not, apply positive voltage, can make it in more reliable closed condition.In the time that selected cell is operated, even rise because coupling makes its adjacent not selected cell grid terminal potential, also can be due to the positive voltage on P trap (P-well), make its equivalent gate source voltage deficiency so that storage unit is crack opens, still, in strict closed condition, there will not be large leakage current.Further, described positive voltage can provide by peripheral road road, and size, for being greater than 0 volt and be not more than 3 volts, be preferably 1 volt, or described positive voltage can provide by operating voltage, and size is 1.8 volts or 3.3 volts.
According to same design of the present invention, the present invention also provides a kind of device that reduces floating-gate memory bit line leakage current, comprise voltage applying unit, in the time that the storage array of floating-gate memory is operated, apply a positive voltage in the substrate terminal of not choosing storage unit.Further, described positive voltage provides by peripheral road road, and size, for being greater than 0 volt and be not more than 3 volts, be preferably 1 volt, or described positive voltage provides by operating voltage, and size is 1.8 volts or 3.3 volts.
The device that reduces floating-gate memory bit line leakage current described in the embodiment of the present invention, by apply a positive voltage in the substrate terminal of not choosing storage unit, with respect to legacy memory method of operating, can reduce programming, read and when various verification operation selected cell for the coupling influence of adjacent not selected cell, can reduce BL leakage current, system power dissipation can be reduced, the accuracy that reads and verify can be promoted.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a method that reduces floating-gate memory bit line leakage current, is characterized in that, in the time that the storage array of floating-gate memory is operated, applies a positive voltage in the substrate terminal of not choosing storage unit, and wherein said operation comprises programming, reads and/or verifies.
2. the method that reduces floating-gate memory bit line leakage current as claimed in claim 1, is characterized in that, described positive voltage provides by peripheral road road, and described positive voltage is greater than 0 volt and be not more than 3 volts.
3. the method that reduces floating-gate memory bit line leakage current as claimed in claim 1 or 2, is characterized in that, described positive voltage is 1 volt.
4. the method that reduces floating-gate memory bit line leakage current as claimed in claim 1, is characterized in that, described positive voltage provides by operating voltage, and described positive voltage size is 1.8 volts or 3.3 volts.
5. one kind reduces the device of floating-gate memory bit line leakage current, it is characterized in that, comprise voltage applying unit, for in the time that the storage array of floating-gate memory is operated, apply a positive voltage in the substrate terminal of not choosing storage unit, wherein said operation comprises programming, reads and/or verifies.
6. the device that reduces floating-gate memory bit line leakage current as claimed in claim 5, is characterized in that, described positive voltage provides by peripheral road road, and described positive voltage is greater than 0 volt and be not more than 3 volts.
7. the device that reduces floating-gate memory bit line leakage current as described in claim 5 or 6, is characterized in that, described positive voltage is 1 volt.
8. the device that reduces floating-gate memory bit line leakage current as claimed in claim 5, is characterized in that, described positive voltage provides by operating voltage, and described positive voltage size is 1.8 volts or 3.3 volts.
9. a floating-gate memory, is characterized in that, comprises the device that reduces floating-gate memory bit line leakage current as described in one of claim 5 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310077030.8A CN104051006A (en) | 2013-03-11 | 2013-03-11 | Method and device for reducing bit line leakage current in floating gate memory |
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| CN201310077030.8A CN104051006A (en) | 2013-03-11 | 2013-03-11 | Method and device for reducing bit line leakage current in floating gate memory |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091632A (en) * | 1997-06-13 | 2000-07-18 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor storage device having a plurality of blocks of memory cell transistors formed on respective wells isolated from each other |
| CN1369096A (en) * | 1999-08-13 | 2002-09-11 | 先进微装置公司 | Circuit implemention to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM |
| CN101425335A (en) * | 2007-11-01 | 2009-05-06 | 海力士半导体有限公司 | Nonvolatile memory device and reading method thereof |
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- 2013-03-11 CN CN201310077030.8A patent/CN104051006A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091632A (en) * | 1997-06-13 | 2000-07-18 | Sharp Kabushiki Kaisha | Nonvolatile semiconductor storage device having a plurality of blocks of memory cell transistors formed on respective wells isolated from each other |
| CN1369096A (en) * | 1999-08-13 | 2002-09-11 | 先进微装置公司 | Circuit implemention to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM |
| CN101425335A (en) * | 2007-11-01 | 2009-05-06 | 海力士半导体有限公司 | Nonvolatile memory device and reading method thereof |
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Application publication date: 20140917 |