CN103000224A - Method for erasing memory chip - Google Patents
Method for erasing memory chip Download PDFInfo
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- CN103000224A CN103000224A CN2011102748507A CN201110274850A CN103000224A CN 103000224 A CN103000224 A CN 103000224A CN 2011102748507 A CN2011102748507 A CN 2011102748507A CN 201110274850 A CN201110274850 A CN 201110274850A CN 103000224 A CN103000224 A CN 103000224A
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Abstract
The invention discloses a method for erasing a memory chip, which changes a common source of the memory chip from a grounding mode to a current limiting device, and comprises the following steps: pre-programming blocks in the memory cells; erasing all memory cells; verifying the erased memory cell; and performing soft program verification in units of bit lines. The invention can effectively shorten the erasing time, and the current limiting device can ensure that the memory cells are not damaged due to overlarge current flowing through the memory cells even though the plurality of cells are erased at the same time, thereby ensuring the reliability of the erasing operation and being particularly suitable for large-capacity memory chips.
Description
Technical field
The present invention relates to integrated circuit and nonvolatile memory chip technical field, particularly a kind of method that memory chip is wiped.
Background technology
Nonvolatile memory is a field that development is very fast, and the memory device that is used for now nonvolatile memory chip adopts the floating gate structure memory device more, and this floating gate structure memory device is wiped the electric erasable modes that adopt more.When wiping, be to add negative bias at floating boom, add positive bias at substrate simultaneously, and then the electronics on the floating boom is removed, realize wiping this floating gate structure memory device.
A problem of floating-gate memory spare being wiped existence was to wipe phenomenon.When the electronics on the floating boom is removed when too much, will occur wiping, will exist a certain amount of positive charge on the floating boom this moment, so that memory device is in the crack state that opens, has leakage current and exist in device channel.Can cause misread phenomenon like this, and can cause obstruction to next time programming, because if will programme fully, need on floating boom, to add than more electronics under normal circumstances with in floating boom on the positive charge that exists.
For there being the storage unit of wiping phenomenon, need to carry out soft programming, soon unnecessary positive charge is removed on the floating boom, makes storage unit return to normal situation.Add the positive voltage lower than when programming in gate terminal during soft programming, add certain positive voltage at drain electrode end, flow through so certain electric current in the raceway groove, some electrons wherein are captured on the floating boom, and then the positive charge that neutralized and stay at floating boom when wiping.
The existing commonly used method that memory chip is wiped as shown in Figure 1, the storage unit of at first needs being wiped is carried out pre-programmed, then carry out erase operation, carry out erase verification for bit (Byte) afterwards, soft programming and soft program verification also are Byte-by-Byte.The method specifically describes as follows:
(1) piece (Sector) of choosing is carried out pre-programmed, namely grid end and the drain terminal in storage unit adds respectively suitable positive voltage (as being respectively 7V and 4V), make current flowing in the memory cell channels, electronics in the electric current is caught by floating boom, thereby all storage unit that will choose are programmed to 0;
(2) all storage unit are wiped, namely the grid end of storage unit add suitable negative pressure (as-9V), substrate adds suitable positive Asia (such as 7V), the electronics on the floating boom is removed, thereby with all cell erase to 1;
(3) storage unit after wiping is verified that namely take Byte as unit, add respectively suitable malleation (as adding respectively 5V and 1V) at grid end and the drain terminal of storage unit, the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully.If wipe successfully, then with the zero setting of Byte address, changed erase verification over to, otherwise Sector was wiped again.If the erasing times to same Sector is inferior above certain number of times such as MAX (8), in order to prevent that some normal cell are caused damage, it is generally acknowledged to wipe and make mistakes, then produce error message, withdraw from and wipe;
(4) carried out erase verification (being soft program verification) take Byte as unit, namely take Byte as unit, grid end and drain terminal in storage unit add respectively suitable malleation (as adding respectively 5V and 1V), and the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully.If pass through, then change next Byte address over to; Otherwise this Byte is carried out soft programming, turn over again erase verification; If the soft programming number of times to same Byte surpasses Maxu time, then return error message, enter next Byte address, until last that Byte among the Sector that chooses.
For the little storage chip of memory capacity, this method reliability is high, and the time also in rational scope, be a kind of good selection.But when memory capacity became large, this method operated and will consume the long time, and this use for memory chip will be serious shortcoming.
Summary of the invention
The technical matters that (one) will solve
For the problem of existing method for deleting overlong time, fundamental purpose of the present invention is to provide a kind of method that memory chip is wiped, with the shortening erasing time, and the reliability of assurance chip.
(2) technical scheme
In order to achieve the above object, the present invention proposes a kind of method that memory chip is wiped, the common source of memory chip is changed into from earthing mode connect current-limiting apparatus, the method comprises: the piece in the storage unit is carried out pre-programmed; All storage unit are wiped; Storage unit after wiping is verified; And carry out soft program verification take bit line as unit.
In the such scheme, described common source with memory chip changes into from earthing mode and connects current-limiting apparatus, is the drain terminal that the source of the storage unit of memory chip is connected in current-limiting apparatus.
In the such scheme, describedly piece in the storage unit is carried out pre-programmed comprise: grid end and drain terminal in storage unit add respectively positive voltage, make current flowing in the memory cell channels, and the electronics in the electric current is caught by floating boom, thereby storage unit is programmed to 0.It is 7V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 4V.
In the such scheme, described all storage unit are wiped comprises: the grid end in storage unit adds negative pressure, adds malleation at substrate, the electronics on the floating boom is removed, thereby with all cell erase to 1.It is-9V that adding malleation at substrate is 7V that described grid end in storage unit adds negative pressure.
In the such scheme, described storage unit after wiping is verified comprises: take bit line as unit, grid end and drain terminal in storage unit add respectively malleation, the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully, if wipe successfully, then with bit line address zero setting, changed erase verification over to, otherwise piece was wiped again; If same erasing times is surpassed certain number of times, then think to wipe and make mistakes, produce error message, withdraw from and wipe.It is 5V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 1V.
In the such scheme, the described soft program verification of carrying out take bit line as unit comprises: take bit line as unit, add respectively malleation at grid end and the drain terminal of storage unit, the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully, if wipe successfully, then change next bit line address over to; Otherwise this bit line is carried out soft programming, turn over again erase verification; If the soft programming number of times to the same bit line surpasses the maximum times of setting, then return error message, enter next bit line address, until the last item bit line in the piece of choosing.It is 5V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 1V.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1, the relatively existing commonly used method that memory chip is wiped of the present invention, do not need circuit is done large change, only the common source of original memory array need to be changed into from earthing mode and connect current-limiting apparatus, current-limiting apparatus as shown in Figure 3, the source of storage unit 320 links to each other with the drain terminal of current-limiting apparatus 322, and this is easy to realize.
2, when effectively shortening the erasing time, because the use of current-limiting apparatus, although so that simultaneously a plurality of unit are wiped, can not make the electric current that flows through storage unit (mirror image effect make the electric current in this electric current and the current-limiting apparatus proportional) excessive and make storage unit destroyed yet, this so that the reliability of erase operation also be guaranteed, so particularly suitable mass storage chip.
Description of drawings
Fig. 1 is the existing commonly used method flow diagram that memory chip is wiped;
Fig. 2 is the method flow diagram that memory chip is wiped according to the embodiment of the invention;
Fig. 3 is the synoptic diagram according to the current-limiting apparatus of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The method that memory chip is wiped that the present invention proposes, its basic thought is all for a bit lines (Bit line) when erase verification, soft programming and soft program verification, and the common source of memory chip changed into from earthing mode connect current-limiting apparatus, specifically comprise: the piece in the storage unit is carried out pre-programmed; All storage unit are wiped; Storage unit after wiping is verified; And carry out soft program verification take bit line as unit.
It is impaired to flow through excessive unit and the circuit of making of the electric current of storage unit when making erase verification and soft program verification, adds current-limiting apparatus in the source of storage unit.In order to guarantee the reliability of soft programming, source in storage unit is added current-limiting apparatus, make the soft programming electric current be no more than a certain numerical value, like this in the situation of steady current, existed the unit of wiping phenomenon with respect to there not being the unit of wiping phenomenon, to flow through more electric current, and soft programming mainly be concentrated on existed on the unit of wiping phenomenon.Add suitable control circuit at word-line direction, so that when erase verification, soft program verification and soft programming, choose all word lines.
Fig. 2 is the method flow diagram that memory chip is wiped according to the embodiment of the invention, and the method specifically describes as follows:
(1) piece (Sector) of choosing is carried out pre-programmed, namely grid end and the drain terminal in storage unit adds respectively suitable positive voltage (as being respectively 7V and 4V), make current flowing in the memory cell channels, electronics in the electric current is caught by floating boom, thereby all storage unit that will choose are programmed to 0;
(2) all storage unit are wiped, namely the grid end of storage unit add suitable negative pressure (as-9V), substrate adds suitable positive Asia (such as 7V), the electronics on the floating boom is removed, thereby with all cell erase to 1;
(3) storage unit after wiping is verified, namely take bit line (Bit line) as unit, grid end and drain terminal in storage unit add respectively suitable malleation (as adding respectively 5V and 1V), and the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully.If wipe successfully, then with the zero setting of Bitline address, changed erase verification over to, otherwise Sector was wiped again.If the erasing times to same Sector is inferior above certain number of times such as MAX (8), it is generally acknowledged to wipe and make mistakes, then produce error message, withdraw from and wipe;
(4) carried out erase verification (being soft program verification) take Bit line as unit, namely take Bit line as unit, grid end and drain terminal in storage unit add respectively suitable malleation (as adding respectively 5V and 1V), and the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully.If pass through, then change next Bit line address over to; Otherwise this Bit line is carried out soft programming, turn over again erase verification; If the soft programming number of times to same Bitline surpasses the maximum times (Maxu) of setting, then return error message, enter next Bit line address, until the last item Bit line among the Sector that chooses.
In order to make erase verification, mistake erase verification and the soft programming Reliability Enhancement in the such scheme, the present invention proposes the solution that adds current-limiting apparatus in the source of storage unit.Fig. 3 is the synoptic diagram according to the current-limiting apparatus of the embodiment of the invention, and wherein device the first transistor 310, mistake transistor seconds 312 and current-limiting apparatus 322 play the mirror image effect, and the source of storage unit 320 is connected with the drain terminal of current-limiting apparatus 322.This is a current-mirror structure, by the electric current of Vload control the first transistor 310, the current mirror that forms by transistor seconds 312 and current-limiting apparatus 322 with the current mirror of the first transistor 310 in current-limiting apparatus 322; The drain terminal of current-limiting apparatus 322 connects the source of storage unit 320.The electric current that flows through as can be known storage unit 320 according to the principle of mirror image circuit is proportional with the electric current that flows through the first transistor 310; thereby adopt a kind of like this structure effectively to control the electric current that flows through storage unit 320 by the electric current of control the first transistor 310; can holding circuit and storage unit; simultaneously because electric current is constant; so in soft programming; electric current more tends to flow through and had the unit of wiping phenomenon, so that soft programming efficient and reliability all are improved.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the method that memory chip is wiped is characterized in that, the common source of memory chip is changed into from earthing mode connect current-limiting apparatus, and the method comprises:
Piece in the storage unit is carried out pre-programmed;
All storage unit are wiped;
Storage unit after wiping is verified; And
Carry out soft program verification take bit line as unit.
2. the method that memory chip is wiped according to claim 1, it is characterized in that, described common source with memory chip changes into from earthing mode and connects current-limiting apparatus, is the drain terminal that the source of the storage unit of memory chip is connected in current-limiting apparatus.
3. the method that memory chip is wiped according to claim 1 is characterized in that, describedly piece in the storage unit is carried out pre-programmed comprises:
Grid end and drain terminal in storage unit add respectively positive voltage, make current flowing in the memory cell channels, and the electronics in the electric current is caught by floating boom, thereby storage unit is programmed to 0.
4. the method that memory chip is wiped according to claim 3 is characterized in that, it is 7V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 4V.
5. the method that memory chip is wiped according to claim 1 is characterized in that, described all storage unit are wiped comprises:
Grid end in storage unit adds negative pressure, adds malleation at substrate, the electronics on the floating boom is removed, thereby with all cell erase to 1.
6. the method that memory chip is wiped according to claim 5 is characterized in that, it is-9V that adding malleation at substrate is 7V that described grid end in storage unit adds negative pressure.
7. the method that memory chip is wiped according to claim 1 is characterized in that, described storage unit after wiping is verified comprises:
Take bit line as unit, add respectively malleation at grid end and the drain terminal of storage unit, the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully, if wipe successfully, then with bit line address zero setting, changed erase verification over to, otherwise piece is wiped again; If same erasing times is surpassed certain number of times, then think to wipe and make mistakes, produce error message, withdraw from and wipe.
8. the method that memory chip is wiped according to claim 7 is characterized in that, it is 5V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 1V.
9. the method that memory chip is wiped according to claim 1 is characterized in that, the described soft program verification of carrying out take bit line as unit comprises:
Take bit line as unit, add respectively malleation at grid end and the drain terminal of storage unit, the electric current of crossing in the storage unit by reading flow judges whether to wipe successfully, if wipe successfully, then changes next bit line address over to; Otherwise this bit line is carried out soft programming, turn over again erase verification; If the soft programming number of times to the same bit line surpasses the maximum times of setting, then return error message, enter next bit line address, until the last item bit line in the piece of choosing.
10. the method that memory chip is wiped according to claim 9 is characterized in that, it is 5V that described grid end in storage unit adds positive voltage, and adding positive voltage at the drain terminal of storage unit is 1V.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102748507A CN103000224A (en) | 2011-09-16 | 2011-09-16 | Method for erasing memory chip |
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| CN2011102748507A CN103000224A (en) | 2011-09-16 | 2011-09-16 | Method for erasing memory chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653085A (en) * | 2015-10-30 | 2017-05-10 | 爱思开海力士有限公司 | Storage device, memory system having the same, and operating method thereof |
| CN106971760A (en) * | 2017-04-01 | 2017-07-21 | 北京兆易创新科技股份有限公司 | Threshold voltage method of calibration, device and NAND memory device based on nand flash memory |
| CN108389601A (en) * | 2017-02-02 | 2018-08-10 | 三星电子株式会社 | The soft-erase method of non-volatile memory device |
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| US20070019470A1 (en) * | 2005-07-25 | 2007-01-25 | Macronix International Co., Ltd. | Systems and methods for improved programming of flash based devices |
| CN101023497A (en) * | 2004-08-30 | 2007-08-22 | 斯班逊有限公司 | Nonvolatile storage and erasing method for nonvolatile storage |
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2011
- 2011-09-16 CN CN2011102748507A patent/CN103000224A/en active Pending
Patent Citations (4)
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| US6031766A (en) * | 1997-09-10 | 2000-02-29 | Macronix International Co., Ltd. | Method and circuit for substrate current induced hot e-injection (SCIHE) approach for VT convergence at low Vcc voltage |
| US6166955A (en) * | 1999-07-09 | 2000-12-26 | Macronix International Co., Ltd. | Apparatus and method for programming of flash EPROM memory |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653085A (en) * | 2015-10-30 | 2017-05-10 | 爱思开海力士有限公司 | Storage device, memory system having the same, and operating method thereof |
| CN106653085B (en) * | 2015-10-30 | 2020-11-10 | 爱思开海力士有限公司 | Storage device, memory system having the same, and method of operating the same |
| CN108389601A (en) * | 2017-02-02 | 2018-08-10 | 三星电子株式会社 | The soft-erase method of non-volatile memory device |
| CN108389601B (en) * | 2017-02-02 | 2021-12-07 | 三星电子株式会社 | Soft erase method for non-volatile memory device |
| CN106971760A (en) * | 2017-04-01 | 2017-07-21 | 北京兆易创新科技股份有限公司 | Threshold voltage method of calibration, device and NAND memory device based on nand flash memory |
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Application publication date: 20130327 |