CN103258845B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN103258845B CN103258845B CN201210038549.0A CN201210038549A CN103258845B CN 103258845 B CN103258845 B CN 103258845B CN 201210038549 A CN201210038549 A CN 201210038549A CN 103258845 B CN103258845 B CN 103258845B
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Abstract
The invention discloses a kind of semiconductor structure and forming method thereof.Semiconductor structure comprises the first semiconductor region, the second semiconductor region, dielectric structure and gate electrode layer.First semiconductor region has the first conductivity type.Second semiconductor region has the second conductivity type in contrast to the first conductivity type.First semiconductor region is adjacent second semiconductor region.Dielectric structure is positioned on the first semiconductor region and the second semiconductor region.Gate electrode layer is positioned on dielectric structure.
Description
Technical field
The invention relates to a kind of semiconductor structure and forming method thereof, relate to metal-oxide-semiconductor structure and forming method thereof especially.
Background technology
Between nearly decades, semiconductor industry continues the size reducing semiconductor structure, and improves the unit cost of speed, usefulness, density and integrated circuit simultaneously.In recent years saving energy IC is one of semiconductor structure development priority, and energy conservation IC commonly uses LDMOS or EDMOS as switch.
For example, in order to improve puncture voltage (the breakdown voltage of semiconductor structure such as lateral double diffused metal oxide-semiconductor (LDMOS) or extension drain metal oxide-semiconductor (EDMOS); BVdss), a kind of method is the doping content of reduction drain region and increases drift length.But the method can improve the specific opening resistor (Ron, sp) of semiconductor structure, and make BVdss and Ron, sp cannot improve simultaneously.
Summary of the invention
The invention relates to a kind of semiconductor structure and forming method thereof, semiconductor structure has excellent usefulness and low cost of manufacture.
According to one embodiment of the invention, the invention provides a kind of semiconductor structure.Semiconductor structure comprises the first semiconductor region, the second semiconductor region, dielectric structure and gate electrode layer.First semiconductor region comprises the first doped region and the second doped region.First semiconductor region, the first doped region and the second doped region have the first conductivity type.Second semiconductor region comprises the 3rd doped region.Second semiconductor region and the 3rd doped region have the second conductivity type in contrast to the first conductivity type.Second doped region abuts against between the first doped region and the 3rd doped region.Second doped region has doping diffusion part.Doping diffusion part extends from the top of the second doped region to the 3rd doped region.Doping diffusion part has the first conductivity type.Dielectric structure is positioned on the first semiconductor region and the second semiconductor region.Gate electrode layer is positioned on dielectric structure.
According to one embodiment of the invention, present invention also offers a kind of formation method of semiconductor structure.Method comprises the following steps.Form the first semiconductor region in substrate.First semiconductor region comprises the first doped region and the second doped region.First semiconductor region, the first doped region and the second doped region have the first conductivity type.Form the second semiconductor region in substrate.Second semiconductor region comprises the 3rd doped region.Second semiconductor region and the 3rd doped region have the second conductivity type in contrast to the first conductivity type.Second doped region abuts against between the first doped region and the 3rd doped region.Second doped region has doping diffusion part.Doping diffusion part extends from the top of the second doped region to the 3rd doped region.Doping diffusion part has the first conductivity type.Form dielectric structure on the first semiconductor region and the second semiconductor region.Form gate electrode layer on dielectric structure.
Embodiments more cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 to Fig. 4 illustrates according to semiconductor structure of an embodiment and forming method thereof.
Fig. 5 illustrates the top view of the semiconductor structure according to an embodiment.
Fig. 6 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 7 illustrates the profile of the semiconductor structure according to an embodiment.
Fig. 8 illustrates the top view of the semiconductor structure according to an embodiment.
Fig. 9 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 10 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 11 illustrates the top view of the semiconductor structure according to an embodiment.
Figure 12 illustrates the profile of the semiconductor structure according to an embodiment.
Figure 13 illustrates the top view of the semiconductor structure according to an embodiment.
[main semiconductor element symbol description]
102: substrate
104,204,304: the first semiconductor regions
106: well region
108: the first doped regions
110,210,310,410: the second doped regions
112: the second semiconductor regions
114: the three doped regions
116,216,316,416: dielectric structure
118,218,318,418: gate electrode layer
120: doped region, top
122: doping diffusion part
124: the first dielectric layers
126: the second dielectric layers
128,228,328,428,528: field plate doped region
130,230,330,430: the first heavy doping contacts
132,232,332,432: the second heavy doping contacts
134,234,334,434: the three heavy doping contacts
136: insulation system
338: protuberance
S: basal surface
T1, T2: thickness
Embodiment
Fig. 1 illustrates the profile of the semiconductor structure according to an embodiment.Semiconductor structure comprises substrate 102.For example, substrate 102 includes but not limited to silicon-on-insulator (SOI), epitaxial material or non-epitaxial material.
First semiconductor region 104 is positioned on substrate 102.First semiconductor region 104 can comprise doped region, well region 106, first doped region 108, second 110 and doped region 120, top.Doped region 120, top is formed in top part of the first doped region 108 and the second doped region 110.
Doped region, well region 106, first doped region 108, second 110 has the first conductivity type such as N conductivity type with doped region 120, top.
Second semiconductor region 112 comprises the 3rd doped region 114.3rd doped region 114 has the second conductivity type such as P conductivity type in contrast to the first conductivity type.3rd doped region 114 is adjacent first semiconductor regions 104.
Second doped region 110 abuts against between the first doped region 108 and the 3rd doped region 114.In embodiment, the second doped region 110 has doping diffusion part 122.Doping diffusion part 122 extends from the top of the second doped region 110 to the 3rd doped region 114.Doping diffusion part 122 has the first conductivity type such as N conductivity type.
Field plate doped region 128 can form the second doped region 110 of the first semiconductor region 104 be arranged in below dielectric structure 116.In embodiment, field plate doped region 128 has the second conductivity type such as P conductivity type.
First heavy doping contact 130 is formed in the first doped region 108 of the first semiconductor region 104.Second heavy doping contact 132 contacts 134 with the 3rd heavy doping and is formed in the 3rd doped region 114 of the second semiconductor region 112.First heavy doping contact 130 contacts 132 with the second heavy doping and has the first conductivity type such as N conductivity type.3rd heavy doping contact 134 has the second conductivity type such as P conductivity type.
Dielectric structure 116 can be positioned at the first doped region 108 and the second doped region 110 of the first semiconductor region 104, with on the 3rd doped region 114 of the second semiconductor region 112.Dielectric structure 116 can contact between 132 with the second heavy doping in the first heavy doping contact 130.
Dielectric structure 116 comprises the first dielectric layer 124 and the second dielectric layer 126.First dielectric layer 124 is adjacent second dielectric layers 126.First dielectric layer 124 and the second dielectric layer 126 can comprise oxide or nitride, such as silica or silicon nitride respectively, or other high-k (high-K) materials be applicable to.For example, the first dielectric layer 124 or the second dielectric layer 126 can have oxidenitride oxide (oxide-nitride-oxide; ONO) structure.
On the first dielectric layer 124 that gate electrode layer 118 can be positioned at dielectric structure 116 and the second dielectric layer 126.Gate electrode layer 118 can comprise metal, polysilicon, metal silicide, or other suitable materials.
Insulation system 136 is not limited to the field oxide (FOX) shown in Fig. 1.For example, insulation system 136 can be shallow trench isolation (shallow trench isolation; STI) or deep trench isolation (deep trench isolation; DTI).
In certain embodiments, be the well region 106 of omission first semiconductor region 104, therefore the first doped region 108 of the first semiconductor region 104 and the 3rd doped region 114 of the second doped region 110 and the second semiconductor region 112 are formed in substrate 102.
In embodiment, semiconductor structure is metal-oxide semiconductor (MOS) (MOS) device, such as LDMOS or EDMOS.In detail, be N conductivity type at the first conductivity type, and the second conductivity type is in the example of P conductivity type, semiconductor structure is N channel LDMOS or N channel EDMOS.Relatively, be P conductivity type at the first conductivity type, and the second conductivity type is in the example of N conductivity type, semiconductor structure is P channel LDMOS or P channel EDMOS.First heavy doping contact 130 is used as drain electrode.Second heavy doping contact 132 is used as source electrode.
In embodiment, second doped region 110 its first conductivity type doping net concentration of position in drift region is less than the doping net concentration of the first conductivity type of the first doped region 108, and this can reduce specific opening resistor (the specific on-resistance of device; Ron, sp).Doped region 120, top is formed in the second doped region 110 (drift region), and this can reduce the specific opening resistor of device.The field plate doped region 128 of position in drift region forms float area (floating area) and the puncture voltage of lifting device (BVdss).
The second doped region 110 due to the first semiconductor region 104 has the doping diffusion part 122 of the 3rd doped region 114 extension to the second semiconductor region 112, therefore.The effective channel length (effective channel length) of device reduces, and reduces aisle resistance.
In embodiment, the first dielectric layer 124 of dielectric structure 116 has the first homogeneous thickness T1.Second dielectric layer 126 has the second homogeneous thickness T2.First thickness T1 is less than the second thickness T2.In embodiment, be used as gate dielectric layer with the first dielectric layer 124.The second dielectric layer 126 using thickness thick compared with the first dielectric layer 124 is used as the puncture voltage that insulation isolation can improve device.The thickness that the thickness of the second dielectric layer 126 is less than insulation system 136 can reduce the specific opening resistor of device.
First dielectric layer 124 and the second dielectric layer 126 have a smooth shared basal surface S.Be the comparative example (not shown) using field oxide compared to the second dielectric layer, use the dielectric structure 116 of embodiment can provide shorter current path in the drift region of device, thus can reduce specific opening resistor.
Fig. 1 to Fig. 4 illustrates the formation method of the semiconductor structure according to an embodiment.Please refer to Fig. 2, utilize doping step to form well region 106 in substrate 102.
Please refer to Fig. 3, utilize doping step in well region 106, form the first semiconductor region 104 and the second semiconductor region 112 respectively.The part that wherein the first semiconductor region 104 is overlapping with the second semiconductor region 112 is the second doped region 110.The formation order of the first semiconductor region 104 and the second semiconductor region 112 does not limit.In an embodiment, the first semiconductor region 104 was formed before the second semiconductor region 112.In another embodiment, the first semiconductor region 104 is formed after the second semiconductor region 112.After carrying out doping step and forming the first semiconductor region 104 and the second semiconductor region 112, be carry out thermal anneal step.Due to the first semiconductor region 104 the first conductivity type such as N conductivity type doping, for thermal diffusion step, there is different diffusion properties from the second conductivity type such as P conductivity type doping of the second semiconductor region 112, be the second doped region 110 obtaining having doping diffusion part 122 after causing thermal diffusion step.Thermal diffusion step can be carried out by arbitrary time point after formation first semiconductor region 104 and the second semiconductor region 112, such as, formed before formation field plate doped region 128, or carry out after formation gate electrode layer 118 (Fig. 4).
Please refer to Fig. 3, then utilize doping step to form field plate doped region 128 in the second doped region 110.In certain embodiments, be omit well region 106, therefore the first doped region 108 of the first semiconductor region 104 and the 3rd doped region 114 of the second doped region 110 and the second semiconductor region 112 are formed in substrate 102.
Please refer to Fig. 4, form dielectric structure 116 on the first semiconductor region 104 and the second semiconductor region 102.For example, the first dielectric layer 124 of dielectric structure 116 and the second dielectric layer 126 can utilize thermal oxidation method or sedimentation such as chemical vapour deposition (CVD) or physical vaporous deposition to be formed.In some embodiments, first can form the lower part of the second dielectric layer 126, while formation first dielectric layer 124, then form the upper part of the second dielectric layer 126.Please refer to Fig. 4, form gate electrode layer 118 on dielectric structure 116.
Please refer to Fig. 1, utilize doping step to be formed in first doped region 108 and the second doped region 110 of the first semiconductor region 104 and push up doped region 120.Doped region 120, top can utilize gate electrode layer 118 to be formed as mask.Utilize doping step in the first doped region 108 of the first semiconductor region 104 and the 3rd doped region 114 of the second semiconductor region 112, form the first heavy doping to contact 130 and contact 132 with the second heavy doping.Utilize doping step in the 3rd doped region 114, form the 3rd heavy doping contact 134.
In embodiment semiconductor structure can application standard high pressure (HV) technique formed, therefore do not need extra mask, and reduce manufacturing cost.
Fig. 5 illustrates the top view of the semiconductor structure according to an embodiment.In some embodiments, semiconductor structure is as shown in Figure 6 along the profile of AB line.Semiconductor structure is as shown in Figure 7 along the profile of CD line.Please refer to Fig. 5 to Fig. 7, Fig. 5 only demonstrate semiconductor structure dielectric structure 216, gate electrode layer 218, first heavy doping contact 230, second heavy doping contact the 232, the 3rd heavy doping contact 234 with field plate doped region 228.Please refer to Fig. 5 and Fig. 7, multiple field plate doped region 228 is separated from each other by the second doped region 210 of the first semiconductor region 204.The field plate doped region 228 of this example has striated (or rectangle, rectangle), right the present invention is not limited to this, and field plate doped region 228 also can have honeycomb, hexagon, octangle (octagonal), circular (circle) or square (square).The difference of the semiconductor structure that Fig. 7 illustrates and the semiconductor structure that Fig. 1 illustrates is, is the doped region, top 120 eliminated in Fig. 1.In addition, the first heavy doping contact 230 is second doped regions 210 of contiguous first semiconductor region 204.
Fig. 8 illustrates the top view of the semiconductor structure according to an embodiment.In some embodiments, semiconductor structure is as shown in Figure 9 along the profile of EF line.Semiconductor structure is as shown in Figure 10 along the profile of GH line.Please refer to Fig. 8 to Figure 10, Fig. 8 only demonstrate semiconductor structure dielectric structure 316, gate electrode layer 318, first heavy doping contact 330, second heavy doping contact the 332, the 3rd heavy doping contact 334 with field plate doped region 328.The difference of the semiconductor structure that Fig. 8 illustrates and the semiconductor structure that Fig. 5 illustrates is, gate electrode layer 318 has multiple protuberance 338 separated from each other.Protuberance 338 is corresponding field plate doped regions 328.Protuberance 338 is not limited to the rectangle shown in Fig. 8, and for example, protuberance 338 can have arc, triangle or other arbitrary shapes.The difference of the semiconductor structure that Figure 10 illustrates and the semiconductor structure that Fig. 1 illustrates is, the first heavy doping contact 330 is second doped regions 310 of contiguous first semiconductor region 304.
Figure 11 illustrates the top view of the semiconductor structure according to an embodiment.In some embodiments, semiconductor structure is the profile being similar to the semiconductor structure shown in Fig. 9 along the profile of IJ line.Semiconductor structure is as shown in figure 12 along the profile of LM line.Please refer to Figure 11 and Figure 12, Figure 11 only demonstrate semiconductor structure dielectric structure 416, gate electrode layer 418, first heavy doping contact 430, second heavy doping contact the 432, the 3rd heavy doping contact 434 with field plate doped region 428.The difference of the semiconductor structure that Figure 11 and Figure 12 illustrates and the semiconductor structure that Fig. 5 and Fig. 7 illustrates is, field plate doped region 428 is laterally separated from each other.
Figure 13 illustrates the top view of the semiconductor structure according to an embodiment.In some embodiments, semiconductor structure is the profile being similar to the semiconductor structure shown in Figure 12 along the profile of OP line.Semiconductor structure is the profile being similar to the semiconductor structure shown in Fig. 6 along the profile of QR line.The difference of the semiconductor structure that Figure 13 illustrates and the semiconductor structure that Figure 11 illustrates is, field plate doped region 528 has honeycomb (hexagon).In other embodiments, field plate doped region 528 can have striated, rectangle (rectangle, square), octangle or circle.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any those who are familiar with this art; in spirit and scope not departing from the present invention; when doing a little change and retouching, therefore the present invention is that protection range is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a semiconductor structure, comprising:
One first semiconductor region, comprises one first doped region and one second doped region, and wherein this first semiconductor region, this first doped region and this second doped region have one first conductivity type;
One second semiconductor region, comprise one the 3rd doped region, wherein this second semiconductor region and the 3rd doped region have one second conductivity type in contrast to this first conductivity type, this second doped region abuts against between this first doped region and the 3rd doped region, this second doped region has a doping diffusion part, extend from the top of this second doped region to the 3rd doped region, this doping diffusion part has this first conductivity type;
One dielectric structure, is positioned on this first semiconductor region and this second semiconductor region;
At least one field plate doped region, is arranged in this first semiconductor region below this dielectric structure, promotes the puncture voltage of semiconductor structure for the formation of float area; And
One gate electrode layer, is positioned on this dielectric structure.
2. semiconductor structure according to claim 1, wherein this first semiconductor region more comprises a doped region, top, is formed in top part of this first doped region, and this doped region, top has this first conductivity type.
3. semiconductor structure according to claim 1, wherein this first semiconductor region more comprises a doped region, top, is formed in top part of this second doped region, and this doped region, top has this first conductivity type.
4. semiconductor structure according to claim 1, wherein the doping net concentration of the first conductivity type of this second doped region is less than the doping net concentration of the first conductivity type of this first doped region.
5. semiconductor structure according to claim 1, wherein this dielectric structure comprises one first dielectric layer and one second dielectric layer, and this first dielectric layer adjoins this second dielectric layer.
6. semiconductor structure according to claim 5, wherein this first dielectric layer has one first homogeneous thickness, and this second dielectric layer has one second homogeneous thickness, and this first thickness is less than this second thickness.
7. semiconductor structure according to claim 5, wherein this first dielectric layer and this second dielectric layer have a smooth shared basal surface.
8. semiconductor structure according to claim 1, wherein this field plate doped region has this second conductivity type.
9. semiconductor structure according to claim 8, wherein this gate electrode layer has multiple protuberance separated from each other, and the plurality of protuberance is corresponding this field plate doped region multiple.
10. a formation method for semiconductor structure, comprising:
Form one first semiconductor region in a substrate, wherein this first semiconductor region comprises one first doped region and one second doped region, and this first semiconductor region, this first doped region and this second doped region have one first conductivity type;
Form at least one field plate doped region in this first semiconductor region, promote the puncture voltage of semiconductor structure for the formation of float area;
Form one second semiconductor region in this substrate, wherein this second semiconductor region comprises one the 3rd doped region, this second semiconductor region and the 3rd doped region have one second conductivity type in contrast to this first conductivity type, this second doped region abuts against between this first doped region and the 3rd doped region, this second doped region has a doping diffusion part, extend from the top of this second doped region to the 3rd doped region, this doping diffusion part has this first conductivity type;
Form a dielectric structure on this first semiconductor region and this second semiconductor region; And
Form a gate electrode layer on this dielectric structure.
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| CN101162697A (en) * | 2006-10-13 | 2008-04-16 | 台湾积体电路制造股份有限公司 | Lateral power mosfet with high breakdown voltage and low on-resistance |
| CN101211975A (en) * | 2006-12-29 | 2008-07-02 | 东部高科股份有限公司 | Semiconductor device having EDMOS transistor and method for manufacturing the same |
| CN102194873A (en) * | 2010-03-10 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Semiconductor device having multi-thickness gate dielectric |
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| JP2008140817A (en) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | Semiconductor device |
| US7847351B2 (en) * | 2008-04-11 | 2010-12-07 | Texas Instruments Incorporated | Lateral metal oxide semiconductor drain extension design |
| US8525263B2 (en) * | 2009-01-19 | 2013-09-03 | International Business Machines Corporation | Programmable high-k/metal gate memory device |
| US8362557B2 (en) * | 2009-12-02 | 2013-01-29 | Fairchild Semiconductor Corporation | Stepped-source LDMOS architecture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162697A (en) * | 2006-10-13 | 2008-04-16 | 台湾积体电路制造股份有限公司 | Lateral power mosfet with high breakdown voltage and low on-resistance |
| CN101211975A (en) * | 2006-12-29 | 2008-07-02 | 东部高科股份有限公司 | Semiconductor device having EDMOS transistor and method for manufacturing the same |
| CN102194873A (en) * | 2010-03-10 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Semiconductor device having multi-thickness gate dielectric |
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