CN103137661B - 横向双扩散金属氧化物半导体器件及其制造方法 - Google Patents
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Abstract
本发明公开的是配置为将集中到栅氧化膜的电场减小并将在器件进行向前动作时所产生的导通电阻降低的LDMOS器件及其制造方法。更具体地，当将n‑漂移区形成在P‑型基底上时，通过外延工艺将p‑基体形成在n‑漂移区上，然后将该p‑基体区域部分蚀刻，以形成为多个p‑外延层，使得当器件执行用于阻断反向电压的动作时，在包括n‑漂移区与p‑基体之间的接合面的p‑外延层与n‑漂移区的接合面之间形成耗尽层。
Description
技术领域
本发明涉及横向双扩散金属氧化物半导体(LDMOS)器件及其制造方法。更具体地，本发明涉及配置成将集中至栅氧化膜的电场减小并将在器件进行向前动作(forwardaction)时产生的导通电阻降低的LDMOS器件及其制造方法。
背景技术
近来，随着采用一个或更多功率半导体器件的装置和应用装置在尺寸和电容方面趋向于变得越来越大，对例如绝缘栅双极晶体管(IGBT)或金属氧化物半导体场效应晶体管(MOSFET)的功率半导体器件存在高要求。此外，还对高效功率半导体器件存在高要求。
在上述功率半导体器件中，适用于集成电路的LDMOS型功率器件具有现有MOS器件的沟道区，和能够耐受高击穿电压的低浓度漂移区。具体地，由于在LDMOS型功率器件工作时可以将高达数百伏的高电压施加到漏极，所以漂移区应当保持高击穿电压，并且在沟道区与漏极之间的导通电压应当较低。因此，为了获得漂移区高击穿电压和低导通电阻，开发了具有降低表面电场(RESURF)结构的器件，其中RESURF结构能够降低表面电场。
具有RESURF结构的常规功率器件涉及具有其中源电极从源极区域延伸到部分漂移区的源场板结构的器件、具有其中源电极从栅极区域延伸到部分漂移区的栅场板结构的器件、以及具有其中p-型杂质被注入到n-型漂移区表面中的结构的器件。然而，上述常规功率器件不能同时实现高击穿电压和低导通电阻。
作为高电压功率器件的LDMOS晶体管具有快速开关速度、高输入阻抗、低功率消耗、与互补金属氧化物半导体(CMOS)工艺的兼容性等，并且在显示器驱动集成电路(ICs)、功率变换器、电动机控制器、汽车电源等中广泛使用。在这种功率器件中，比导通电阻(specific ON-resistance)和击穿电压是关键因素，器件的性能通过其大大地受到影响。如此，已提出各种技术用于在保持导通电阻的同时增大击穿电压。
图6是示出常规LDMOS晶体管结构的横截面视图。在图6中，LDMOS晶体管在P-型基底100中包括用作LDMOS晶体管漂移区的深n-漂移区102、将在顶部形成有LDMOS晶体管的沟道的p-基体(body)104、n+源极106和漏极108、用于基体接触的p+源极110、具有硅的局部氧化(LOCOS)结构的场氧化膜112、栅氧化膜114、漏电极116、和源电极118。
在这种常规LDMOS晶体管中，n-漂移区的长度(LD)和掺杂浓度是用于确定器件的导通电阻和击穿电压的重要因素。即，当图6中由箭头所示的n-漂移区的长度LD增大时，击穿电压增大并且导通电阻也增大，并且当漂移区的浓度增大时，导通电阻降低并且击穿电压也降低。换句话说，漂移区的长度与浓度之间具有互为消长的关系。结果，采用这种常规LDMOS晶体管结构，难以增大击穿电压而不增大导通电阻。
许多报道表明通过在LDMOS晶体管的漂移区中形成由氧化物代替硅的局部氧化(LOCSO)作为场氧化膜所填充的沟槽可以提高击穿电压。例如，LDMOS晶体管已经发展，其通过在LDMOS晶体管的漂移区中经由硅沟槽蚀刻、氧化膜填缝和化学机械抛光(CMP)代替LOCOS形成沟槽而表现出击穿电压提高而不增大导通电阻(Won-So Son,Young-Ho Sohnand Sie-young Choi,“SOI RESURF LDMOS transistor using trench filled withoxide”,Electronics Letters,Vol.39,pp.1760-1761(2003))。
然而，由于在以上工艺中所涉及的相当复杂的步骤，例如形成这种沟槽结构所需的CMP，所以整个工艺变得比工业中期望的大多数工艺更加复杂和昂贵。
发明内容
本发明提供具有新结构的LDMOS器件，其中在n-漂移区形成在P-型基底上的状态下，通过外延工艺在该n-漂移区上形成p-基体。接着，将p-基体区域部分地蚀刻以形成多个p-外延层，使得当器件执行用于阻断反向电压的动作时，耗尽层形成在p-外延层与n-漂移区的接合面之间，其中所述接合面包括n-漂移区与p-基体之间的接合面。本发明的另一方面是提供用于制造这种LDMOS器件的方法。
一方面，本发明提供横向双扩散金属氧化物半导体器件，包括：在P-型基底上形成的n-漂移区；在n-漂移区顶部的一侧形成的p-基体；在n-漂移区顶部的另一侧形成的多个p-外延层；通过向p-基体注入N-型和P-型离子而形成的n+源极和p+源极；在n-漂移区上的外延层的一侧处形成的n+漏极；在p-基体的一个端部与各个p-外延层的一个端部之间的空间内形成并且形成为将各个p-外延层封装的场氧化膜；在场氧化膜的沟槽部分中形成的栅氧化膜；在n+源极和p+源极上形成的源电极；以及在n+漏极上形成的漏电极。
另一方面，本发明提供用于制造横向双扩散金属氧化物半导体器件的方法，包括：在n-漂移区形成在P-型基底上的状态下通过外延工艺在n-漂移区上形成p-基体；通过部分蚀刻p-基体形成与p-基体一起布置成“梳”状的多个p-外延层；通过向p-基体注入N-型和P-型离子形成包括n+源极和p+源极的源极区域，并且通过向n-漂移区注入N-型和P-型离子在n-漂移区上形成包括n+漏极和漏极区域；以及在p-基体的一个端部与各个p-外延层的一个端部之间的空间内形成场氧化膜，并且在场氧化膜的沟槽部分内形成栅氧化膜。
有利地，当n-漂移区形成在P-型基底上时，将p-基体外延形成在n-漂移区上，然后p-基体区域被部分蚀刻以形成多个p-外延层，使得当本发明的示例说明的实施方式中的半导体器件进行反向电压阻断操作时，在p-外延层与n-漂移区的接合面之间以及在n-漂移区与p-基体的接合面之间形成一个或更多耗尽层。结果，可以降低集中到栅氧化膜的电场，同时降低操作的复杂性。
此外，由于可以增大n-漂移区的掺杂浓度，因此本发明的示例说明的实施方式还降低在本发明的半导体器件进行向前动作时所产生的导通电阻。
附图说明
现在将参考附图图示的本发明的某些示例性实施方式来详细地描述本发明的上述和其它特征，下文给出的这些实施方式仅仅用于示例说明，因此不是对本发明的限制，其中：
图1是示出本发明的LDMOS器件的透视图；
图2是沿图1中的A-A线截取的横截面视图；
图3是沿图1中的B-B线截取的横截面视图；
图4是沿图1中的C-C线截取的横截面视图；
图5是示出本发明的LDMOS器件的制造工艺的横截面视图；
图6是示出常规LDMOS晶体管结构的横截面视图。
具体实施方式
下面将详细地参照本发明的各个实施方式，其实施例图示在所附附图中，并在下文加以描述。
首先，将参照图5描述制造碳化硅横向MOSFET器件的方法，以帮助理解本发明。当在单晶半导体基底即P-型基底10上形成用作漂移区的n-漂移区时，将p-基体14外延形成在n-漂移区12上(参见图5a)。接着，采用常规蚀刻工艺将p-基体14蚀刻成梳状，以在p-基体14中形成多个p-外延层16。P-基体14与p-外延层16在横向方向上彼此分离，并且p-外延层16在纵向方向上彼此分离(参见图1和5b)。
接着，采用离子注入掩模向p-基体14注入N-型和P-型离子，从而形成包括n+源极18和p+源极20的源极区域，并且同时，将N-型和P-型离子注入到在外延层16的一侧处暴露的n-漂移区12，从而形成包括n+漏极的漏极区域(参见图1和5c)。
随后，在除n+源极18的部分顶面和一个侧面、p-基体14的一个侧面、n-漂移区12的整个暴露的表面、以及各个p-外延层16的一个端部的整个表面之上形成场氧化膜24，并且在沟槽部分以及场氧化膜24的部分顶面之上形成栅氧化膜26(参见图1和5d)。通过本领域公知的后序工艺，在n+源极18和p+源极20上形成源电极28，并在n+漏极上形成漏电极30，由此完成本发明的示例说明的实施方式的横向MOSFET器件(参见图1和5e)。
现在，将参考图1至4更详细地描述以上述顺序制造的本发明的MOSFET器件的个别部件的特征和形成步骤。与在LDMOS晶体管中将由氧化物代替LOCOS作为场氧化物而填充的沟槽形成在n-漂移区中的现有方法不同，在示例说明的的示例性MOSFET器件即LDMOS器件中，采用外延工艺而非现有的离子注入工艺在n-漂移区12上形成p-基体14，接着将p-基体14以如下方式进行部分蚀刻，即除p-基体14外还将多个外延层14形成为沿着纵向方向呈间隔地布置成梳状，如图4所示。
此外，如图2和3所示，在形成p-外延层16之后，通过注入N-型和P-型离子将包括n+源极18和p+源极的源极区域形成在p-基体14上，并且通过注入N-型和P-型离子将包括n+漏极22的漏极区域形成于在外延层16的一侧处暴露的n-漂移区12上。
此时，在对部分p-基体14进行蚀刻的过程中，部分蚀刻n-漂移区12的顶部，以形成比p-基体14的一侧的高度与n+源极18的一侧的高度的总和更深，并且比p-外延层16的高度更深的沟道，使得包括场氧化膜24和栅氧化膜26的栅电极可以容易地形成在沟道中。栅氧化膜可以由多晶硅形成。
具体地，如上所述通过对部分p-基体14进行蚀刻在源极区域和漏极区域之间将与n-漂移区12接合的多个p-外延层形成为沿纵向方向的梳状布置。当器件的反向电压被阻断时，在p-外延层16与n-漂移区12的接合面之间形成一个或更多耗尽层，其中各个所述p-外延层16均为P-型半导体外延层，并且所述n-漂移区12是N-型半导体外延层。
而且，除了在p-型外延层16与n-漂移区12的接合面之间形成的耗尽层，在P-型基底10与n-漂移区12的接合面之间也制备出一个或更多耗尽层，其中所述n-漂移区12是N-型半导体外延层。此外，在场介电层中即在场氧化膜24与作为N-型半导体外延层的n-漂移区12之间，出现介电RESURF，并且在n-漂移区12与P-型基底10之间形成超级结结构。
因此，由于当n-漂移区12具有高掺杂浓度时n-漂移区12会整个形成耗尽层，因此可以获得高击穿电压，并且通过具有高掺杂浓度的n-漂移区12，可以同时降低导通电阻。
此时，假定N-漂移区12的厚度是tn并且掺杂浓度是Ndrift，则n-漂移区的电荷总量可以采用下面的式1计算。
Qn＝tn×Ndrift……(1)
优选地，为了将n-漂移区12整个形成为耗尽层，应当对n-漂移区的厚度和掺杂浓度进行适当选择并对电荷总量进行良好控制，从而通过超级结和RESURF效应使击穿电压最大化。
本发明参考其示例性实施方式进行了详细描述。然而，本领域技术人员能够理解，可以在不偏离本发明的原理和精神的情况下对这些实施方式进行改变，本发明的范围由所附的权利要求及其等同方式限定。
Claims (4)
1.一种横向双扩散金属氧化物半导体器件，包括：
在P-型基底上形成的n-漂移区；
在所述n-漂移区顶部表面的一侧形成的p-基体的第一部分；
在所述n-漂移区顶部表面的另一侧，由部分蚀刻的p-基体的第二部分形成的多个p-外延层；
通过向所述p-基体注入N-型和P-型离子而形成的n+源极和p+源极；
在所述n-漂移区上的所述外延层的一侧处形成的n+漏极；
在所述p-基体的一个端部与各个所述p-外延层的一个端部之间的空间内形成并且形成为将各个所述p-外延层封装的场氧化膜；
在所述场氧化膜的沟槽部分中形成的栅氧化膜；
在所述n+源极和所述p+源极上形成的源电极；以及
在所述n+漏极上形成的漏电极。
2.如权利要求1所述的器件，其中所述p-外延层沿与所述p-基体垂直的纵向方向呈间隔地布置成梳状。
3.如权利要求1所述的器件，其中在除所述n+源极的部分顶面和一个侧面、所述p-基体的一个侧面、所述n-漂移区的暴露表面以及各个所述p-外延层的一个端部的整个表面之上形成所述场氧化膜。
4.如权利要求1所述的器件，其中在所述p-外延层与所述n-漂移区的接合面之间形成耗尽层，所述接合面包括所述n-漂移区与所述p-基体之间的接合面。
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