CN102842596A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN102842596A CN102842596A CN2011101768715A CN201110176871A CN102842596A CN 102842596 A CN102842596 A CN 102842596A CN 2011101768715 A CN2011101768715 A CN 2011101768715A CN 201110176871 A CN201110176871 A CN 201110176871A CN 102842596 A CN102842596 A CN 102842596A
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region, wherein the dielectric structure is arranged above the well region; the dielectric structure is provided with a first dielectric lateral side and a second dielectric lateral side which are arranged oppositely; the dielectric structure comprises a first dielectric part and a second dielectric part which are arranged between the first dielectric lateral side and the second dielectric lateral side; the first doped layer is arranged above the well region between the first dielectric part and the second dielectric part; the second doped layer is arranged above the first doped layer; the first doped layer is arranged inside the well region on the first dielectric lateral side; the well region, the first doped layer and the first doped region are of the first conductive type; the second doped layer is of the second conductive type opposite to the first conductive type; and the semiconductor structure comprises a high-voltage-resisting schottky diode.
Description
Technical field
The invention relates to semiconductor structure and manufacturing approach thereof, particularly relevant for high voltage semiconductor device and manufacturing approach thereof.
Background technology
The semiconductor industry continues to dwindle the size of semiconductor structure, and improves the unit cost of speed, usefulness, density and integrated circuit simultaneously.For instance, the diode in the semiconductor structure for example Schottky diode can be applicable to asynchronous device.General Schottky diode has Metal Contact, an oxide spacer and the N type heavy doping part that is formed on the N type substrate.Be positioned at single Metal Contact and the N type heavy doping part on the substrate on the relative both sides of oxide spacer and be electrically connected to anode and negative electrode respectively.
Asynchronous device generally has two power metal oxide-semiconductor field-effect transistors (powerMOSFET), is configured in high side and downside respectively.The configurable MOSFET at downside of Schottky diode is to reduce the transfer power loss of device in direct current step-down conversion (buck DC to DC conversion).Yet general Schottky diode has the leakage current that has a strong impact on device usefulness under reverse biased, and this leakage current is the loss that causes power on the circuit.For example please with reference to Fig. 1, general Schottky diode is under reverse biased, and leakage current can linearly along with the rising of voltage uprise gradually, and general Schottky diode can not collapse.Therefore when being applied to high-pressure installation, the voltage level (voltage level) of general Schottky diode squints.
Summary of the invention
The invention relates to semiconductor structure and manufacturing approach thereof.Semiconductor structure has the element that utilizes the RESURF notion on the drift region between two dielectric part separated from each other, but so operating voltage of lifting device.The part that semiconductor structure and anode electrically connect has folder and ends element, therefore can reduce device leakage current.Semiconductor structure can be applicable in the high-pressure installation.Semiconductor structure can comprise high pressure resistant Schottky diode.
A kind of semiconductor structure is provided.Semiconductor structure comprises a well region, a dielectric structure, one first doped layer, one second doped layer and one first doped region.Dielectric structure is positioned on the well region.Dielectric structure has one first relative dielectric side and one second dielectric side.Dielectric structure comprises one first dielectric part and one second dielectric part, between the first dielectric side and the second dielectric side.First doped layer is on the well region between first dielectric part and second dielectric part.Second doped layer is positioned on first doped layer.First doped region is arranged in the well region on the first dielectric side.Well region, first doped layer and first doped region have one first conductivity type.Second doped layer has one second conductivity type in contrast to first conductivity type.One negative electrode is electrically connected to first doped region.One anode is electrically connected to the well region on the second dielectric side.
A kind of semiconductor structure also is provided.Semiconductor structure comprises a well region, a dielectric structure, one first doped region, one second doped region and one the 3rd doped region.Dielectric structure is positioned on the well region.Dielectric structure has one first relative dielectric side and one second dielectric side.First doped region is arranged in the well region on the first dielectric side.Second doped region and the 3rd doped region are arranged in the well region on the second dielectric side.The well region and first doped region have one first conductivity type.Second doped region and the 3rd doped region have one second conductivity type in contrast to first conductivity type.One negative electrode is electrically connected to first doped region.One anode is electrically connected to well region, second doped region and the 3rd doped region between second doped region and the 3rd doped region.
A kind of manufacturing approach of semiconductor structure is provided.Method may further comprise the steps.Form a dielectric structure on a well region.Dielectric structure has one first relative dielectric side and one second dielectric side.Dielectric structure comprises one first dielectric part and one second dielectric part, between the first dielectric side and the second dielectric side.Form one first doped layer.First doped layer is on the well region between first dielectric part and second dielectric part.Form one second doped layer on first doped layer.Form one first doped region.First doped region is arranged in the well region on the first dielectric side.Well region, first doped layer and first doped region have one first conductivity type.Second doped layer has one second conductivity type in contrast to first conductivity type.
A kind of manufacturing approach of semiconductor structure is provided.Method may further comprise the steps.Form a dielectric structure on a well region.Dielectric structure has one first relative dielectric side and one second dielectric side.Form one first doped region.First doped region is arranged in the well region on the first dielectric side.Form one second doped region and one the 3rd doped region.Second doped region and the 3rd doped region are arranged in the well region on the second dielectric side.Second doped region and the 3rd doped region are separated from each other through well region.The well region and first doped region have one first conductivity type.Second doped region and the 3rd doped region have one second conductivity type in contrast to first conductivity type.
Hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 is the I-V curve of general semiconductor device under reverse biased.
Fig. 2 illustrates according to the semiconductor structure of an embodiment and manufacturing approach thereof.
Fig. 3 illustrates the I-V curve of device under forward bias voltage drop among the embodiment.
Fig. 4 illustrates the I-V curve of device under reverse biased.
Fig. 5 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 6 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 7 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 8 illustrates the profile according to the semiconductor structure of an embodiment.
Fig. 9 illustrates the top view according to the semiconductor structure of an embodiment.
Figure 10 illustrates the top view according to the semiconductor structure of an embodiment.
Figure 11 illustrates the profile according to the semiconductor structure of an embodiment.
Figure 12 illustrates the profile according to the semiconductor structure of another embodiment.
[main element symbol description]
1,801: substrate
2,102,202,302,502,702,802: well region
4,104,304: the first dielectric part
6,106,306: the second dielectric part
8: the first dielectric sides
10: the second dielectric sides
12: the first doped regions
14: the second doped regions
16: the three doped regions
18,20,22 heavy doping parts
24,124,224,324,424,624: the first doped layers
26,126,226,326,426,626: the second doped layers
28: grid structure
30: negative electrode
32: anode
34: Metal Contact
303,203: the doping striped
305: the dielectric striped
407,507,607: the dielectric island
736: buried horizon
838: deep is isolated
Embodiment
Fig. 2 illustrates according to the semiconductor structure of an embodiment and manufacturing approach thereof.Please, a substrate 1 is provided with reference to Fig. 2.Substrate 1 can comprise piece silicon, silicon-on-insulator or other suitable semi-conducting material.Substrate 1 also can be the doped well region in the base material.Perhaps, substrate 1 also can be with extension or the p-n film that forms of vapour deposition process for example.On substrate 1, form well region 2.Form in the well region 2 of first doped region 12 on the first dielectric side 8.Form in the well region 2 of second doped region 14 on the second dielectric side 10.Also form in the well region 2 of the 3rd doped region 16 on the second dielectric side 10.
Please, on well region 2, form dielectric structure, comprise first dielectric part 4 and second dielectric part 6 with reference to Fig. 2.Dielectric structure can comprise for example silica of oxide.First dielectric part 4 and second dielectric part 6 are not limited to field oxide as shown in Figure 2, also can comprise shallow trench isolation.First dielectric part 4 and second dielectric part 6 have respectively mutually away from the first dielectric side 8 and the second dielectric side 10.Form first doped layer 24 on the well region 2 between first dielectric part 4 and second dielectric part 6.Form second doped layer 26 on first doped layer 24.In embodiment, well region 2, first doped layer 24, first doped region 12 have first conductivity type with heavy doping part 18.Second doped region 14, the 3rd doped region 16, heavy doping part 20, heavy doping part 22 and first doped layer 26 have second conductivity type in contrast to first conductivity type.For instance, first conductivity type is the N type, and second conductivity type is the P type.
Please, can form grid structure 28 on second doped region 14 and well region 2, and extend on second dielectric part 6 with reference to Fig. 2.Grid structure 28 can comprise gate dielectric layer and gate electrode layer.Gate electrode layer is formed on the gate dielectric layer.Gate electrode layer can comprise metal or silicon for example polysilicon or metal silicide.
Please with reference to Fig. 2, negative electrode 30 can via between be electrically connected to first doped region 12 with Metal Contact 34 for the heavy doping part 18 of ohmic contact.Anode 32 can be electrically connected to grid structure 28 through the Metal Contact 34 that ohmic contact is provided.Anode 32 also can via between be electrically connected to second doped region 14 and the 3rd doped region 16 for heavy doping part 20 of ohmic contact, heavy doping part 22 and Metal Contact 34.Anode 32 also can be electrically connected to the well region 2 between second doped region 14 and the 3rd doped region 16 via Metal Contact 34, can form schottky junction between Metal Contact 34 and the well region 2.
Please with reference to Fig. 2, in embodiment, semiconductor structure can comprise for example lateral direction schottky diode (lateral Schottky diode) of diode.First doped layer 24 and second doped layer 26 that are formed on the drift region between first dielectric part 4 and second dielectric part 6 are to use the RESURF notion, but therefore the Schottky of lifting device collapses (Schottky breakdown) and can bear high operating voltage.In addition, device has low Schottky barrier (Schottky Barrier).Embodiment is not limited to the double-deck RESURF structure with first doped layer 24 and second doped layer 26 as shown in Figure 2, also can be the RESURF structure of other multilayer.Second doped region 14 and the 3rd doped region 16 can form folder and end element, in order to vague and general well region 2 between second doped region 14 and the 3rd doped region 16.Therefore device can have low-leakage current.
Fig. 3 illustrates the I-V curve of device under forward bias voltage drop among the embodiment.Fig. 4 illustrates the I-V curve of device under reverse biased.Please with reference to Fig. 3, device has the two-part conducting resistance under forward bias voltage drop.The turning point of resistance change is about 0.2V (Schottky diode conducting) and 0.55V (PN type diode current flow).Please with reference to Fig. 4, the operating voltage below about 350V, device have low leakage current.Therefore, the semiconductor structure of embodiment can comprise Schottky diode and PN type diode.
Fig. 5 illustrates the top view according to the semiconductor structure of an embodiment.Please with reference to Fig. 5, first doped layer 124 and second doped layer 126 extend on the whole well region 102 between first dielectric part 104 and second dielectric part 106.In an embodiment, form first dielectric part 104 and second dielectric part 106, mixing as mask layer and to well region 102 with first dielectric part 104 and second dielectric part 106 then forms first doped layer 124 and second doped layer 126.Therefore the formation of first doped layer 124 and second doped layer 126 does not involve the point-device mask of pattern.The formation method is simple and can reduce manufacturing cost.
Fig. 6 illustrates the top view according to the semiconductor structure of an embodiment.Please with reference to Fig. 6, first doped layer 224 and second doped layer 226 are to be divided into doping striped 203 separated from each other through well region 202.
Fig. 7 illustrates the top view according to the semiconductor structure of an embodiment.Please, form dielectric striped 305, extend between first dielectric part 304 and second dielectric part 306 with reference to Fig. 7.Dielectric striped 305 is divided into doping striped 303 separated from each other with first doped layer 324 and second doped layer 326.In an embodiment; Form first dielectric part 304, second dielectric part 306 and dielectric striped 305, mix as mask layer and to well region 302 with dielectric striped 305 and form the doping striped 303 that comprises first doped layer 324 and second doped layer 326 with first dielectric part 304, second dielectric part 306 then.Therefore the formation of first doped layer 324 and second doped layer 326 does not involve the point-device mask of pattern.The formation method is simple and can reduce manufacturing cost.
Fig. 8 illustrates the profile according to the semiconductor structure of an embodiment.Please, form dielectric island 407 in first doped layer 424 and second doped layer 426 with reference to Fig. 8.Dielectric island 407 can comprise for example silica of oxide.Dielectric island 407 is not limited to field oxide as shown in Figure 8, also can comprise shallow trench isolation.Fig. 9 illustrates the top view according to the semiconductor structure of an embodiment.Please with reference to Fig. 9, dielectric island 507 extends on the well region 502.Figure 10 illustrates the top view according to the semiconductor structure of an embodiment.Please with reference to Figure 10, dielectric island 607 can suitably be configured in first doped layer 624 and second doped layer 626 according to the equipment energy characteristic of expectation.
Figure 11 illustrates the profile according to the semiconductor structure of an embodiment.The difference of semiconductor structure shown in Figure 11 and semiconductor structure shown in Figure 2 is that buried horizon 736 is formed on the well region 702.In embodiment, well region 702 is to have opposite conductivity type respectively with buried horizon 736.Use buried horizon 736 can improve the operating voltage of device.Figure 12 illustrates the profile according to the semiconductor structure of another embodiment.The difference of semiconductor structure shown in Figure 12 and semiconductor structure shown in Figure 11 is that deep is isolated 838 and is formed in the substrate 801.Use deep isolation 838 also can improve the operating voltage of device.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Anyly be familiar with this art; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defined.
Claims (10)
1. semiconductor structure comprises:
One well region;
One dielectric structure is positioned on this well region, and has one first relative dielectric side and one second dielectric side, and wherein this dielectric structure comprises one first dielectric part and one second dielectric part, between this first dielectric side and this second dielectric side;
One first doped layer is on this well region between this first dielectric part and this second dielectric part;
One second doped layer is positioned on this first doped layer; And
One first doped region; Be arranged in this well region on this first dielectric side; Wherein this well region, this first doped layer and this first doped region have one first conductivity type; This second doped layer has one second conductivity type in contrast to this first conductivity type, and a negative electrode is electrically connected to this first doped region, and an anode is electrically connected to this well region on this second dielectric side.
2. semiconductor structure according to claim 1 more comprises a dielectric island, is arranged in this first doped layer and this second doped layer.
3. semiconductor structure according to claim 1, wherein this first doped layer and this second doped layer are to be divided into a plurality of doping stripeds separated from each other through this well region.
4. semiconductor structure according to claim 1 more comprises a dielectric striped, extends between this first dielectric part and this second dielectric part, and this first doped layer and this second doped layer are divided into a plurality of doping stripeds separated from each other.
5. semiconductor structure according to claim 1, wherein this semiconductor structure comprises Schottky diode and PN type diode.
6. semiconductor structure comprises:
One well region;
One dielectric structure is positioned on this well region, and has one first relative dielectric side and one second dielectric side;
One first doped region is arranged in this well region on this first dielectric side; And
One second doped region and one the 3rd doped region; Be arranged in this well region on this second dielectric side; Wherein, this well region and this first doped region have one first conductivity type, and this second doped region and the 3rd doped region have one second conductivity type in contrast to this first conductivity type; One negative electrode is electrically connected to this first doped region, and an anode is electrically connected to this well region, this second doped region and the 3rd doped region between this second doped region and the 3rd doped region.
7. semiconductor structure according to claim 6, wherein this semiconductor structure comprises Schottky diode and PN type diode.
8. the manufacturing approach of a semiconductor structure comprises:
Form a dielectric structure on a well region; Wherein this dielectric structure has one first relative dielectric side and one second dielectric side; This dielectric structure comprises one first dielectric part and one second dielectric part, between this first dielectric side and this second dielectric side;
Form one first doped layer, wherein this first doped layer is on this well region between this first dielectric part and this second dielectric part;
Form one second doped layer on this first doped layer; And
Form one first doped region; Wherein this first doped region is arranged in this well region on this first dielectric side; This well region, this first doped layer and this first doped region have one first conductivity type, and this second doped layer has one second conductivity type in contrast to this first conductivity type.
9. the manufacturing approach of semiconductor structure according to claim 8; More comprise and form a plurality of dielectric stripeds; Wherein these a plurality of dielectric stripeds extend between this first dielectric part and this second dielectric part, and this first doped layer is formed on this well region between these a plurality of dielectric stripeds.
10. the manufacturing approach of a semiconductor structure comprises:
Form a dielectric structure on a well region, wherein this dielectric structure has one first relative dielectric side and one second dielectric side;
Form one first doped region, wherein this first doped region is arranged in this well region on this first dielectric side;
Form one second doped region and one the 3rd doped region; Wherein this second doped region and the 3rd doped region are arranged in this well region on this second dielectric side; This second doped region and the 3rd doped region are separated from each other through this well region; This well region and this first doped region have one first conductivity type, and this second doped region and the 3rd doped region have one second conductivity type in contrast to this first conductivity type.
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| CN201110176871.5A CN102842596B (en) | 2011-06-22 | 2011-06-22 | Semiconductor structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000600A1 (en) * | 2014-06-30 | 2016-01-07 | 无锡华润上华半导体有限公司 | Junction field effect transistor and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7180132B2 (en) * | 2004-09-16 | 2007-02-20 | Fairchild Semiconductor Corporation | Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region |
| US20070102725A1 (en) * | 2002-11-14 | 2007-05-10 | Stmicroelectronics, S.R.L. | Insulated gate planar integrated power device with co-integrated Schottky diode and process |
| CN1977389A (en) * | 2004-06-30 | 2007-06-06 | 飞思卡尔半导体公司 | Schottky device and method of forming |
| KR20070070413A (en) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | Schottky barrier diode with enhanced electrical characreristic |
| CN102017162A (en) * | 2008-04-23 | 2011-04-13 | 飞兆半导体公司 | Integrated low leakage schottky diode |
-
2011
- 2011-06-22 CN CN201110176871.5A patent/CN102842596B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070102725A1 (en) * | 2002-11-14 | 2007-05-10 | Stmicroelectronics, S.R.L. | Insulated gate planar integrated power device with co-integrated Schottky diode and process |
| CN1977389A (en) * | 2004-06-30 | 2007-06-06 | 飞思卡尔半导体公司 | Schottky device and method of forming |
| US7180132B2 (en) * | 2004-09-16 | 2007-02-20 | Fairchild Semiconductor Corporation | Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region |
| KR20070070413A (en) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | Schottky barrier diode with enhanced electrical characreristic |
| CN102017162A (en) * | 2008-04-23 | 2011-04-13 | 飞兆半导体公司 | Integrated low leakage schottky diode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000600A1 (en) * | 2014-06-30 | 2016-01-07 | 无锡华润上华半导体有限公司 | Junction field effect transistor and manufacturing method therefor |
| US9947785B2 (en) | 2014-06-30 | 2018-04-17 | Csmc Technologies Fab1 Co., Ltd. | Junction field effect transistor and manufacturing method therefor |
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| CN102842596B (en) | 2015-05-20 |
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