CN105097889A - Terminal structure of semiconductor element, and manufacturing method thereof - Google Patents
Terminal structure of semiconductor element, and manufacturing method thereof Download PDFInfo
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- CN105097889A CN105097889A CN201410200466.6A CN201410200466A CN105097889A CN 105097889 A CN105097889 A CN 105097889A CN 201410200466 A CN201410200466 A CN 201410200466A CN 105097889 A CN105097889 A CN 105097889A
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Abstract
The invention provides a terminal structure of a semiconductor element, and a manufacturing method thereof. The semiconductor element includes an active zone and a terminal zone adjacent to the active zone, wherein the terminal zone has a terminal structure. The terminal structure includes a substrate, an epitaxy layer, dielectric layers, conductive material layers and a conductive layer. The epitaxy layer is disposed on the substrate, and has a voltage resistance zone. The voltage resistance zone is equipped with multiple grooves, and the grooves are parallel to each other. The dielectric layers are disposed in the grooves and on part of the epitaxy layer. The conductive material layers are disposed on the dielectric layers in the grooves. The conductive layer covers the grooves, is in contact with the conductive material layers and part of the epitaxy layer, and is in electric connection with the active zone and the terminal zone.
Description
Technical field
The invention relates to a kind of terminal structure of semiconductor element, particularly about a kind of terminal structure and the manufacture method thereof with many grooves.
Background technology
In power semiconductor, proof voltage ability is very important index.For example, because general plough groove type field-effect transistor possesses the characteristics such as high withstand voltage ability, low on-resistance and high electric current, therefore plough groove type field-effect transistor has been widely used in electric power controller as power semiconductor.
Make above-mentioned plough groove type field-effect transistor and usually need complicated and repeatedly optical cover process, processing time and opportunities for contamination will be increased, the yield of power semiconductor and production capacity are restricted.
On the other hand, general plough groove type field-effect transistor has the terminal structure of larger area, to promote breakdown voltage.But for the electronic component development trend of current volume microminiaturization, it is obviously outdated that this type of has large-area terminal structure.
Summary of the invention
An aspect of of the present present invention is the terminal structure providing a kind of semiconductor element.This semiconductor element comprises active region and termination environment, and termination environment is adjacent with active region.Termination environment has above-mentioned terminal structure, and terminal structure comprises substrate, epitaxial layer, dielectric layer, conductive material layer and conductive layer.
Epitaxial layer is arranged on substrate, and has a withstand voltage zone.Withstand voltage zone has multiple first groove (trench), and wherein the first groove extends along first direction.Dielectric layer is arranged in all first grooves and on part epitaxial layer.Conductive material layer is arranged on the dielectric layer in all first grooves.Conductive layer covers all first grooves, contact conductive material layer and part epitaxial layer, and is electrically connected above-mentioned active region.
Another aspect of the present invention is the manufacture method of the terminal structure providing a kind of semiconductor element.This semiconductor element comprises active region and termination environment, and termination environment is adjacent with active region and have terminal structure.This manufacture method comprises formation epitaxial layer on base material, and epitaxial layer has a withstand voltage zone; Form multiple groove in the withstand voltage zone of epitaxial layer, wherein groove extends along first direction and is arranged in parallel with each other; Form dielectric layer in each groove; Formed on the dielectric layer of conductive material layer in each groove; And form conductive layer on each groove, conductive layers make contact conductive material layer and part epitaxial layer.
Dielectric layer due to each groove is interconnected, and increases, can bear higher breakdown voltage in less area through groove structure, and therefore the terminal structure of semiconductor element provided by the present invention can dramatically the breakdown voltage promoting integral member.
Accompanying drawing explanation
Figure 1A is the profile of the semiconductor element 100 illustrated according to embodiments of the invention;
Figure 1B be according to embodiments of the invention illustrate the section top view of semiconductor element along A-A ' hatching of Figure 1A;
Fig. 2 be according to embodiments of the invention illustrate the profile of semiconductor element 200;
Fig. 3 A be according to embodiments of the invention illustrate the profile of semiconductor element 300;
Fig. 3 B be according to embodiments of the invention illustrate the section top view of semiconductor element along B-B ' hatching of Fig. 3 A;
Fig. 4 A be according to embodiments of the invention illustrate the profile of semiconductor element 400a;
Fig. 4 B be according to embodiments of the invention illustrate the top view of semiconductor element 400a;
Fig. 4 C be according to embodiments of the invention illustrate the top view of groove 431b in semiconductor element 400b;
Fig. 4 D is the section top view of the semiconductor element 400b illustrated according to embodiments of the invention;
Fig. 5 A ~ Fig. 5 J is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention;
Fig. 6 A ~ Fig. 6 F is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention;
Fig. 7 is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention; And
Fig. 8 is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention.
Embodiment
Terminal structure and the manufacture method thereof of proposed by the invention is a kind of semiconductor element, it can be applicable to the groove type power semiconductor component as groove type gold oxygen half Schottky energy barrier diode (TMBSdiode), plough groove type insulated gate bipolar transistor (TrenchIGBT) or trench power metal-oxide semiconductor field-effect transistor (TrenchPowerMOSFET) and so on.Below enumerate several embodiment so that terminal structure and the manufacture method thereof of semiconductor element of the present invention to be described.
Figure 1A is the profile of the semiconductor element 100 illustrated according to embodiments of the invention.In figure ia, semiconductor element 100 comprises active region 101 and termination environment 102, and termination environment 102 is adjacent with active region 101.Termination environment 102 has terminal structure, and terminal structure comprises substrate 110, epitaxial layer 120, dielectric layer 132, conductive material layer 133 and conductive layer 140.
Epitaxial layer 120 is arranged on substrate 110, and have withstand voltage zone 130.Withstand voltage zone 130 is positioned near the trench semiconductor unit 103 of active region 101, and has multiple first groove 131.According to one embodiment of the invention, substrate 110 can be silicon substrate.According to one embodiment of the invention, epitaxial layer 120 can be N-type epitaxial layer.According to embodiments of the invention, the width of each first groove 131 can be not same design.According to embodiments of the invention, the width of each first groove 131 can be gradually wide or gradually narrow design.
Dielectric layer 132 is arranged in all first grooves 131 and on part epitaxial layer 120.According to one embodiment of the invention, dielectric layer 132 is made up of oxide.According to embodiments of the invention, the dielectric layer 132 in every two adjacent the first grooves 131 contacts with each other.
Conductive material layer 133 is arranged on the dielectric layer 132 in all first grooves 131.According to one embodiment of the invention, conductive material layer 133 is made up of polysilicon or metal.Its dielectric layer 132 and the large I of both conductive material layers 133 width are done in ratio according to actual required withstand voltage degree and are adjusted.
Conductive layer 140 covers all first grooves 131, contact conductive material layer 133 and part epitaxial layer 120, and is electrically connected above-mentioned active region 101 and termination environment 102.According to embodiments of the invention, conductive layer 140 is Schottky energy barrier metal level.
According to embodiments of the invention, terminal structure also comprises second dielectric-sandwiched between conductive layer and partially conductive material layer, and order makes conductive layer be electrically connected at conductive material layer in part first groove.Because inner layer dielectric layer is folded between conductive layer and partially conductive material layer, can makes and make conductive material layer have different potentials, different proof voltage effects is provided.
Figure 1B be according to embodiments of the invention illustrate the section top view of semiconductor element along A-A ' hatching of Figure 1A.In fig. ib, in terminal structure, the withstand voltage zone 130 of epitaxial layer 120 has the first groove 131.First groove 131 extends along a direction and is arranged in parallel with each other, and dielectric layer 132 and conductive material layer 133 are arranged in the first groove 131.
Fig. 2 is the profile of the semiconductor element 200 illustrated according to embodiments of the invention.In fig. 2, semiconductor element 200 comprises active region 201 and termination environment 202, and termination environment 202 is adjacent with active region 201.Termination environment 202 has terminal structure, and terminal structure comprises substrate 210, epitaxial layer 220, dielectric layer 232, conductive material layer 233 and conductive layer 240.
Epitaxial layer 220 is arranged on substrate 210, and have withstand voltage zone 230.Withstand voltage zone 230 is positioned near the trench semiconductor unit 203 of active region 201, and has multiple first groove 231.According to one embodiment of the invention, substrate 210 can be silicon substrate.According to one embodiment of the invention, epitaxial layer 220 can be N-type epitaxial layer.According to embodiments of the invention, the width of each first groove 231 can be not same design.According to embodiments of the invention, the width of each first groove 231 can be gradually wide or gradually narrow design.According to embodiments of the invention, the width at each groove interval 250 between each first groove 231 is not identical.According to embodiments of the invention, each groove interval between each first groove 231 250 is in gradually dredging or gradually solid matter row.
Dielectric layer 232 is arranged in all first grooves 231 and on part epitaxial layer 220.According to one embodiment of the invention, dielectric layer 232 is made up of oxide.According to embodiments of the invention, the dielectric layer 232 in every two adjacent the first grooves 231 separated by a groove interval 250.According to embodiments of the invention, each groove interval 250 between each first groove 231 also comprises doped region 251.According to embodiments of the invention, doped region 251 can be the doping of P type.Adding the doping of P type can prevent leakage current from occurring ahead of time from periphery, promotes breakdown voltage by this.
Conductive material layer 233 is arranged on the dielectric layer 232 in all first grooves 231.According to one embodiment of the invention, conductive material layer 233 is made up of polysilicon or metal.According to embodiments of the invention, the dielectric layer 232 in each first groove 231 and conductive material layer 233 have a planarized surface with epitaxial layer 220.Certain terminal structure also can carry out in non-flat forms mode, such as, in Figure 1A terminal structure also comprise the first dielectric layer 134 be arranged at above-mentioned dielectric layer 132 and conductive material layer 133 and epitaxial layer 120 forms on planarized surface, wherein the first dielectric layer 134 and dielectric layer 132 can be same step and formed.This first dielectric layer 134 is positioned on the dielectric layer 132 that contacts with each other between every two adjacent the first grooves 131.
Conductive layer 240 covers all first grooves 231, contact conductive material layer 233 and part epitaxial layer 220, and is electrically connected above-mentioned active region 201 and termination environment 202.According to embodiments of the invention, conductive layer 240 is Schottky energy barrier metal level.
Fig. 3 A is the profile of the semiconductor element 300 illustrated according to embodiments of the invention.In figure 3 a, semiconductor element 300 comprises active region 301 and termination environment 302, and termination environment 302 is adjacent with active region 301.Termination environment 302 has terminal structure, and terminal structure comprises substrate 310, epitaxial layer 320, dielectric layer 332, conductive material layer 333 and conductive layer 340.
Epitaxial layer 320 is arranged on substrate 310, and have withstand voltage zone 330.Withstand voltage zone 330 is adjacent with the trench semiconductor unit 303 of active region 301, and has multiple first groove 331.According to one embodiment of the invention, substrate 310 can be silicon substrate.According to one embodiment of the invention, epitaxial layer 320 can be N-type epitaxial layer.According to embodiments of the invention, the width of each first groove 331 is not identical.According to embodiments of the invention, the width of each first groove 331 can be gradually wide or gradually narrow.According to embodiments of the invention, the width at each groove interval 350 between each first groove 331 is not identical.According to embodiments of the invention, each groove interval between each first groove 331 350 is in gradually dredging or gradually solid matter row.
Dielectric layer 332 is arranged in all first grooves 331 and on part epitaxial layer 320.According to one embodiment of the invention, dielectric layer 332 is made up of oxide.According to embodiments of the invention, the dielectric layer 332 in every two adjacent the first grooves 331 separated by a groove interval 350.
Conductive material layer 333 is arranged on the dielectric layer 332 in all first grooves 331.According to one embodiment of the invention, conductive material layer 333 is made up of polysilicon or metal.According to embodiments of the invention, the dielectric layer 332 in each first groove 331 and part epitaxial layer 320 comprise one first dielectric layer 334.This first dielectric layer 334 is positioned at above the groove interval 350 between every two adjacent the first grooves 331, and the first dielectric layer 334 also expands to according to processing procedure change and is positioned at above the adjoining dielectric layer in groove interval 350 332 as shown in Figure 3A.
Conductive layer 340 covers all first grooves 331, contact conductive material layer 333 and part epitaxial layer 320, and is electrically connected above-mentioned active region 301 and termination environment 302.According to embodiments of the invention, conductive layer 340 is Schottky energy barrier metal level.
Fig. 3 B is the section top view of semiconductor element along B-B ' hatching of Fig. 3 A illustrated according to embodiments of the invention.In figure 3b, dielectric layer 332 and conductive material layer 333 are arranged in the first groove 331, and have groove interval 350 between every two adjacent the first grooves 331.
Fig. 4 A is the profile of the semiconductor element 400a illustrated according to embodiments of the invention.In Figure 4 A, semiconductor element 400a comprises active region 401 and termination environment 402, and termination environment 402 is adjacent with active region 401.Termination environment 402 has terminal structure, and terminal structure comprises substrate 410, epitaxial layer 420, dielectric layer 432, conductive material layer 433 and conductive layer 440.
Epitaxial layer 420 is arranged on substrate 410, and have withstand voltage zone 430.Withstand voltage zone 430 is positioned near the trench semiconductor unit 403 of active region 401, and comprises more than one second groove 431a and extend along a direction.According to one embodiment of the invention, substrate 410 can be silicon substrate.According to one embodiment of the invention, epitaxial layer 420 can be N-type epitaxial layer.According to embodiments of the invention, the second groove 431a has the dielectric layer 332 identical with each first groove 331 in Fig. 3 A and conductive material layer 333.
Dielectric layer 432 is arranged in the second groove 431a and on part epitaxial layer 420.According to one embodiment of the invention, dielectric layer 432 is made up of oxide.
Conductive material layer 433 is arranged on the dielectric layer 432 in the second groove 431a.According to one embodiment of the invention, conductive material layer 433 is made up of polysilicon or metal.
Conductive layer 440 covers the second groove 431a, contact conductive material layer 433 and part epitaxial layer 420, and is electrically connected above-mentioned active region 401 and termination environment 402.According to embodiments of the invention, conductive layer 440 is Schottky energy barrier metal level.
Fig. 4 B be according to embodiments of the invention illustrate the section top view of semiconductor element.Wherein, Fig. 4 A is the profile of the C-C ' hatching along Fig. 4 B.In figure 4b, there is dielectric layer 332 and conductive material layer 333 and be positioned at the first groove 331 (figure does not indicate the first groove 331), dielectric layer 432 and conductive material layer 433 are positioned at the second groove 431a (figure does not indicate the first groove 431a), and in terminal structure, the withstand voltage zone 430 of epitaxial layer 420 has the first groove 331 and the second groove 431a.First groove 331 extends along first direction and is arranged in parallel with each other.Between every two adjacent the first grooves 331, there is groove interval 350.Second groove 431a extends along second direction.According to embodiments of the invention, the first direction of above-mentioned each first groove 331 and the second direction of the second groove 431a orthogonal thereto.
Fig. 4 C is the section top view of the groove 431b of the semiconductor element illustrated according to embodiments of the invention.In figure 4 c, in terminal structure, the withstand voltage zone 430 of epitaxial layer 420 has the first groove 331 and the second groove 431b.First groove 331 extends along first direction and is arranged in parallel with each other.Second groove 431b be along second direction extend and parallel to each other.According to embodiments of the invention, the first direction of above-mentioned each first groove 331 and the second direction of the second groove 431b orthogonal thereto, and the visual required situation of the second groove 431b is orthogonal thereto at the first groove 331 that part is parallel, does not need as Fig. 4 B only has a second groove 431a to run through all first grooves 331.
Fig. 4 D be according to embodiments of the invention illustrate the section top view of the 400b of semiconductor element.For the framework above first groove 331 of Fig. 4 C and the second groove 431a, in fig. 4d, dielectric layer 332 and conductive material layer 333 are arranged in the first groove 331, and have groove interval 350 between every two adjacent the first grooves 331.Dielectric layer 432 and conductive material layer 433 are arranged in the second groove 431b.According to embodiments of the invention, the material of dielectric layer 332 and dielectric layer 432 is identical, and the material of conductive material layer 333 and conductive material layer 433 is identical.Be connected owing in this embodiment conductive material layer 333 being done partial orthogonality with conductive material layer 433, demand that therefore can be withstand voltage according to difference, design various different withstand voltage framework.
Fig. 5 A ~ Fig. 5 J is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention.In fig. 5, substrate 510 is provided.According to embodiments of the invention, substrate 510 is silicon substrate.In figure 5b, form epitaxial layer 520 on substrate 510, wherein epitaxial layer 520 can be divided into active region 501 and termination environment 502, and formation epitaxial layer 520 forms N-type epitaxial layer.
In figure 5 c, to have withstand voltage zone 530 adjacent with active region 501 for epitaxial layer 520.Form multiple groove 531 in withstand voltage zone 530, and each groove 531 extends along first direction.Between every two adjacent grooves 531, there is groove interval, and the width at groove interval is d1.According to embodiments of the invention, the step forming each groove 531 comprises etching epitaxial layer 520 to form each groove 531, and removes an oxide layer on each groove 531 surface, as shown in 5D figure.After one oxide layer on each groove 531 surface is removed, the groove interval width between every two adjacent grooves 531 is d2, and wherein d2 is less than d1.
In Fig. 5 E, form dielectric layer 532 in each groove 531.According to embodiments of the invention, the dielectric layer 532 in every two adjacent grooves 531 contacts with each other.
In Fig. 5 F, formed on the dielectric layer 532 of conductive material layer 533 in each groove 531.As depicted in fig. 5g, form the step of conductive material layer 533 to comprise and electric conducting material inserted and covers each groove 531; And remove partially conductive material, to form conductive material layer 533 in each groove 531.According to embodiments of the invention, above-mentioned manufacture method also comprises and forms the second dielectric layer 534 as illustrated in fig. 5h on epitaxial layer 520, dielectric layer 532 and conductive material layer 533; And remove part second dielectric layer 534 as shown in fig. 5i, to expose conductive material layer 533 and part epitaxial layer 520.According to embodiments of the invention, remove part second dielectric layer 534, to be formed on dielectric layer 532 that the first dielectric layer 535 contacts with each other between every two adjacent grooves 531.
In fig. 5j, form conductive layer 540 on each groove 531, conductive layer 540 contacts conductive material layer 533 and part epitaxial layer 520.According to embodiments of the invention, forming conductive layer 540 is form Schottky energy barrier metal level.
Fig. 6 A ~ Fig. 6 F is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention.Fig. 6 A is another embodiment of hookup 5D.In fig. 6, dielectric layer 632 is formed in each groove 631.According to embodiments of the invention, the dielectric layer 632 in every two adjacent grooves 631 separated by a groove interval 650.
In fig. 6b, formed on the dielectric layer 632 of conductive material layer 633 in each groove 631.According to embodiments of the invention, form the step of conductive material layer 633 and comprise and electric conducting material inserted and covers each groove 631; And remove partially conductive material, to form conductive material layer 633 in each groove 631, as shown in Figure 6 C.According to embodiments of the invention, above-mentioned manufacture method also comprises formation second dielectric layer 634 on epitaxial layer 620, dielectric layer 632 and conductive material layer 633; And remove part second dielectric layer 634, to expose conductive material layer 633 and part epitaxial layer 620, as shown in 6D ~ 6E figure.According to embodiments of the invention, remove part second dielectric layer 634, to be formed on the groove interval 650 of the first dielectric layer 635 between every two adjacent grooves 631.According to embodiments of the invention, above-mentioned manufacture method also comprises makes epitaxial layer, dielectric layer and conductive material layer form planarized surface.
In Fig. 6 F, form conductive layer 640 on each groove 631, conductive layer 640 contacts conductive material layer 633 and part epitaxial layer 620.According to embodiments of the invention, forming conductive layer 640 is form Schottky energy barrier metal level.
Fig. 7 is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention.In the figure 7, the epitaxial layer 720 be positioned on substrate 710 has withstand voltage zone 730.Region overlay dielectric layer 732 first beyond withstand voltage zone 730 and photoresist layer 740, then carry out dopping process 741.Through dopping process 741, in the formation doped region, surface 751 of epitaxial layer 720.According to embodiments of the invention, doped region 751 is P type doped region.According to embodiments of the invention, this doping step can design before epitaxial layer not yet forms groove.
Fig. 8 is the stage schematic diagram of the manufacture semiconductor element illustrated according to embodiments of the invention.In fig. 8, the epitaxial layer 820 be positioned on substrate 810 has withstand voltage zone 830.Withstand voltage zone 830 has formed multiple groove 831, dielectric layer 832 and conductive material layer 833, wherein has groove interval 850 between every two adjacent grooves 831.Region overlay photoresist layer 840 first beyond withstand voltage zone 830, then carry out dopping process 841.Through dopping process 841, between every two adjacent grooves 831, there is groove interval 850 and form doped region 851.According to embodiments of the invention, doped region 851 is P type doped region.According to embodiments of the invention, this doping step is before formation conductive layer.
In an embodiment of the present invention, the terminal structure of semiconductor element comprises multiple groove and is positioned at withstand voltage zone, and all has dielectric layer and conductive material layer in each groove.The terminal structure that embodiments of the invention provide effectively can reduce the occupied area of termination environment in power semiconductor, to reach the object of volume microminiaturization.On the other hand, dielectric layer due to each groove is interconnected, through the relief fabric of groove to increase the surface area of dielectric layer, can bear higher breakdown voltage in less area, therefore the terminal structure of semiconductor element provided by the present invention can dramatically the breakdown voltage promoting integral member.In one embodiment of this invention, the breakdown voltage of terminal structure can promote more than 10 ~ 20%, and its area reduces more than 50%.In the manufacture method of the terminal structure provided at embodiments of the invention, only need three to four road optical cover process can complete optical cover process loaded down with trivial details needed for prior art, so just effectively can simplify processing time and improve prouctiveness.
Although embodiments of the invention have disclosed as above; so itself and be not used to limit the present invention, be anyly familiar with this those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, the scope that therefore protection scope of the present invention ought define with appending claims is as the criterion.
Claims (15)
1. a terminal structure for semiconductor element, is characterized in that, this semiconductor element comprise an active region and a termination environment adjacent with this active region, this termination environment has this terminal structure, and this terminal structure comprises:
One substrate;
One epitaxial layer, be arranged on this substrate, this epitaxial layer has a withstand voltage zone, and this withstand voltage zone has multiple first groove, and wherein said first groove extends along a first direction and is arranged in parallel with each other;
One dielectric layer, is arranged in each first groove and on this epitaxial layer of part;
One conductive material layer, is arranged on this dielectric layer in each first groove; And
One conductive layer, covers described first groove, contacts this conductive material layer and this epitaxial layer of part, and is electrically connected this active region.
2. the terminal structure of semiconductor element according to claim 1, is characterized in that, this dielectric layer in every two adjacent the first grooves contacts with each other.
3. the terminal structure of semiconductor element according to claim 1, is characterized in that, this dielectric layer in every two adjacent the first grooves separated by a groove interval.
4. the terminal structure of semiconductor element according to claim 3, is characterized in that, the width at the described groove interval between described first groove is different.
5. the terminal structure of semiconductor element according to claim 3, is characterized in that, the described groove interval between described first groove also comprises a doped region.
6. the terminal structure of semiconductor element according to claim 1, is characterized in that, this dielectric layer, this conductive material layer of described first groove have a planarized surface.
7. the terminal structure of semiconductor element according to claim 1, it is characterized in that, also comprise one first dielectric layer, wherein this first dielectric layer is positioned at this dielectric layer that every two adjacent the first grooves contact with each other, or separated by a groove interval between every two adjacent the first grooves, this first dielectric layer is positioned at top between this groove.
8. the terminal structure of semiconductor element according to claim 1, is characterized in that, also comprises more than one second groove and extends along second direction, have this dielectric layer identical with described first groove and this conductive material layer in this second groove.
9. the terminal structure of semiconductor element according to claim 8, is characterized in that, the first direction of described first groove and the second direction of this second groove are orthogonal thereto.
10. a manufacture method for the terminal structure of semiconductor element, is characterized in that, this semiconductor element comprise an active region and a termination environment adjacent with this active region, this termination environment has a terminal structure, and the manufacture method of this terminal structure comprises:
Form an epitaxial layer on a base material, this epitaxial layer has a withstand voltage zone;
Form multiple groove in this withstand voltage zone of this epitaxial layer, wherein said groove extends along a first direction and is arranged in parallel with each other;
Form a dielectric layer in each groove;
Formed on a conductive material layer this dielectric layer in each groove; And
Form a conductive layer on described groove, this conductive material layer of this conductive layers make contact and this epitaxial layer of part.
The manufacture method of the terminal structure of 11. semiconductor elements according to claim 10, is characterized in that, the step forming described groove comprises:
Etch this epitaxial layer to form described groove; And
Remove an oxide layer of described flute surfaces.
The manufacture method of the terminal structure of 12. semiconductor elements according to claim 10, is characterized in that, this dielectric layer in every two adjacent grooves contacts with each other.
The manufacture method of the terminal structure of 13. semiconductor elements according to claim 10, is characterized in that, this dielectric layer in every two adjacent grooves separated by a groove interval.
The manufacture method of the terminal structure of 14. semiconductor elements according to claim 13, is characterized in that, also comprises in this groove interval between described groove, formation one doped region.
The manufacture method of the terminal structure of 15. semiconductor elements according to claim 10, is characterized in that, also comprises and makes this epitaxial layer, this dielectric layer and this conductive material layer form a planarized surface.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109390232A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | Trench schottky termination environment groove etching method and trench schottky preparation method |
| CN113809144A (en) * | 2020-06-16 | 2021-12-17 | 台湾半导体股份有限公司 | Multi-trench schottky diode |
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| US20100140689A1 (en) * | 2008-12-08 | 2010-06-10 | Yedinak Joseph A | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics |
| CN102856352A (en) * | 2011-06-27 | 2013-01-02 | 中国科学院微电子研究所 | Insulated gate bipolar transistor terminal and manufacturing method thereof |
| CN103219395A (en) * | 2012-01-20 | 2013-07-24 | 英属维京群岛商节能元件股份有限公司 | Multi-channel terminal structure used for semiconductor element and manufacturing method of multi-channel terminal structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100140689A1 (en) * | 2008-12-08 | 2010-06-10 | Yedinak Joseph A | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics |
| CN102856352A (en) * | 2011-06-27 | 2013-01-02 | 中国科学院微电子研究所 | Insulated gate bipolar transistor terminal and manufacturing method thereof |
| CN103219395A (en) * | 2012-01-20 | 2013-07-24 | 英属维京群岛商节能元件股份有限公司 | Multi-channel terminal structure used for semiconductor element and manufacturing method of multi-channel terminal structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109390232A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | Trench schottky termination environment groove etching method and trench schottky preparation method |
| CN113809144A (en) * | 2020-06-16 | 2021-12-17 | 台湾半导体股份有限公司 | Multi-trench schottky diode |
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