CN102346236A - Time parameter measurement system - Google Patents

Abstract

The invention discloses a time parameter measurement system for digital integrated circuits. The system is implemented by converting a to-be-measured signal IN into a time interval start signal Start and a stop signal Stop as well as pulse signals RStart and RStop by a channel circuit unit; then, the four signals are respectively provided for an accurate time measurement unit and a coarse time measurement unit to carry out measurement, wherein the accurate time measurement unit is composed of a multi-stage delay line and a calibration unit, and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is steep; and the coarse time measurement unit is composed of a jittering shielding circuit, a counter 1 and a counter 2 (the operating frequencies of the counter 1 and the counter 2 are complementary), and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is slow. By using the system disclosed by the invention, the difficulty of improving the resolution ratio of a time parameter measurement system for high-precision digital integrated circuits in the prior art is overcome, and the technical difficulty that the measurement bandwidth of a time parameter measurement system is limited caused by the jitter of output signals of a comparator for channel circuits.

Description

A kind of time parameter measuring system

Technical field

The invention belongs to electronic measuring technology field, more specifically, relate to a kind of digital integrated circuit time parameter measuring system.

Background technology

Integrated circuit is as the basis and the core of information industry; It is the strategic industry of national economy and social development; Important effect is being brought into play in the aspect promoting economic development, social progress, uplift the people's living standard and safeguard national security etc., has become the focus and the important symbol of weighing a country up-to-dateness and overall national strength of current international competition.

The high precision time parameter measurement system has been brought into play very important effect in design, checking and the encapsulation process of integrated circuit.Whether qualified it be test and validation integrated circuit and time dependent parameter powerful measure.

Fig. 1 is existing a kind of time parameter measuring principle of measurement system figure.

As shown in Figure 1, the time parameter measuring system comprises main control unit, channel circuit unit and measuring unit three parts.Wherein, main control unit is responsible for the sending of various control signals and reading back of measurement result of channel circuit unit and measuring unit.Measured signal IN is connected to comparer A1 and the anode of A2 in the channel circuit unit, and the negative terminal of comparer A1 and A2 meets level comparison signal VrefA and VrefB.The level of measured signal IN compares in comparer A1 and A2 with comparative level VrefA and VrefB respectively; Output signal RStart and RStop; Signal RStart and the RStop time interval signal in the channel circuit unit produces in the circuit and converts time interval commencing signal Start and the stop signal Stop that measuring unit can be discerned into; Send into then carry out XOR in the measuring unit after; Meet the Enable Pin EN of counter as the enable signal of counter, counter is counted, and the output CNT [31:0] in the time interval is represented in output.Wherein CLK is the counting pulse signal of counter, connects the CP end of counter, and counter output CNT [31:0] is 32 bit binary data.

Fig. 2 is the measurement timing waveform of Fig. 1 time parameter measuring system.

The channel circuit unit at first converts measured signal IN into signal RStart and RStop, and time interval signal produces circuit and converts signal RStart and RStop into time interval commencing signal Start and stop signal Stop.The value of supposing counter output CNT [31:0] is N, the count pulse of counter, and promptly the cycle of CLK is T, then time interval T _x, promptly measured signal IN time between VrefA and VrefB is:

T _x＝NT (1)

Time interval measurement this moment resolution is the count pulse cycle T of counter.

If requiring measuring resolution is 1ns, the frequency that then requires clock CLK is 1GHz.Resolution requirement is high more, then requires the rolling counters forward pulsed frequency high more, if resolution is brought up to 125ps, the frequency that then requires CLK is 8GHz, and existing techniques in realizing is got up very difficult.Obviously it is difficult only depending on the way that improves the counter pulse frequency to improve resolving power.

Simultaneously; When measured signal IN rising edge was slow, can there be shake in comparer A1 in the channel circuit unit and A2 output, cause its output pulse signal RStart and RStop jitter phenomenon to occur; Finally cause measuring unit to measure difficulty, the time parameter measuring system is measured limited bandwidth.

Summary of the invention

The objective of the invention is to overcome the deficiency of prior art, the time parameter measuring system of a kind of high resolving power and high measurement bandwidth is provided.

For realizing above-mentioned purpose, time parameter measuring system of the present invention comprises:

One main control unit;

One channel circuit unit; Be used for measured signal is compared in the comparer of channel circuit unit; Output two pulse signals RStart and RStop; Simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in the circuit and converts time interval commencing signal Start and stop signal Stop into;

It is characterized in that also comprising:

One time accurate measurement unit, it is more precipitous to be used for the measured signal rising edge, and comparer is exported the measurement under the situation that does not have shake, is made up of multilevel delay line and scrambler;

Successively with many lag line formation multilevel delay connected in series lines, lag line comprises a plurality of delay cells and a plurality of d type flip flop through interconnection line; Time interval commencing signal Start from upper level connects first delay cell; If lag line is the first order; Then connect the time interval commencing signal Start of circuit unit output; After each delay cell postpones time interval commencing signal Start successively then, all be connected to a d type flip flop, the D end of each d type flip flop meets the time interval commencing signal Start after the delay units delay successively; The time clock CP end of each d type flip flop all meets time interval stop signal Stop, and its reset terminal R meets the reset signal RESET that main control unit sends;

The Q end output of the d type flip flop on each lag line is sent in the scrambler, and when time interval stop signal Stop arrived, the Q of each d type flip flop end output locking obtained representing time interval T _xScrambler output N, the then time interval T of the delay cell number of interior time interval commencing signal Start process _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\ΔL}},$

Wherein, ROUND representes rounding operation, N ₂The delay cell number of expression single-stage passive delay, t _{Δ L}Be the time delay of interconnection line;

One time bigness scale unit; It is slower to be used for the measured signal rising edge; There are the measurement under the situation of shaking in comparer output pulse signal RStart and RStop; Be made up of dither mask circuit and time interval measurement unit, the dither mask circuit comprises that debouncing circuit, waveform restoring circuit and time interval signal produce circuit;

Debouncing circuit comprises that two are removed to shake d type flip flop, two not gates, two programmable delay modules, a synchronous d type flip flop and a NAND gate;

Pulse signal RStart that comparer is exported in the channel circuit unit and RStop import the time clock CP end that removes to shake d type flip flop separately, and programmable delay module delay Δ t is separately passed through in two outputs of going to shake d type flip flop output Q end _L1, Δ t _L2After, behind the door non-through one respectively, be input to the R end that resets separately, two are gone the data D that shakes d type flip flop to hold the Q end output that all connects synchronous d type flip flop, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge shake time Δ t of pulse signal RStart and RStop separately _Start, Δ t _StopPulse signal RStart and RStop are through receiving synchronous d type flip flop time clock CP end, the R termination synchronous reset signal TRI that resets of synchronous d type flip flop, data D termination high level behind the NAND gate; Pulse signal RStart and RStop going separately shaken the signal Q after d type flip flop output goes to shake _StartWith signal Q _Stop

The waveform restoring circuit comprises two JK flip-flops; The J of two JK flip-flops, K end all connect high level; The R termination that resets is from the synchronous reset signal TRI of main control unit, and the time clock CP of two JK flip-flops end removes to shake d type flip flop output Q end and is connected with two respectively, exports the signal Q after going to shake _StartWith signal Q _StopRestoring signal JStart and signal JStop;

Time interval signal produces circuit and comprises two d type flip flops, the D termination high level Vcc of a d type flip flop, and time clock CP termination signal JStart, Q end output time is commencing signal JJStart at interval; The D termination signal JStart of another d type flip flop, clock pulse terminal CP meets signal JStop, and Q end output time is stop signal JJStop at interval; The equal welding system reset signal of the reset terminal R RESET of two d type flip flops;

The time interval measurement unit is used to measure the time interval T that rising edge is tandem time interval commencing signal JJStart, stop signal JJStop _x

Goal of the invention of the present invention is achieved in that

Compare in the comparer of measured signal in the channel circuit unit; Output two pulse signals RStart and RStop; Simultaneously; Under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in the circuit and converts time interval commencing signal Start and stop signal Stop into, owing to adopt the time accurate measurement unit of multilevel delay line structure to have very high Measurement Resolution; The generation that has overcome the high-frequency counting pulse signal of prior art is very difficult, and high resolving power time parameter measuring system is difficult for the defective of realization.Simultaneously, adopted have the dither mask circuit time bigness scale unit, overcome the comparer output that prior art measured signal rising edge slowly causes and had shake, the time parameter measuring system is measured the defective of limited bandwidth.

Description of drawings

Fig. 1 is prior art time parameter measuring principle of measurement system figure.

Fig. 2 is the working timing figure of Fig. 1 time parameter measuring system.

Fig. 3 is a kind of embodiment schematic diagram in channel circuit unit among the present invention;

Fig. 4 is a kind of embodiment structural drawing of time accurate measurement unit among the present invention;

Fig. 5 is the working timing figure of time accurate measurement unit;

Fig. 6 is a kind of embodiment schematic diagram in time bigness scale unit among the present invention;

Fig. 7 is the circuit of dither mask shown in a Fig. 6 embodiment schematic diagram;

Fig. 8 is the working timing figure of dither mask circuit shown in Figure 7;

Fig. 9 is the theory diagram of time parameter measuring system embodiment of the present invention.

Embodiment

Describe below in conjunction with the accompanying drawing specific embodiments of the invention, so that those skilled in the art understands the present invention better.What need point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.

Embodiment

One, channel circuit unit

Fig. 3 is a kind of embodiment schematic diagram in channel circuit unit among the present invention.

The channel circuit unit is the front end of time parameter measuring system, and in the present embodiment, the channel circuit unit comprises: input interface circuit, high-speed comparator, data selector and the time interval produce circuit.Its function is that correct and effective ground is incorporated into the time parameter measuring system with measured signal, and converts measured signal into pulse signal RStart, RStop and time interval commencing signal Start and stop signal Stop that time bigness scale unit, time accurate measurement unit can be discerned.

As shown in Figure 3; In this enforcement, measured signal IN is connected to input interface circuit, in input interface circuit; The resistance R 1, R2 that is connected in series to ground IN to measured signal carried out dividing potential drop, and relay R ELAY1 selects measured signal IN directly or select voltage division signal to send in the high-speed comparator.Then with this signal be connected to the anode of comparer A1 and A2+, at the negative terminal of comparer A1, A2-connect respectively comparative level VrefA and VrefB.

Data selector selects the forward of comparer A1, A2 to export still reverse output through control signal SelStr and SelStop, and the signal RStart after the selection, RStop send into time interval signal and produce circuit generation time interval commencing signal Start and stop signal Stop.

Time interval signal produces circuit and comprises two d type flip flop D1 and D2, the data D termination high level Vcc of D1, and time clock CP termination pulse signal RStart, Q end output time is commencing signal Start at interval; The Q end of the data D termination D1 of D2, time clock CP termination pulse signal RStop, Q end output time is stop signal Stop at interval.The reset terminal R of D1 and D2 all fetches the reset signal RESET from the master control unit.

The channel circuit unit is work like this:

To measure the measured signal IN rise time is example, and at first relay R ELAY1 selects the voltage measurement scope of measured signal IN.Set comparative level VrefA then and be measured signal IN dividing potential drop amplitude 10%, comparative level VrefB is 90% of measured signal IN amplitude.Simultaneously, main control unit begins control signal SelStr and stop control signal SelStop, makes data selector select the forward output of comparer A1, A2.At last, main control unit sends reset signal RESET.At this moment; At d type flip flop D1 rising edge appears at preceding time interval commencing signal Start; After the time interval, commencing signal Start became high level, d type flip flop D2 occur rising edge after time interval stop signal Stop, and data selector output pulse signal RStart and RStop.When measured signal IN rising edge was slow, can there be shake in comparer A1 in the channel circuit unit and A2 output, cause its output pulse signal RStart and RStop jitter phenomenon to occur.

Two, time accurate measurement unit

Fig. 4 is a kind of embodiment of time accurate measurement unit among the present invention.Fig. 5 is the corresponding work sequential chart.

In the present embodiment, as shown in Figure 4, time accurate measurement unit is made up of multilevel delay line and alignment unit.The multilevel delay line is made up of lag line and 6 interconnection lines of 7 same structures, and lag line is by delay cell L ₁-L ₆₈Form with d type flip flop DFFE1-DFFE68.Alignment unit is made up of lag line and 1 interconnection line of 2 same structures.

In delay-line structure, delay cell L ₁-L ₆₈Connected in series successively, connect first delay cell from the time interval signal Start of upper level, if lag line is the first order, then connect the time interval commencing signal Start of circuit unit output,, on the multilevel delay line, transmit successively then.The data terminal of d type flip flop DFFE1D-FFE68 is received in the output of every grade of lag line successively.Time interval stop signal Stop connects the clock end of all d type flip flops.The reset terminal R of all d type flip flops meets reset signal RESET, so just can be removed to latch the output state of delay unit by d type flip flop, i.e. A_Q1 ... A_Q68, B_Q1 ... B_Q68 ..., G_Q1 ... G_Q68.Then output is sent into and just can be obtained between time interval commencing signal Start and the stop signal Stop delay cell number of transmission altogether in the decimal encoder.Scrambler output result is N, and be t the time delay of single delay cell, promptly obtains time interval T _x:

T _x＝N*t (2)

Along with the birth of scale programmable logic device CPLD and FPGA, the metering circuit of showing for Fig. 4 provides good physical Design platform.In FPGA, make up lag line and need satisfy following two conditions: one, require t time delay of delay cell very little, and highly stable; Two, in FPGA inside a kind of like this special construction must be arranged, be convenient to make up lag line.In the present embodiment, the FPGA of the ACEX1K50 of selected altera corp series is in order to realize multilevel delay line and the alignment unit shown in Fig. 4.

Under the common situation, the length of this FPGA internal latency line is limited, searches the device handbook and learns and be 72 grades to the maximum that t time delay of stage delay unit is about 125ps.Can know that maximum measuring intervals of TIME is 125ps * 72=9ns.In the present invention, utilize interconnection line among the FPGA with a plurality of such wall scroll lag line cascades, just can expansion time range of dynamic measurement at interval.

In the present embodiment, as shown in Figure 4.The output of the wall scroll lag line of upper level is connected to the input of the wall scroll lag line of next stage through interconnection line, cascades up successively, has formed 7 wall scroll lag lines and 6 multilevel delay line structures that interconnection line constitutes altogether.

Fig. 5 is the work schedule of multilevel delay line, D ₁-D ₄₇₆Be the output of each delay cell of lag line, remove to latch the transmission state of delay cell on the lag line, then this transmission state is exported through the decimal encoder coding through time interval stop signal Stop signal.Scrambler output result is N, and be t the time delay of delay cell, and be t the time delay of interconnection line _{Δ L}, time interval T then _xFor:

T _x＝N*t+N ₁*t _ΔL(3)

And N ₁For:

${\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="HDA0000069763570000011.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">N</figure-callout>}}_1=\mathrm{ROUND}\left(\frac{N}{N_2}\right),---\left(4\right)$

Wherein, ROUND representes rounding operation, N ₂The delay cell number of expression wall scroll lag line.Formula (4) is brought in the formula (3), then T _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}}---\left(5\right)$

In the present embodiment, time accurate measurement unit: N ₂=68, N ₁=6, t=125ps, measurement range: 0ns-50ns, Measurement Resolution 125ps.

Simultaneously, because the size of FPGA power consumption, working temperature and use resource is different, the t and t time delay of interconnection line time delay of the delay cell in the multilevel delay line _{Δ L}Different sizes can appear.So, in the present embodiment, for the multilevel delay line provides an alignment unit, in order to real-time measurement t and t _{Δ L}Size, the measurement performance of alignment time accurate measurement unit.

Delay line calibration unit schematic diagram is as shown in Figure 4.

In the present embodiment, alignment unit is made up of 2 lag lines, 1 interconnection line and scrambler 2.

The alignment unit principle of work is: be approximately t the time delay of supposing the wall scroll lag line _LAt first, produce former and later two time interval signals SStart and SStop through a reference instrument, the time interval of establishing this moment is T _X1, and T _X1＜t _LTime interval commencing signal SStart is from lag line 1 input, and time interval stop signal SStop latchs the output state of delay cell in lag line 1 and the lag line 2, obtains exporting N as a result through decimal encoder then _Cal-1In like manner, produce two time interval signal SStart and SStop through reference instrument once more, the time interval of this moment is T _X2, and t _L＜T _X2＜2*t _L, in like manner obtain exporting N as a result _Cal-2

Can know by formula (3):

$\left\{\begin{array}{c}{T}_{x1}=N_{\mathrm{cal}-1}*t\\ T_{x2}=N_{\mathrm{cal}-2}*t+t_{\mathrm{\&Delta;L}}\end{array}\right.---\left(6\right)$

Then t and t _{Δ L}:

$\left\{\begin{array}{c}t=\frac{T_{x1}}{N_{\mathrm{cal}-1}}\\ t_{\mathrm{\&Delta;L}}=T_{x2}-N_{\mathrm{cal}-2}*\frac{T_{x1}}{N_{\mathrm{cal}-1}}\end{array}\right.---\left(7\right)$

Can measure t and t in system works environment through formula (7) this moment _{Δ L}Size, with t and t _{Δ L}In the substitution formula (5), reached the purpose of alignment time accurate measurement unit.

Three, time bigness scale unit

In the present embodiment, as shown in Figure 3, pulse signal RStart and RStop are obtained through data selector by comparer A1, A2 output.When the measured signal rising edge more precipitous; When comparer A1, A2 output pulse signal RStart and RStop do not shake, can directly utilize pulse signal RStart and RStop to remove to trigger d type flip flop D1 and D2 generation time interval commencing signal Start and stop signal Stop.When the measured signal rising edge slower; When there are shake in comparer A1, A2 output pulse signal RStart and RStop; When if reset signal RESET resets to d type flip flop D1 and D2, pulse signal RStart is in during high level or the negative edge shake, and the negative edge shake will make d type flip flop D1 produce the upset from the low level to the high level; Can negative edge be judged as rising edge by error like this, cause time parameter to measure mistake.At this moment just can not directly utilize pulse signal RStart and RStop to remove to trigger d type flip flop generation time commencing signal Start Start and stop signal Stop at interval.

Wherein, time bigness scale unit also is in the FPGA of above-mentioned time accurate measurement unit, to realize.

Fig. 6 is a kind of embodiment schematic diagram in time bigness scale unit.

As shown in Figure 6, time bigness scale unit comprises and contains dither mask circuit and time interval measurement unit, in the present embodiment, is to improve resolution, and the gate time interval measurement unit comprises two counters, i.e. counter 1 and 2 and one XOR gate.Wherein, Counter 1 and 2 clock end CP meet clock signal

and CLK respectively; Enable Pin EN connects XOR gate output; And

and CLK 180 ° of phasic differences mutually; Frequency is 125MHz, and then measurement resolution is 4ns.Under the constant situation of counter clock frequency, resolving power is doubled.

Time bigness scale unit is work like this:

Like Fig. 7 and shown in Figure 8, at first, low level of given synchronous reset signal TRI, synchronous d type flip flop 5 is output as low, at this moment, and two output Qstart and Qstop that remove to shake d type flip flop 3,4, the output JStart of two JK flip-flops 1,2 and JStop are low; When given synchronous reset signal is high level, enable synchronous d type flip flop 5 and two JK flip-flops 1,2.When if the pulse RStart of data selector output and RStop are low level simultaneously in the channel circuit unit, triggering synchronous d type flip flop 5, the output high level enables two and removes to shake d type flip flop 3,4.

Synchronous d type flip flop 5 and synchronous reset signal TRI; Making two, to remove to shake d type flip flop D effective for low level simultaneously at pulse signal RStart and RStop; Start working; The output JStart and the JStop that make two JK flip-flops are consistent its state simultaneously for low, have guaranteed that so whole dither mask circuit sequence is synchronous, consistent.

Pulse signal RStart and RStop are through being reduced into signal JStart and the JStop that does not have shake after the dither mask circuit.Produce in the circuit at time interval signal then, through reset signal RESET, generation time is commencing signal JJStart and stop signal JJStop at interval.Signal JJStart and JJStop export the CNTEN signal behind the XOR in XOR gate, counting in counter 1,2, thus measure time interval T _xThe measurement result of supposing counter 1 sum counter 2 is respectively CNT1 and CNT2, and then time interval Tx is:

$T_x=\frac{\mathrm{<figure-callout\; id="1"\; label="CNT"\; filenames="HDA0000069763570000011.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">CNT</figure-callout>}1+\mathrm{CNT}2}{2}*T---\left(8\right)$

Wherein, T is the count pulse clk cycle of counter.

Fig. 7 is a kind of embodiment schematic diagram of dither mask circuit.

As shown in Figure 7, the dither mask circuit comprises debouncing circuit, waveform restoring circuit and time interval signal and produces circuit.

As shown in Figure 7, debouncing circuit comprises that a synchronous d type flip flop is that to remove to shake d type flip flop be 3,4, two not gates of d type flip flop and two programmable delay modules for d type flip flop 5, two.Pulse signal RStart and RStop are through receiving the CP end of synchronous d type flip flop, the R termination that resets synchronous reset signal TRI, data D termination high level behind the NAND gate; The clock CP end that removes to shake d type flip flop 3,4 separately of pulse signal RStart and RStop input simultaneously, output Q end postpones Δ t through programmable delay module separately _L1, Δ t _L2After time, behind the door non-through one respectively, be input to the R end that resets of shaking d type flip flop 3,4, two are gone the data D that shakes d type flip flop 3,4 to hold the Q end output that all connects synchronous d type flip flop, and Q is used in the output of going to shake d type flip flop 3,4 respectively _Start, Q _StopExpression, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge shake time Δ t of pulse signal RStart and RStop separately _Start, Δ t _Stop

As shown in Figure 7; The waveform restoring circuit comprises two JK flip-flops, and promptly the J of 1,2, two JK flip-flops of JK flip-flop, K end all meet high level Vcc; The R termination that resets synchronous reset signal TRI, the time clock CP of two JK flip-flops end remove to shake d type flip flop 3,4 output Q ends and are connected with two respectively.JStart is used in the output of two JK flip-flops respectively, and JStop representes.

As shown in Figure 7; It is identical with time interval signal generation circuit in Fig. 3 channel circuit unit that time interval signal produces circuit; Comprise two d type flip flops 6,7; The data D termination high level Vcc of d type flip flop 6, time clock CP termination signal JStart, Q end output time is commencing signal JJStart at interval; The Q end of the D termination d type flip flop 6 of d type flip flop 7, clock pulse terminal CP meets signal JStop, and Q end output time is stop signal JJStop at interval.The reset terminal R of d type flip flop 1,2 all meets reset signal RESET.

Fig. 8 is the working timing figure of Fig. 7 institute dither mask circuit.

The dither mask circuit is work like this:

The principle of eliminating pulse signal RStart and RStop shake is similar, is example with pulse signal RStart, and as shown in Figure 8, the shake time of pulse signal RStart is Δ t _Start, when pulse signal RStart arrived, the data D end that removes to shake d type flip flop 3 was for carrying out the high level of synchronous d type flip flop 5 outputs of sequential after synchronously.When the time clock CP termination of removing to shake d type flip flop 3 is received the rising edge of pulse RStart, remove to shake the output terminal Q output signal Q of d type flip flop 3 _StartBe high level, signal Q _StartPostpone a period of time Δ t through programmable Postponement module 1 _L1Back output postpones Δ t _L1Be the size that main control unit is in advance set, and time delay Δ t _L1Edge shake time Δ t greater than pulse RStart _StartPulse Q _StartShake d type flip flop 3 through resetting after the not gate negate, remove to shake d type flip flop 3 output pulse Q this moment _StartEqual low level, when this arrives again, trigger once more and remove to shake d type flip flop 3, remove to shake d type flip flop 3 output pulse Q up to the rising edge of pulse RStart signal _StartBecome high level again, and afterpulse Q _StartPostpone a period of time Δ t through programmable Postponement module 1 again _L1Back output.Shake d type flip flop 3 through resetting after the not gate negate then, remove to shake d type flip flop 3 and export pulse Q once more this moment _StartEqual low level, so just convert pulse RStart into pulse Q _StartAnd pulse Q _StartThe high level width equal Δ t _L1

Because pulse Q _StartReceive the clock end CP of JK flip-flop 1, and the data terminal J of JK flip-flop 1 and K all connect fixedly high level.Principle of work by JK flip-flop can know that when coming a rising edge, the output of JK flip-flop just is turned to state 1 from state 0, or is turned to state 0 from state 1.JK flip-flop is just with signal Q like this _StartConversion is for signal JStart.And can know that the JStart signal removes the signal that reduces after the shake for the RStart signal.

Fig. 9 is the theory diagram of time parameter measuring system embodiment.

As shown in Figure 9, in the present embodiment, time parameter measuring system of the present invention comprises main control unit, channel circuit unit, time accurate measurement unit and time bigness scale unit.

Main control unit sends control command, and the channel circuit unit converts measured signal into time interval commencing signal Start and stop signal Stop, and pulse signal RStart and the RStop of pulse behind data selector of comparer generation.

When measurement range 0ns-50ns, service time, the accurate measurement unit was measured, the time interval between measuring intervals of TIME commencing signal Start and the stop signal Stop.At last measurement result is transferred to main control unit from the SPI interface.

When measurement range 50ns-1ms, service time, the bigness scale unit was measured.Comparer output through pulse RStart behind the data selector and RStop process dither mask circuit, is removed signal jitter, send into counter then and measure.At last measurement result is transferred to main control unit from the SPI interface.

Control signal from main control unit produces various control signals in control logic circuit, comprise control signal of synchronous reset signal TRI, reset signal RESET and channel circuit unit, time accurate measurement unit and time bigness scale unit or the like.

In the present embodiment, digital integrated circuit time parameter measuring system of the present invention provides time accurate measurement unit and time bigness scale unit to be used for measuring respectively.Not only solved the difficulty that the time parameter Measurement Resolution improves, and solved the comparator output signal shake, the time parameter measuring system is measured the defective of limited bandwidth.This system testing resolution of test result proof, repeatability and stability all satisfy each item index request of digital integrated circuit time parameter test macro, and the measurement index of realization is:

1, time accurate measurement unit: range of dynamic measurement 0ns-50ns, resolution is 125ps, measuring accuracy 500ps ± 1%.

2, time bigness scale unit: range of dynamic measurement 50ns-1ms, resolution is 4ns, measuring accuracy 4ns ± 0.1%.

Simultaneously, time parameter measuring system of the present invention also has important use value and development meaning in every field such as theory research, test scientific and engineering, medical skill and science, Communications And Navigation, modulating domain analyzing appearance.

Although above the illustrative embodiment of the present invention is described; So that the technician in present technique field understands the present invention, but should be clear, the invention is not restricted to the scope of embodiment; To those skilled in the art; As long as various variations appended claim limit and the spirit and scope of the present invention confirmed in, these variations are conspicuous, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (3)

1. time parameter measuring system comprises:

One main control unit;

One channel circuit unit; Be used for measured signal is compared in the comparer of channel circuit unit; Output two pulse signals RStart and RStop; Simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in the circuit and converts time interval commencing signal Start and stop signal Stop into;

It is characterized in that also comprising:

One time accurate measurement unit, it is more precipitous to be used for the measured signal rising edge, and comparer is exported the measurement under the situation that does not have shake, is made up of multilevel delay line and scrambler;

Successively with many lag line formation multilevel delay connected in series lines, lag line comprises a plurality of delay cells and a plurality of d type flip flop through interconnection line; Time interval commencing signal Start from upper level connects first delay cell; If lag line is the first order; Then connect the time interval commencing signal Start of circuit unit output; After each delay cell postpones time interval commencing signal Start successively then, all be connected to a d type flip flop, the D end of each d type flip flop meets the time interval commencing signal Start after the delay units delay successively; The time clock CP end of each d type flip flop all meets time interval stop signal Stop, and its reset terminal R meets the reset signal RESET that main control unit sends;

The Q end output of the d type flip flop on each lag line is sent in the scrambler, and when time interval stop signal Stop arrived, the Q of each d type flip flop end output locking obtained representing time interval T _xScrambler output N, the then time interval T of the delay cell number of interior time interval commencing signal Start process _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}},$

Wherein, ROUND representes rounding operation, N ₂The delay cell number of expression single-stage passive delay, t _{Δ L}Be the time delay of interconnection line;

One time bigness scale unit; It is slower to be used for the measured signal rising edge; There are the measurement under the situation of shaking in comparer output pulse signal RStart and RStop; Be made up of dither mask circuit and time interval measurement unit, the dither mask circuit comprises that debouncing circuit, waveform restoring circuit and time interval signal produce circuit;

Debouncing circuit comprises that two are removed to shake d type flip flop, two not gates, two programmable delay modules, a synchronous d type flip flop and a NAND gate;

Pulse signal RStart that comparer is exported in the channel circuit unit and RStop import the time clock CP end that removes to shake d type flip flop separately, and programmable delay module delay Δ t is separately passed through in two outputs of going to shake d type flip flop output Q end _L1Δ t _L2After, behind the door non-through one respectively, be input to the R end that resets separately, two are gone the data D that shakes d type flip flop to hold the Q end output that all connects synchronous d type flip flop, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge shake time Δ t of pulse signal RStart and RStop separately _Start,Δ t _StopPulse signal RStart and RStop be through receiving synchronous d type flip flop time clock CP end behind the NAND gate, the R termination that resets of d type flip flop is from the synchronous reset signal TRI of main control unit, data D termination high level synchronously; Pulse signal RStart and RStop going separately shaken the signal Q after d type flip flop output goes to shake _StartWith signal Q _Stop

The waveform restoring circuit comprises two JK flip-flops; The J of two JK flip-flops, K end all connect high level; The R termination that resets synchronous reset signal TRI, the time clock CP of two JK flip-flops end remove to shake d type flip flop output Q end and are connected with two respectively, export the signal Q after going to shake _StartWith signal Q _StopRestoring signal JStart and signal JStop;

Time interval signal produces circuit and comprises two d type flip flops, the D termination high level Vcc of a d type flip flop, and time clock CP termination signal JStart, Q end output time is commencing signal JJStart at interval; The D termination signal JStart of another d type flip flop, clock pulse terminal CP meets signal JStop, and Q end output time is stop signal JJStop at interval; The equal welding system reset signal of the reset terminal R RESET of two d type flip flops;

The time interval measurement unit is used to measure the time interval T that rising edge is tandem time interval commencing signal JJStart, stop signal JJStop _x

2. time parameter measuring system according to claim 1 is characterized in that also comprising:

One delay line calibration unit, the delay line calibration unit is made up of two lag lines, an interconnection line and a scrambler;

Produce former and later two time interval signals SStart and SStop through a reference instrument, the time interval of this moment is T _X1, and T _X1＜t _L, time interval commencing signal SStart is from lag line 1 input, and time interval stop signal SStop latchs the output state of delay cell in lag line 1 and the lag line 2, obtains exporting N as a result through decimal encoder then _Cal-1In like manner, produce two time interval signal SStart and SStop through reference instrument once more, the time interval of this moment is T _X2, and t _L＜T _X2＜2*t _L, in like manner obtain exporting N as a result _Cal-2, then, the t and t time delay of interconnection line time delay of delay cell _{Δ L}:

$\left\{\begin{array}{c}t=\frac{T_{x1}}{N_{\mathrm{cal}-1}}\\ t_{\mathrm{\&Delta;L}}=T_{x2}-N_{\mathrm{cal}-2}*\frac{T_{x1}}{N_{\mathrm{cal}-1}}\end{array}\right.$

T and t time delay of interconnection line time delay with delay cell _{Δ L}The substitution formula:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}}$

Proofreaied and correct time interval T thereby reach _X:, i.e. the purpose of smart time measuring unit.

3. time parameter measuring system according to claim 1; It is characterized in that; Described time interval measurement unit comprises two counters and an XOR gate; The clock end CP of two countings meets clock signal

and CLK respectively; Enable Pin EN connects XOR gate output, and

and CLK 180 ° of phasic differences mutually;

The output result of two counters is respectively CNT1 and CNT2, and then time interval Tx is:

$T_x=\frac{\mathrm{CNT}1+\mathrm{CNT}2}{2}*T$

Wherein, T is the count pulse clk cycle of counter.

Images