CN113092858B - High-precision frequency scale comparison system and comparison method based on time-frequency information measurement - Google Patents
High-precision frequency scale comparison system and comparison method based on time-frequency information measurement Download PDFInfo
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- CN113092858B CN113092858B CN202110387851.6A CN202110387851A CN113092858B CN 113092858 B CN113092858 B CN 113092858B CN 202110387851 A CN202110387851 A CN 202110387851A CN 113092858 B CN113092858 B CN 113092858B
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- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
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- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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Abstract
The invention provides a high-precision frequency scale comparison system and a comparison method based on time-frequency information measurement, which comprises a frequency standard module, a frequency scale pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module and a display module which are connected in sequence, wherein the signal output end of the frequency scale pulse signal module is also connected with the signal input end of the time interval measurement module; the invention avoids the normalization processing of frequency in the traditional frequency standard comparison method, overcomes the influence of additional noise by using the FPGA technology, and further enhances the robustness of the system; the invention realizes the rapid and direct phase measurement of any frequency relation in the radio frequency range and accelerates the speed of frequency standard comparison.
Description
Technical Field
The invention relates to a frequency scale comparison system and a comparison method, in particular to a high-precision frequency scale comparison system and a high-precision frequency scale comparison method based on time frequency information measurement.
Background
In time frequency information measurement, a traditional frequency standard comparison method is established on the basis of same-frequency phase comparison, aiming at phase comparison among different frequency standard signals, the frequency of the signals needs to be normalized through complex frequency conversion processes such as frequency mixing, frequency doubling, frequency synthesis and the like, the normalization processing of the frequency not only makes the system structure complex and the cost increased, but also is easy to introduce additional noise of a synthesis circuit, so that the precision, namely the accuracy of the frequency standard comparison and the frequency stability of the frequency measurement are difficult to guarantee; the pilot frequency phase comparison method can directly complete the phase measurement between two comparison signals without frequency normalization, overcomes the defects of the traditional frequency standard comparison method in principle, but the pilot frequency phase comparison method obtains the high precision based on the fixed frequency relation between the two comparison signals, and aims at the phase comparison between the two frequency standard signals under the complex frequency relation and the large frequency difference relation, because the phase coincidence point serving as the gate signal is difficult to generate, the accuracy and the stability of the measurement are greatly reduced, and even the system cannot measure.
Disclosure of Invention
The invention aims to provide a high-precision frequency scale comparison system and a comparison method based on time-frequency information measurement, which can change passive generation of a phase coincidence point serving as a gate signal into active detection, realize direct phase measurement of any frequency relation under a complex background, improve response time of frequency scale comparison in time-frequency information measurement, namely second-level frequency stability of speed and frequency measurement, and enhance stability and reliability of the system.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-precision frequency scale comparison system based on time-frequency information measurement comprises a frequency standard module, a measured frequency module, a frequency scale pulse signal module, a measured pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module, a display module and a power supply module; the system comprises a frequency standard module, a frequency standard pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module and a display module which are sequentially connected, wherein the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module;
the frequency standard module is used for generating frequency with accuracy higher than +/-1 multiplied by 10-12A magnitude frequency scale signal;
the tested frequency module is used for generating the frequency with the accuracy lower than +/-1 multiplied by 10-12Comparing the magnitude of the frequency signal to obtain a measured frequency signal;
the frequency scale pulse signal module and the pulse signal to be tested module are respectively used for generating a rectangular frequency scale pulse signal with the duty ratio of 50% and a rectangular pulse signal to be tested with the duty ratio of 50%;
the adjustable time delay module is used for generating a fixed time delay signal and a fine tuning time delay signal of the frequency standard signal;
the phase detection module is used for generating a phase coincidence point pulse signal;
the gate generation module is used for generating a reference gate time interval and an actual gate switching signal;
the time interval measuring module is used for generating a frequency scale signal and a counting value of a measured frequency signal;
the data processing module is used for processing the counting values of the frequency standard signal and the measured frequency signal and generating the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system;
and the display module is used for receiving and displaying the processing result of the data processing module.
The frequency standard module adopts a 10MHz 5071A high-performance cesium atomic frequency standard, and the frequency accuracy is +/-5 multiplied by 10-13。
The measured frequency module adopts a crystal oscillator or a KDS rubidium atomic clock, and the frequency accuracy is lower than +/-1 multiplied by 10-12Magnitude.
The frequency scale pulse signal module and the pulse signal module to be tested both adopt Schmidt contactor 74LS14N chips.
The adjustable time delay module consists of a first-stage time delay circuit, a second-stage time delay circuit and a third-stage time delay circuit;
the first-stage delay circuit consists of a first edge type D trigger 74LS175 chip and a first D trigger 74LS375 chip, signal input ends of the first edge type D trigger 74LS175 chip and the first D trigger 74LS375 chip, namely signal input ends of the first-stage delay circuit are connected with a signal output end of a frequency scale pulse signal module, a signal output end of the first D trigger 74LS375 chip is connected with a signal input end of a second-stage delay circuit, and a signal output end of the first edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module;
the second-stage time delay circuit consists of a second edge type D trigger 74LS175 chip and a second D trigger 74LS375 chip, signal input ends of the second edge type D trigger 74LS175 chip and the second D trigger 74LS375 chip, namely signal input ends of the second-stage time delay circuit are connected with a signal output end of the first D trigger 74LS375 chip in the first-stage time delay circuit, a signal output end of the second D trigger 74LS375 chip is connected with a signal input end of the third-stage time delay circuit, and a signal output end of the second edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module;
the third-stage time delay circuit is composed of a third edge type D trigger 74LS175 chip, a third D trigger 74LS375 chip and a fourth edge type D trigger 74LS175 chip, signal input ends of the third edge type D trigger 74LS175 chip and the third D trigger 74LS375 chip, namely signal input ends of the third-stage time delay circuit are connected with a signal output end of the second D trigger 74LS375 chip in the second-stage time delay circuit, a signal output end of the third D trigger 74LS375 chip is connected with a signal input end of the fourth edge type D trigger 74LS175 chip, a signal output end of the third edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module, and a signal output end of the fourth edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module.
The phase detection module consists of a first pulse conversion circuit, a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit, a fifth pulse conversion circuit, a first phase coincidence detection circuit, a second phase coincidence detection circuit, a third phase coincidence detection circuit and a fourth phase coincidence detection circuit;
the first pulse conversion circuit, the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit all adopt pulse conversion circuits, the pulse conversion circuit consists of a pulse conversion D flip-flop 74LS375 chip, a pulse conversion logic AND gate circuit 74LS08D chip and a pulse conversion logic NOT gate circuit 74LS04N chip, wherein the D signal input end of the pulse conversion D flip-flop 74LS375 chip is connected with the A signal input end of the pulse conversion logic AND gate circuit 74LS08D chip, the Q signal output end of the pulse conversion D flip-flop 74LS375 chip is connected with the signal input end of the pulse conversion logic NOT gate circuit 74LS04N chip, the signal output end of the pulse conversion logic NOT gate circuit 74LS04N chip is connected with the B signal input end of the pulse conversion logic AND gate circuit 74LS08D chip, and the signal output end Y of the pulse conversion logic AND gate circuit 74LS08D chip is used as the signal output end of the pulse conversion circuit;
the first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip, the A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip, the A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip, the A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the fourth phase coincidence detection circuit is composed of a fourth logic AND circuit 74LS08D chip, the A4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the fifth pulse conversion circuit; and the signal output end of the fourth phase coincidence detection circuit is connected with the signal input end of the gate generation module.
The gate generation module is composed of a programmable frequency divider, a three-input three-NOR gate 74LS27N chip and a logic NOT gate 74LS04N chip, the signal output end of the programmable frequency divider is connected with the signal input end of the time interval measurement module, the signal input end of the three-input three-NOR gate 74LS27N chip is respectively connected with the signal output ends of the first phase coincidence detection circuit, the second phase coincidence detection circuit, the third phase coincidence detection circuit and the fourth phase coincidence detection circuit, the signal output end of the input three-NOR gate 74LS27N chip is connected with the signal input end of the logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip is connected with the signal input end of the time interval measurement module.
The time interval measuring module adopts a programmable counter and is realized by FPGA hardware description language programming; the FPGA adopts a Cyclone IV chip EP4CE 75.
The data processing module adopts an embedded singlechip STM32F103RBT6 chip, and the display module can adopt an LCD.
A high-precision frequency scale comparison method based on time-frequency information measurement comprises the following steps:
step A, respectively carrying out digital processing on a frequency standard signal and a measured frequency signal generated by a frequency standard module and a measured frequency module by using a frequency standard pulse signal module and a measured pulse signal module, namely respectively converting the frequency standard signal generated by a 10MHz 5071A high-performance cesium atomic frequency standard and the measured frequency signal generated by a crystal oscillator or a KDS rubidium atomic clock into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with the duty ratio of 50% through a Schmidt trigger 74LS 14N;
b, sending the rectangular frequency scale pulse signal with the duty ratio of 50% to an adjustable time delay module for time delay to generate a time delay signal;
specifically, a rectangular frequency standard pulse signal with a duty ratio of 50% is sent to a first-stage delay circuit, a first fixed delay signal is generated through a first D flip-flop 74LS375 chip, the delay amount of the first fixed delay signal is the clock cycle of the first D flip-flop 74LS375 chip, a first fine-tuning delay signal is generated through a first edge type D flip-flop 74LS175 chip, the delay amount of the first fine-tuning delay signal is the clock cycle of the first edge type D flip-flop 74LS175 chip, and the delay amount of the first fixed delay signal is larger than the delay amount of the first fine-tuning delay signal;
sending the first fixed time delay signal into a second-stage time delay circuit, generating a second fixed time delay signal through a second D trigger 74LS375 chip, wherein the time delay of the second fixed time delay signal is the clock period of the second D trigger 74LS375 chip, generating a second fine tuning time delay signal through a second edge type D trigger 74LS175 chip, the time delay of the second fine tuning time delay signal is the clock period of the second edge type D trigger 74LS175 chip, and the time delay of the second fixed time delay signal is greater than the time delay of the second fine tuning time delay signal;
sending the second fixed time delay signal to a third-stage time delay circuit, generating a third fixed time delay signal through a third D trigger 74LS375 chip, wherein the time delay of the third fixed time delay signal is the clock period of the third D trigger 74LS375, generating a third fine-tuning time delay signal through a third edge type D trigger 74LS175 chip, the time delay of the third fine-tuning time delay signal is the clock period of the third edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is greater than the time delay of the third fine-tuning time delay signal;
sending the third fixed time delay signal into a fourth edge type D trigger 74LS175 chip to generate a fourth fine tuning time delay signal, wherein the time delay of the fourth fine tuning time delay signal is the clock period of the fourth edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is larger than that of the fourth fine tuning time delay signal;
step C, sending a rectangular pulse signal to be tested with a duty ratio of 50% generated by a pulse signal module to be tested into a first pulse conversion circuit, generating a rectangular pulse signal to be tested with a duty ratio lower than 10%, respectively sending a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal into a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit and a fifth pulse conversion circuit, and respectively generating a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal after pulse conversion;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a first fine-tuning time delay signal after pulse conversion into a first phase coincidence detection circuit to generate a first phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a second fine-tuning time delay signal after pulse conversion into a second phase coincidence detection circuit to generate a second phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a third fine-tuning time delay signal after pulse conversion into a third phase coincidence detection circuit to generate a third phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a fourth fine-tuning time delay signal after pulse conversion into a fourth phase coincidence detection circuit to generate a fourth phase coincidence point pulse;
calculating the least common multiple of the frequency standard signal and the measured frequency signal according to the frequency relation between the frequency standard signal and the measured frequency signal, and generating a reference gate signal by a programmable frequency divider in a gate generation module by taking the period of the least common multiple as a time interval;
the first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to a three-input three-NOR gate 74LS27N chip in a gate generation module, the signal output end of the three-input three-NOR gate 74LS27N chip is connected with the signal input end of a logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip generates an actual gate signal of a time interval measurement module under the control of a reference gate signal;
e, simultaneously sending the rectangular frequency scale pulse signal with the duty ratio of 50% and the rectangular pulse signal to be measured into a time interval measuring module, wherein the time interval measuring module consists of a programmable counter, and carrying out gapless counting under the control of an actual gate signal to obtain the count values of the rectangular frequency scale pulse signal and the rectangular pulse signal to be measured;
and F, sending the count value of the programmable counter into a data processing module, namely a singlechip STM32F103RBT6 chip for processing, and obtaining the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system.
Compared with the prior art, the invention has the beneficial effects that:
the invention avoids the normalization processing of frequency in the traditional frequency standard comparison method, simplifies the system structure by utilizing the FPGA technology, reduces the cost, overcomes the influence of additional noise and further strengthens the robustness of the system; because the adjustable time delay chain technology different from the traditional frequency standard comparison method is adopted, the influence of the complex frequency relation on the phase measurement precision is effectively eliminated, the system response time and the frequency accuracy are greatly improved, the system response time at any moment is better than 1ms, and the frequency accuracy is better than +/-6 multiplied by 10-13The method and the device realize rapid direct phase measurement of any frequency relation in a radio frequency range and accelerate the speed of frequency standard comparison.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1: the invention relates to a high-precision frequency scale comparison system based on time-frequency information measurement, which comprises a frequency standard module, a measured frequency module, a frequency scale pulse signal module, a measured pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module, a display module and a power supply module, wherein the frequency standard module is used for measuring the time frequency of a measured pulse signal; the system comprises a frequency standard module, a frequency standard pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module and a display module which are sequentially connected, wherein the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module;
the frequency standard module is used for generating frequency with accuracy higher than +/-1 multiplied by 10-12A magnitude frequency scale signal; preferably, the frequency standard module adopts a 10MHz 5071A high-performance cesium atomic frequency standard, the frequency accuracy of the 10MHz 5071A high-performance cesium atomic frequency standard is +/-5E-13, and the frequency standard module is used for generating the frequency accuracy which is preferably higher than +/-1 multiplied by 10-12A magnitude frequency scale signal;
the tested frequency module is used for generating the frequency with the accuracy lower than +/-1 multiplied by 10-12Comparing the magnitude of the frequency signal to obtain a measured frequency signal; preferably, the frequency module to be measured can adopt a crystal oscillator or a secondary frequency standard such as a KDS rubidium atomic clock and the like for useProducing frequency accuracy less than + -1 × 10-12Magnitude comparison frequency signals, namely measured frequency signals;
the frequency scale pulse signal module and the pulse signal to be tested module are respectively used for generating a rectangular frequency scale pulse signal with the duty ratio of 50% and a rectangular pulse signal to be tested with the duty ratio of 50%; preferably, the frequency scale pulse signal module and the pulse signal to be detected module adopt schmitt trigger 74LS14N chips; the frequency standard pulse signal module and the tested pulse signal module are respectively used for carrying out digital processing on the frequency standard signal and the tested frequency signal generated by the frequency standard module and the tested frequency module;
the adjustable time delay module is used for generating a fixed time delay signal and a fine tuning time delay signal of the frequency standard signal; preferably, the adjustable delay module is composed of a first-stage delay circuit, a second-stage delay circuit and a third-stage delay circuit;
the first-stage delay circuit is composed of a first edge type D trigger 74LS175 chip and a first D trigger 74LS375 chip, signal input ends of the first edge type D trigger 74LS175 chip and the first D trigger 74LS375 chip, namely signal input ends of the first-stage delay circuit are connected with signal output ends of a frequency scale pulse signal module, a signal output end of the first D trigger 74LS375 chip is connected with a signal input end of a second-stage delay circuit, a signal output end of the first edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module, and particularly, a signal output end of the first edge type D trigger 74LS175 chip is connected with a signal input end of a first phase coincidence detection circuit in the phase detection module; sending a rectangular frequency standard pulse signal with a duty ratio of 50% into a first-stage delay circuit, generating a first fixed delay signal through a first D trigger 74LS375 chip, wherein the delay amount of the first fixed delay signal is the clock period of the first D trigger 74LS375, generating a first fine-tuning delay signal through a first edge type D trigger 74LS175 chip, the delay amount of the first fine-tuning delay signal is the clock period of the first edge type D trigger 74LS175 chip, and the delay amount of the first fixed delay signal is far greater than the delay amount of the first fine-tuning delay signal;
the second-stage time delay circuit consists of a second edge type D trigger 74LS175 chip and a second D trigger 74LS375 chip, signal input ends of the second edge type D trigger 74LS175 chip and the second D trigger 74LS375 chip, namely signal input ends of the second-stage time delay circuit are connected with a signal output end of the first D trigger 74LS375 chip in the first-stage time delay circuit, a signal output end of the second D trigger 74LS375 chip is connected with a signal input end of the third-stage time delay circuit, and a signal output end of the second edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module; specifically, the signal output end of the second edge type D flip-flop 74LS175 chip is connected to the signal input end of the second phase coincidence detection circuit in the phase detection module; sending the first fixed time delay signal into a second-stage time delay circuit, generating a second fixed time delay signal through a second D trigger 74LS375 chip, wherein the time delay of the second fixed time delay signal is the clock period of the second D trigger 74LS375, generating a second fine-tuning time delay signal through a second edge type D trigger 74LS175 chip, the time delay of the second fine-tuning time delay signal is the clock period of the second edge type D trigger 74LS175 chip, and the time delay of the second fixed time delay signal is far greater than the time delay of the second fine-tuning time delay signal;
the third-stage time delay circuit is composed of a third edge type D flip-flop 74LS175 chip, a third D flip-flop 74LS375 chip and a fourth edge type D flip-flop 74LS175 chip, signal input ends of the third edge type D flip-flop 74LS175 chip and the third D flip-flop 74LS375 chip, namely signal input ends of the third-stage time delay circuit are connected with a signal output end of a second D flip-flop 74LS375 chip in the second-stage time delay circuit, a signal output end of the third D flip-flop 74LS375 chip is connected with a signal input end of a fourth edge type D flip-flop 74LS175 chip, a signal output end of the third edge type D flip-flop 74LS175 chip is connected with a signal input end of a phase detection module, and specifically, a signal output end of the third edge type D flip-flop 74LS175 chip is connected with a signal input end of a third phase coincidence detection circuit in the phase detection module; the signal output end of the fourth edge type D flip-flop 74LS175 chip is connected with the signal input end of the phase detection module; sending the second fixed time delay signal to a third-stage time delay circuit, generating a third fixed time delay signal through a third D trigger 74LS375 chip, wherein the time delay of the third fixed time delay signal is the clock period of the third D trigger 74LS375, generating a third fine-tuning time delay signal through a third edge type D trigger 74LS175 chip, the time delay of the third fine-tuning time delay signal is the clock period of the third edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is far greater than that of the third fine-tuning time delay signal; sending the third fixed time delay signal into a fourth edge type D trigger 74LS175 chip to generate a fourth fine tuning time delay signal, wherein the time delay of the fourth fine tuning time delay signal is the clock period of the fourth edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is far larger than that of the fourth fine tuning time delay signal;
the phase detection module is used for generating a phase coincidence point pulse signal; specifically, the phase detection module is composed of a first pulse conversion circuit, a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit, a fifth pulse conversion circuit, a first phase coincidence detection circuit, a second phase coincidence detection circuit, a third phase coincidence detection circuit and a fourth phase coincidence detection circuit;
the first pulse conversion circuit, the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit all adopt pulse conversion circuits, the pulse conversion circuit consists of a pulse conversion D flip-flop 74LS375 chip, a pulse conversion logic AND gate circuit 74LS08D chip and a pulse conversion logic NOT gate circuit 74LS04N chip, wherein the D signal input end of the pulse conversion D flip-flop 74LS375 chip is connected with the A signal input end of the pulse conversion logic AND gate circuit 74LS08D chip, the Q signal output end of the pulse conversion D flip-flop 74LS375 chip is connected with the signal input end of the pulse conversion logic NOT gate circuit 74LS04N chip, the signal output end of the pulse conversion logic NOT gate circuit 74LS04N chip is connected with the B signal input end of the pulse conversion logic AND gate circuit 74LS08D chip, and the signal output end Y of the pulse conversion logic AND gate circuit 74LS08D chip is used as the signal output end of the pulse conversion circuit;
the first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip, the A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip, the A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip, the A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the fourth phase coincidence detection circuit is composed of a fourth logic AND circuit 74LS08D chip, the A4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the fifth pulse conversion circuit; the signal output end of the fourth phase coincidence detection circuit is connected with the signal input end of the gate generation module;
sending a rectangular measured pulse signal with a duty ratio of 50% generated by a measured pulse signal module into a first pulse conversion circuit, generating a rectangular measured pulse signal with a duty ratio lower than 10%, respectively sending a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal into a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit and a fifth pulse conversion circuit, and respectively generating a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal after pulse conversion;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a first fine-tuning time delay signal after pulse conversion into a first phase coincidence detection circuit to generate a first phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a second fine-tuning time delay signal after pulse conversion into a second phase coincidence detection circuit to generate a second phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a third fine-tuning time delay signal after pulse conversion into a third phase coincidence detection circuit to generate a third phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a fourth fine-tuning time delay signal after pulse conversion into a fourth phase coincidence detection circuit to generate a fourth phase coincidence point pulse;
the gate generation module is used for generating a reference gate time interval and an actual gate switching signal; specifically, the gate generating module is composed of a programmable frequency divider, a three-input three-or-gate circuit 74LS27N chip and a logic not-gate circuit 74LS04N chip, a signal output end of the programmable frequency divider is connected with a signal input end of the time interval measuring module, signal input ends of the three-input three-or-gate circuit 74LS27N chip are respectively connected with signal output ends of the first phase coincidence detecting circuit, the second phase coincidence detecting circuit, the third phase coincidence detecting circuit and the fourth phase coincidence detecting circuit, a signal output end of the three-or-gate circuit 74LS27N chip is connected with a signal input end of the logic not-gate circuit 74LS04N chip, and a signal output end of the logic not-gate circuit 74LS04N chip is connected with a signal input end of the time interval measuring module N chip; calculating the least common multiple of the frequency scale signal and the measured frequency signal according to the frequency relation between the frequency scale signal and the measured frequency signal, and generating a reference gate signal by a programmable frequency divider in a gate generation module by taking the least common multiple period as a time interval; the first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to a three-input three-NOR gate 74LS27N chip in a gate generation module, the signal output end of the three-input three-NOR gate 74LS27N chip is connected with the signal input end of a logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip generates an actual gate signal of a time interval measurement module under the control of a reference gate signal;
the time interval measuring module is used for generating a frequency scale signal and a counting value of a measured frequency signal; specifically, the time interval measuring module adopts a programmable counter and is realized by programming of FPGA hardware description language; the FPGA adopts a Cyclone IV chip EP4CE75, and the EP4CE75 type FPGA can also realize the logic functions of a programmable frequency divider and a 74LS series chip;
the data processing module is used for processing the counting values of the frequency standard signal and the measured frequency signal and generating the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system; the display module is used for receiving and displaying the processing result of the data processing module; specifically, the data processing module adopts an embedded singlechip STM32F103RBT6 chip, and the display module can adopt an LCD.
The high-precision frequency scale comparison method based on the time-frequency information measurement, which is carried out by utilizing the high-precision frequency scale comparison system based on the time-frequency information measurement, comprises the following steps:
step A, respectively carrying out digital processing on a frequency standard signal and a measured frequency signal generated by a frequency standard module and a measured frequency module by using a frequency standard pulse signal module and a measured pulse signal module, namely respectively converting the frequency standard signal generated by a 10MHz 5071A high-performance cesium atomic frequency standard and the measured frequency signal generated by a crystal oscillator or a KDS rubidium atomic clock into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with the duty ratio of 50% through a Schmidt trigger 74LS 14N;
b, sending the rectangular frequency scale pulse signal with the duty ratio of 50% to an adjustable time delay module for time delay to generate a time delay signal;
specifically, a rectangular frequency standard pulse signal with a duty ratio of 50% is sent to a first-stage delay circuit, a first fixed delay signal is generated through a first D flip-flop 74LS375 chip, the delay amount of the first fixed delay signal is the clock cycle of the first D flip-flop 74LS375 chip, a first fine-tuning delay signal is generated through a first edge type D flip-flop 74LS175 chip, the delay amount of the first fine-tuning delay signal is the clock cycle of the first edge type D flip-flop 74LS175 chip, and the delay amount of the first fixed delay signal is larger than the delay amount of the first fine-tuning delay signal;
sending the first fixed time delay signal into a second-stage time delay circuit, generating a second fixed time delay signal through a second D trigger 74LS375 chip, wherein the time delay of the second fixed time delay signal is the clock period of the second D trigger 74LS375 chip, generating a second fine tuning time delay signal through a second edge type D trigger 74LS175 chip, the time delay of the second fine tuning time delay signal is the clock period of the second edge type D trigger 74LS175 chip, and the time delay of the second fixed time delay signal is greater than the time delay of the second fine tuning time delay signal;
sending the second fixed time delay signal to a third-stage time delay circuit, generating a third fixed time delay signal through a third D trigger 74LS375 chip, wherein the time delay of the third fixed time delay signal is the clock period of the third D trigger 74LS375, generating a third fine-tuning time delay signal through a third edge type D trigger 74LS175 chip, the time delay of the third fine-tuning time delay signal is the clock period of the third edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is greater than the time delay of the third fine-tuning time delay signal;
sending the third fixed time delay signal into a fourth edge type D trigger 74LS175 chip to generate a fourth fine tuning time delay signal, wherein the time delay of the fourth fine tuning time delay signal is the clock period of the fourth edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is larger than that of the fourth fine tuning time delay signal;
step C, sending a rectangular pulse signal to be tested with a duty ratio of 50% generated by a pulse signal module to be tested into a first pulse conversion circuit, generating a rectangular pulse signal to be tested with a duty ratio lower than 10%, respectively sending a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal into a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit and a fifth pulse conversion circuit, and respectively generating a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal after pulse conversion;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a first fine-tuning time delay signal after pulse conversion into a first phase coincidence detection circuit to generate a first phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a second fine-tuning time delay signal after pulse conversion into a second phase coincidence detection circuit to generate a second phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a third fine-tuning time delay signal after pulse conversion into a third phase coincidence detection circuit to generate a third phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a fourth fine-tuning time delay signal after pulse conversion into a fourth phase coincidence detection circuit to generate a fourth phase coincidence point pulse;
calculating the least common multiple of the frequency standard signal and the measured frequency signal according to the frequency relation between the frequency standard signal and the measured frequency signal, and generating a reference gate signal by a programmable frequency divider in a gate generation module by taking the period of the least common multiple as a time interval;
the first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to a three-input three-NOR gate 74LS27N chip in a gate generation module, the signal output end of the three-input three-NOR gate 74LS27N chip is connected with the signal input end of a logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip generates an actual gate signal of a time interval measurement module under the control of a reference gate signal;
e, simultaneously sending the rectangular frequency scale pulse signal with the duty ratio of 50% and the rectangular pulse signal to be measured into a time interval measuring module, wherein the time interval measuring module consists of a programmable counter, and carrying out gapless counting under the control of an actual gate signal to obtain the count values of the rectangular frequency scale pulse signal and the rectangular pulse signal to be measured;
and F, sending the count value of the programmable counter into a data processing module, namely a singlechip STM32F103RBT6 chip for processing, and obtaining the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system.
Compared with the prior art, the high-precision frequency scale comparison system and the comparison method based on time-frequency information measurement have the following beneficial effects:
the invention avoids the normalization processing of frequency in the traditional frequency standard comparison method, simplifies the system structure by utilizing the FPGA technology, reduces the cost, overcomes the influence of additional noise and further strengthens the robustness of the system; because the adjustable time delay chain technology different from the traditional frequency standard comparison method is adopted, the influence of the complex frequency relation on the phase measurement precision is effectively eliminated, the system response time and the frequency accuracy are greatly improved, the system response time at any moment is better than 1ms, and the frequency accuracy is better than +/-6 multiplied by 10-13The method and the device realize rapid direct phase measurement of any frequency relation in a radio frequency range and accelerate the speed of frequency standard comparison.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A high-precision frequency scale comparison system based on time-frequency information measurement is characterized in that: the device comprises a frequency standard module, a tested frequency module, a frequency standard pulse signal module, a tested pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module, a display module and a power supply module; the system comprises a frequency standard module, a frequency standard pulse signal module, an adjustable time delay module, a phase detection module, a gate generation module, a time interval measurement module, a data processing module and a display module which are sequentially connected, wherein the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module;
the frequency standard module is used for generating frequency with accuracy higher than +/-1 multiplied by 10-12A magnitude frequency scale signal;
the tested frequency module is used for generating the frequency with the accuracy lower than +/-1 multiplied by 10-12Comparing the magnitude of the frequency signal to obtain a measured frequency signal;
the frequency scale pulse signal module and the pulse signal to be tested module are respectively used for generating a rectangular frequency scale pulse signal with the duty ratio of 50% and a rectangular pulse signal to be tested with the duty ratio of 50%;
the adjustable time delay module is used for generating a fixed time delay signal and a fine tuning time delay signal of the frequency standard signal;
the phase detection module is used for generating a phase coincidence point pulse signal;
the gate generation module is used for generating a reference gate time interval and an actual gate switching signal;
the time interval measuring module is used for generating a frequency scale signal and a counting value of a measured frequency signal;
the data processing module is used for processing the counting values of the frequency standard signal and the measured frequency signal and generating the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system;
and the display module is used for receiving and displaying the processing result of the data processing module.
2. The system according to claim 1, wherein the system comprises: the frequency standard module adopts a 10MHz 5071A high-performance cesium atomic frequency standard, and the frequency accuracy is +/-5 multiplied by 10-13。
3. The system according to claim 2, wherein the system comprises: the measured frequency module adopts a crystal oscillator or a KDS rubidium atomic clock, and the frequency accuracy is lower than +/-1 multiplied by 10-12Magnitude.
4. The system according to claim 3, wherein the system comprises: the frequency scale pulse signal module and the pulse signal module to be tested both adopt Schmidt contactor 74LS14N chips.
5. The system according to claim 4, wherein the system comprises: the adjustable time delay module consists of a first-stage time delay circuit, a second-stage time delay circuit and a third-stage time delay circuit;
the first-stage delay circuit consists of a first edge type D trigger 74LS175 chip and a first D trigger 74LS375 chip, signal input ends of the first edge type D trigger 74LS175 chip and the first D trigger 74LS375 chip, namely signal input ends of the first-stage delay circuit are connected with a signal output end of a frequency scale pulse signal module, a signal output end of the first D trigger 74LS375 chip is connected with a signal input end of a second-stage delay circuit, and a signal output end of the first edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module;
the second-stage time delay circuit consists of a second edge type D trigger 74LS175 chip and a second D trigger 74LS375 chip, signal input ends of the second edge type D trigger 74LS175 chip and the second D trigger 74LS375 chip, namely signal input ends of the second-stage time delay circuit are connected with a signal output end of the first D trigger 74LS375 chip in the first-stage time delay circuit, a signal output end of the second D trigger 74LS375 chip is connected with a signal input end of the third-stage time delay circuit, and a signal output end of the second edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module;
the third-stage time delay circuit is composed of a third edge type D trigger 74LS175 chip, a third D trigger 74LS375 chip and a fourth edge type D trigger 74LS175 chip, signal input ends of the third edge type D trigger 74LS175 chip and the third D trigger 74LS375 chip, namely signal input ends of the third-stage time delay circuit are connected with a signal output end of the second D trigger 74LS375 chip in the second-stage time delay circuit, a signal output end of the third D trigger 74LS375 chip is connected with a signal input end of the fourth edge type D trigger 74LS175 chip, a signal output end of the third edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module, and a signal output end of the fourth edge type D trigger 74LS175 chip is connected with a signal input end of the phase detection module.
6. The system according to claim 5, wherein the system comprises: the phase detection module consists of a first pulse conversion circuit, a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit, a fifth pulse conversion circuit, a first phase coincidence detection circuit, a second phase coincidence detection circuit, a third phase coincidence detection circuit and a fourth phase coincidence detection circuit;
the pulse conversion circuit comprises a pulse conversion D flip-flop 74LS375 chip, a pulse conversion logic AND gate 74LS08D chip and a pulse conversion logic NOT gate 74LS04N chip, a D signal input end of the pulse conversion D flip-flop 74LS375 chip is used as an input end of the pulse conversion circuit and connected with an A signal input end of the pulse conversion logic AND gate 74LS08D chip, a Q signal output end of the pulse conversion D flip-flop 74LS375 chip is connected with a signal input end of the pulse conversion logic NOT gate 74LS04N chip, a signal output end of the pulse conversion logic NOT gate 74LS04N chip is connected with a B signal input end of the pulse conversion logic AND gate 74LS08D chip, and a signal output end Y of the pulse conversion logic AND gate 74LS08D chip is used as a signal output end of the pulse conversion circuit Outputting;
the first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip, the A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B1 signal input end of the first logic AND gate circuit 74LS08D chip is connected with the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip, the A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B2 signal input end of the second logic AND gate circuit 74LS08D chip is connected with the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip, the A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B3 signal input end of the third logic AND gate circuit 74LS08D chip is connected with the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected with the signal input end of the gate generation module;
the fourth phase coincidence detection circuit is composed of a fourth logic AND circuit 74LS08D chip, the A4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the first pulse conversion circuit, and the B4 signal input end of the fourth logic AND circuit 74LS08D chip is connected with the signal output end of the fifth pulse conversion circuit; and the signal output end of the fourth phase coincidence detection circuit is connected with the signal input end of the gate generation module.
7. The system according to claim 6, wherein the system comprises: the gate generation module is composed of a programmable frequency divider, a three-input three-NOR gate 74LS27N chip and a logic NOT gate 74LS04N chip, the signal output end of the programmable frequency divider is connected with the signal input end of the time interval measurement module, the signal input end of the three-input three-NOR gate 74LS27N chip is respectively connected with the signal output ends of the first phase coincidence detection circuit, the second phase coincidence detection circuit, the third phase coincidence detection circuit and the fourth phase coincidence detection circuit, the signal output end of the three-input three-NOR gate 74LS27N chip is connected with the signal input end of the logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip is connected with the signal input end of the time interval measurement module.
8. The system according to claim 7, wherein the system comprises: the time interval measuring module adopts a programmable counter and is realized by FPGA hardware description language programming; the FPGA adopts a Cyclone IV chip EP4CE 75.
9. The system according to claim 8, wherein the system comprises: the data processing module adopts an embedded singlechip STM32F103RBT6 chip, and the display module can adopt an LCD.
10. A high-precision frequency scale comparison method based on time-frequency information measurement, which is performed by using the high-precision frequency scale comparison system based on time-frequency information measurement according to claim 9, and comprises the following steps:
step A, respectively carrying out digital processing on a frequency standard signal and a measured frequency signal generated by a frequency standard module and a measured frequency module by using a frequency standard pulse signal module and a measured pulse signal module, namely respectively converting the frequency standard signal generated by a 10MHz 5071A high-performance cesium atomic frequency standard and the measured frequency signal generated by a crystal oscillator or a KDS rubidium atomic clock into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with the duty ratio of 50% through a Schmidt trigger 74LS 14N;
b, sending the rectangular frequency scale pulse signal with the duty ratio of 50% to an adjustable time delay module for time delay to generate a time delay signal;
specifically, a rectangular frequency standard pulse signal with a duty ratio of 50% is sent to a first-stage delay circuit, a first fixed delay signal is generated through a first D flip-flop 74LS375 chip, the delay amount of the first fixed delay signal is the clock cycle of the first D flip-flop 74LS375 chip, a first fine-tuning delay signal is generated through a first edge type D flip-flop 74LS175 chip, the delay amount of the first fine-tuning delay signal is the clock cycle of the first edge type D flip-flop 74LS175 chip, and the delay amount of the first fixed delay signal is larger than the delay amount of the first fine-tuning delay signal;
sending the first fixed time delay signal into a second-stage time delay circuit, generating a second fixed time delay signal through a second D trigger 74LS375 chip, wherein the time delay of the second fixed time delay signal is the clock period of the second D trigger 74LS375 chip, generating a second fine tuning time delay signal through a second edge type D trigger 74LS175 chip, the time delay of the second fine tuning time delay signal is the clock period of the second edge type D trigger 74LS175 chip, and the time delay of the second fixed time delay signal is greater than the time delay of the second fine tuning time delay signal;
sending the second fixed time delay signal to a third-stage time delay circuit, generating a third fixed time delay signal through a third D trigger 74LS375 chip, wherein the time delay of the third fixed time delay signal is the clock period of the third D trigger 74LS375, generating a third fine-tuning time delay signal through a third edge type D trigger 74LS175 chip, the time delay of the third fine-tuning time delay signal is the clock period of the third edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is greater than the time delay of the third fine-tuning time delay signal;
sending the third fixed time delay signal into a fourth edge type D trigger 74LS175 chip to generate a fourth fine tuning time delay signal, wherein the time delay of the fourth fine tuning time delay signal is the clock period of the fourth edge type D trigger 74LS175 chip, and the time delay of the third fixed time delay signal is larger than that of the fourth fine tuning time delay signal;
step C, sending a rectangular pulse signal to be tested with a duty ratio of 50% generated by a pulse signal module to be tested into a first pulse conversion circuit, generating a rectangular pulse signal to be tested with a duty ratio lower than 10%, respectively sending a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal into a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit and a fifth pulse conversion circuit, and respectively generating a first fine-tuning time delay signal, a second fine-tuning time delay signal, a third fine-tuning time delay signal and a fourth fine-tuning time delay signal after pulse conversion;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a first fine-tuning time delay signal after pulse conversion into a first phase coincidence detection circuit to generate a first phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a second fine-tuning time delay signal after pulse conversion into a second phase coincidence detection circuit to generate a second phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a third fine-tuning time delay signal after pulse conversion into a third phase coincidence detection circuit to generate a third phase coincidence point pulse;
sending a rectangular pulse signal to be detected with a duty ratio lower than 10% and a fourth fine-tuning time delay signal after pulse conversion into a fourth phase coincidence detection circuit to generate a fourth phase coincidence point pulse;
calculating the least common multiple of the frequency standard signal and the measured frequency signal according to the frequency relation between the frequency standard signal and the measured frequency signal, and generating a reference gate signal by a programmable frequency divider in a gate generation module by taking the period of the least common multiple as a time interval;
the first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to a three-input three-NOR gate 74LS27N chip in a gate generation module, the signal output end of the three-input three-NOR gate 74LS27N chip is connected with the signal input end of a logic NOT gate 74LS04N chip, and the signal output end of the logic NOT gate 74LS04N chip generates an actual gate signal of a time interval measurement module under the control of a reference gate signal;
e, simultaneously sending the rectangular frequency scale pulse signal with the duty ratio of 50% and the rectangular pulse signal to be measured into a time interval measuring module, wherein the time interval measuring module consists of a programmable counter, and carrying out gapless counting under the control of an actual gate signal to obtain the count values of the rectangular frequency scale pulse signal and the rectangular pulse signal to be measured;
and F, sending the count value of the programmable counter into a data processing module, namely a singlechip STM32F103RBT6 chip for processing, and obtaining the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system.
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| CN113933612B (en) * | 2021-10-12 | 2022-11-22 | 湖南师范大学 | Phase noise measurement system and measurement method based on Beidou navigation satellite payload |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1410776A (en) * | 2002-11-27 | 2003-04-16 | 湖南大学 | Homosequence specific phase frequency measurement method and high accuracy frequency meter |
| RU2002125772A (en) * | 2002-09-27 | 2004-03-27 | Пензенский технологический институт | DEVICE FOR MEASURING THE FREQUENCY OF ELECTRICAL SIGNALS |
| CN102334038A (en) * | 2009-02-27 | 2012-01-25 | 古野电气株式会社 | Phase determining device and frequency determining device |
| CN103176045A (en) * | 2013-03-01 | 2013-06-26 | 西安电子科技大学 | Method and system for pilot frequency bi-phase coincidence detection based on coincidence pulse counting |
| CN104090160A (en) * | 2014-06-04 | 2014-10-08 | 郑州轻工业学院 | High-precision frequency measuring device |
| CN105182069A (en) * | 2015-08-10 | 2015-12-23 | 郑州轻工业学院 | High resolution group quantization phase processing method under pilot frequency architecture |
| CN106646282A (en) * | 2017-01-03 | 2017-05-10 | 中国地质大学（武汉） | Method and circuit for improving FID signal frequency measurement precision based on quantized time delay method |
| CN206321776U (en) * | 2017-01-03 | 2017-07-11 | 中国地质大学（武汉） | A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method |
| CN107817383A (en) * | 2017-10-31 | 2018-03-20 | 郑州轻工业学院 | A kind of High Precise Frequency Measurement System based on moving emitter |
| CN109030939A (en) * | 2018-06-01 | 2018-12-18 | 中国人民解放军陆军工程大学石家庄校区 | A kind of multi-channel synchronous frequency measuring device |
| CN111769822A (en) * | 2020-06-30 | 2020-10-13 | 山东卓奇电气科技有限公司 | Frequency measuring device |
-
2021
- 2021-04-12 CN CN202110387851.6A patent/CN113092858B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2002125772A (en) * | 2002-09-27 | 2004-03-27 | Пензенский технологический институт | DEVICE FOR MEASURING THE FREQUENCY OF ELECTRICAL SIGNALS |
| CN1410776A (en) * | 2002-11-27 | 2003-04-16 | 湖南大学 | Homosequence specific phase frequency measurement method and high accuracy frequency meter |
| CN102334038A (en) * | 2009-02-27 | 2012-01-25 | 古野电气株式会社 | Phase determining device and frequency determining device |
| CN103176045A (en) * | 2013-03-01 | 2013-06-26 | 西安电子科技大学 | Method and system for pilot frequency bi-phase coincidence detection based on coincidence pulse counting |
| CN104090160A (en) * | 2014-06-04 | 2014-10-08 | 郑州轻工业学院 | High-precision frequency measuring device |
| CN105182069A (en) * | 2015-08-10 | 2015-12-23 | 郑州轻工业学院 | High resolution group quantization phase processing method under pilot frequency architecture |
| CN106646282A (en) * | 2017-01-03 | 2017-05-10 | 中国地质大学（武汉） | Method and circuit for improving FID signal frequency measurement precision based on quantized time delay method |
| CN206321776U (en) * | 2017-01-03 | 2017-07-11 | 中国地质大学（武汉） | A kind of circuit that FID signal frequency-measurement accuracy is improved based on quantization delay method |
| CN107817383A (en) * | 2017-10-31 | 2018-03-20 | 郑州轻工业学院 | A kind of High Precise Frequency Measurement System based on moving emitter |
| CN109030939A (en) * | 2018-06-01 | 2018-12-18 | 中国人民解放军陆军工程大学石家庄校区 | A kind of multi-channel synchronous frequency measuring device |
| CN111769822A (en) * | 2020-06-30 | 2020-10-13 | 山东卓奇电气科技有限公司 | Frequency measuring device |
Non-Patent Citations (2)
| Title |
|---|
| Time-To-Digital Converter with adjustable resolution using a digital Vernier Ring Oscillator;A. Annagrebah et al.;《2018 Conference on Design of Circuits and Integrated Systems (DCIS)》;20181116;第1-4页 * |
| 基于时间间隔测量的宽范围高分辨率时间同步检测方法;杜宝强 等;《电子学报》;20130630;第41卷(第6期);第1076-1083页 * |
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