You are mixing up integer register size and instruction length. RISC-V has varia... | Hacker News

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brucehoult on Dec 2, 2021 | parent | context | favorite | on: “Risc V greatly underperforms”

You are mixing up integer register size and instruction length.

RISC-V has variants with 32 bit, 64 bit, or (not yet fully specified or implemented) 128 bit registers.

RISC-V has instructions of length 32 bits and, optionally but almost universally, 16 bit length.

bpye on Dec 2, 2021 | [–]

Ah yes, I misunderstood the original comment as implying that RISC-V C had 16 bit register length, rather than opcode length.

Taniwha on Dec 2, 2021 | [–]

The E version only has half as many registers

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