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uart

Here are 76 public repositories matching this topic...

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Jul 6, 2024
Verilog

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

ZipCPU / wbuart32

A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

Updated Jan 29, 2024
Verilog

riscv-steel / riscv-steel

Free collection of hardware modules written in Verilog for FPGAs and embedded systems.

microcontroller cpu gpio core processor riscv spi uart mcu steel risc-v rv32i system-on-chip zicsr

Updated Jul 8, 2024
Verilog

WangXuan95 / FPGA-UART

Include 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

fpga rtl verilog uart

Updated Sep 14, 2023
Verilog

ben-marshall / uart

A simple implementation of a UART modem in Verilog.

fpga hardware verilog uart uart-verilog verilog-hdl

Updated Nov 10, 2021
Verilog

hell03end / verilog-uart

Simple 8-bit UART realization on Verilog HDL.

fpga verilog uart hdl quartus

Updated Apr 27, 2024
Verilog

ultraembedded / core_soc

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

gpio fpga timer verilog spi uart

Updated May 8, 2020
Verilog

ultraembedded / core_dbg_bridge

UART -> AXI Bridge

fpga verilog uart axi4

Updated Jul 1, 2021
Verilog

tongplw / HW-Syn-Lab

⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

ultraembedded / core_usb_uart

USB serial device (CDC-ACM)

fpga verilog uart serial-port usb-cdc usb-serial usb-device

Updated Jun 28, 2020
Verilog

matt-alencar / fpga-uart-tx-rx

Basic UART TX/RX module for FPGA

fpga verilog uart hdl uart-protocol soft-core uart-interface

Updated Oct 18, 2018
Verilog

nju-mips / noop-lo

A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.

gpio fpga sbt mips vivado uart noop verilator

Updated Feb 10, 2020
Verilog

hakan-demirli / PID-FPGA

PID controller on an FPGA with custom RS232 addressing protocol.

fpga controller matlab pid verilog uart rs232 dc-motor

Updated Sep 7, 2021
Verilog

lingbai-kong / computer-system

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

cpu gpio fpga uart sdcard big-endian wishbone ucosii sopc tongji-university ddr2 dynamic-pipelines openmips

Updated Jun 3, 2023
Verilog

tongplw / Undertale-Verilog

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

fpga verilog uart fpga-game vga undertale basys3 fpga-board verilog-project basys3-fpga

Updated Jul 3, 2020
Verilog

ilyajob05 / verilog_modules

verilog modules

synchronization fpga i2c memory timer verilog spi xilinx uart usart 7-segment xilinx-fpga nexys4 pll rmii nexys-4-spartan-3e nexys4-board

Updated May 4, 2020
Verilog

abdelazeem201 / ASIC-Implementation-UART

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr

Updated Mar 30, 2022
Verilog

splinedrive / i2c_sdd1306_framebuffer

It is a fpga implementation of an i2c master, framebuffer for sdd1306 display

fpga i2c verilog uart oled ice40 ds3132 sdd1306

Updated May 14, 2021
Verilog

BrianHGinc / Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor

Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.

hex-editor verilog uart rs232 hdl

Updated Jan 15, 2022
Verilog

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