sgherbst / svreal Star 42 Code Issues Pull requests Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim Updated Jan 13, 2021 SystemVerilog
sgherbst / msdsl Star 37 Code Issues Pull requests Automatic generation of real number models from analog circuits python generator simulation analog model synthesis rnm mixed-signal ams synthesizable analog-circuits real-number-modeling Updated Apr 2, 2024 Python
SnrNotHere16 / Asynchronous-FIFO Star 4 Code Issues Pull requests An FPGA implementation of Cummings' Asynchronous FIFO fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level Updated Apr 14, 2022 SystemVerilog
erictaur / Component-Labeler Star 1 Code Issues Pull requests A hardware implementation of component labeling verilog synthesizable component-labeler Updated Jan 13, 2021 Verilog