Here are
66 public repositories
matching this topic...
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Updated
Sep 7, 2020
Verilog
Simple 8-bit UART realization on Verilog HDL.
Updated
Apr 27, 2024
Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Updated
Sep 15, 2023
Verilog
Test for video output using the ADV7513 chip on a de10 nano board
Updated
Feb 14, 2019
Verilog
A 32-bit MIPS processor used Altera Quartus II with Verilog.
Updated
Sep 20, 2018
Verilog
Updated
Apr 21, 2019
Verilog
Updated
Aug 17, 2021
Verilog
A verilog HDL based project to control a servomotor with voice commands from an android phone.
Updated
Nov 11, 2019
Verilog
fpga verilog risc-v rv32i cpu
Updated
Apr 18, 2023
Verilog
Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine
Updated
Mar 21, 2019
Verilog
2019年UPC应用物理专业《数字电子技术课程设计》任务内容:数字时钟设计
Updated
Jul 2, 2019
Verilog
Updated
Jul 14, 2019
Verilog
Simple LED blink example for DE2-115
Updated
Jun 6, 2018
Verilog
HDL project of Matrix Processing Unit for FPGA devices.
Updated
Sep 2, 2020
Verilog
Projekat iz Arhitekture Racunara (AR-a)
Updated
Feb 27, 2024
Verilog
Updated
Sep 21, 2020
Verilog
Ping Pong game on an FPGA in Verilog using HDMI
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Jun 14, 2020
Verilog
Implementation of an Edge Detection Filter Using the Avalon Interface
Updated
Jan 30, 2023
Verilog
CAD for automatically configuring FPGA "Marsohod"
Updated
May 1, 2023
Verilog
Play and learn some valuable lessons with a generic Ebay/China CPLD board featuring an Altera/Intel MAX II CPLD. The hardware is pretty crappy (just mine?) so it won't be much fun.
Updated
Sep 18, 2019
Verilog
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