Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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Updated
Jan 31, 2023 - VHDL
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Expiremental Speech Recognition System using VHDL & MATLAB.
An FPGA implementation of a digital storage oscilloscope.
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)
Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.
Multi-level second-order (Silva Steensgaard Structure) delta-sigma modulator
Firmware and software for the implementation of a FIR filter co-processor in FPGA with IPBUS protocol
IIR Filter for audio application
Designed and Implemented a low pass filter in Nexys 4 FPGA
Final project for Hardware Course implemented with VHDL
Image processing - 3x3 Median Filter (Grayscale)
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