CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis
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Updated
Oct 3, 2023 - SystemVerilog
CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis
Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
Resources accompanying my talk at NLUUG 2022
Laboratories of 'Microelectronic Systems' course at PoliTo
Wolf sheep cabbage river crossing puzzle ASIC design (🐺🐐🥬🚣)
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
Undegraduate Capstone Project - Spring'21 (VIT University).
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
This repository contains the work done during learning LinuxFoundationX LFD111x Building a RISC-V CPU Core
A simple Recap for different Digital Design topics from different references and books.
Blake2 RTL implementation
High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC
TCL Script automating the frontend of ASIC design
300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design
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