University project about the game rock-paper-scissors
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Updated
Feb 19, 2024 - SystemVerilog
University project about the game rock-paper-scissors
Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
This was the project assignment for the Digital Logic Design course.
CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis
Learned as a part of Computer architecture Course
Datapath and Control for a Turing Complete ISA with Interrupt Handling
Uni project about the game rock-paper-scissors
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