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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
The official repository for the gem5 computer-system architecture simulator.
Sourcetrail - free and open-source interactive source explorer
Flexible Intermediate Representation for RTL
A template project for beginning new Chisel work
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
Qflow full end-to-end digital synthesis flow for ASIC designs
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
RSD: RISC-V Out-of-Order Superscalar Processor
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Open-source high-performance RISC-V processor
SystemVerilog parser library fully compliant with IEEE 1800-2017
SystemVerilog preprocessor, lexer and parser with examples
Scala 2 compiler and standard library. Scala 2 bugs at https://github.com/scala/bug; Scala 3 at https://github.com/scala/scala3
A copy of the Lua development repository, as seen by the Lua team. Mirrored irregularly. Please DO NOT send pull requests or any other stuff. All communication should be through the Lua mailing lis…
