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@svunit
SVUnit svunit
An xUnit testing framework for SystemVerilog (and other HDLs)
@cnrv
CNRV cnrv
为推广RISC-V尽些薄力

China

@openhwgroup
OpenHW Group openhwgroup

Ottawa, Ontario, Canada

@OpenXiangShan
XiangShan OpenXiangShan
Open-source high-performance RISC-V processor
@verilator
Verilator verilator
Verilator Open-Source SystemVerilog simulator and lint system
@chipsalliance
CHIPS Alliance chipsalliance
Common Hardware for Interfaces, Processors and Systems
@ZipCPU
Dan Gisselquist ZipCPU

Gisselquist Technology, LLC

@drom
Aliaksei Chapyzhenka drom
always @ posedge

@sifive Terra ⴲ

@torvalds
Linus Torvalds torvalds

Linux Foundation Portland, OR