You like pytorch? You like micrograd? You love tinygrad! ❤️

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

A Rocket-based RISC-V superscalar in-order core

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Verilog Ethernet components for FPGA implementation

A modern hardware definition language and toolchain based on Python

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

The missing test suite for RISC-V V extension.

Verilog PCI express components

Verilog AXI components for FPGA implementation

VRoom! RISC-V CPU

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Open-source high-performance RISC-V processor

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

RISC-V Zve32x Vector Coprocessor

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Run Rocket Chip on VCU128

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online workshop: https://google.githu…