A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on RISC-V research chips.

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)

Accelergy is an energy estimation infrastructure for accelerator energy estimations

A simple GUI designer for the python tkinter module

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

FPGA Stitching with FABulous and OpenLane 2

MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).

List of awesome open source hardware tools, generators, and reusable designs

compiler learning resources collect.

Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).

Llama中文社区，Llama3在线体验和微调模型已开放，实时汇总最新Llama3学习资料，已将所有代码更新适配Llama3，构建最好的中文Llama大模型，完全开源可商用

Chisel RISC-V Vector 1.0 Implementation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V

A Python-base EBPF code generator

A curated list of awesome projects related to eBPF.

hBPF = eBPF in hardware

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Tengine is a lite, high performance, modular inference engine for embedded device

A comparison and benchmark for testing CPU versus Vector acceleration of tensor and image conversion sublayers

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

A Darknet-YOLOv3 with support for RISC-V Vector accelerator offloading

A completely configurable RISC-V Out of Order Core with a base model geared towards maximizing performance