Dabhade et al., 2017 - Google Patents

A reconfigurable and scalable FPGA architecture for bilateral filtering

Dabhade et al., 2017

Document ID
8153884791750147893
Author
Dabhade S
Rathna G
Chaudhury K
Publication year
Publication venue
IEEE Transactions on Industrial Electronics

External Links

Snippet

Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, fieldprogrammable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration, e.g. from bit-mapped to bit-mapped creating a similar image
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement

Similar Documents

Publication Publication Date Title
Dabhade et al. A reconfigurable and scalable FPGA architecture for bilateral filtering
Qian et al. An architecture for fault-tolerant computation with stochastic logic
Kulkarni et al. Low overhead architectures for OMP compressive sensing reconstruction algorithm
Rao et al. Implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages
Monson et al. Implementing high-performance, low-power FPGA-based optical flow accelerators in C
Malik et al. Gaussian random number generation: A survey on hardware architectures
Chen et al. High-level synthesis algorithm for the design of reconfigurable constant multiplier
Xu et al. Toward self-tunable approximate computing
Schatz Low-latency histogram equalization for infrared image sequences: a hardware implementation
Pal et al. An efficient FPGA implementation of optimized anisotropic diffusion filtering of images
Sarkar et al. Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
Muthukumar et al. Image processing algorithms on reconfigurable architecture using HandelC
Xydis et al. A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization
Bhadouria et al. A novel image impulse noise removal algorithm optimized for hardware accelerators
Horé et al. On the design of optimal 2D filters for efficient hardware implementations of image processing algorithms by using power-of-two terms
Garcés-Socarrás et al. Library for model-based design of image processing algorithms on FPGAs
Kumar et al. Implementation of image processing lab using Xilinx System Generator
Zhang et al. Exploring slice-energy saving on an video processing FPGA platform with approximate computing
Singh et al. Power estimation of FIR filter based on IP modeling for DSP and communication applications
Chen et al. Iterative linear interpolation based on fuzzy gradient model for low-cost VLSI implementation
Güngör et al. A logistic map Runge Kutta-4 solution for FPGA using fixed point representation
Martínez-Alvarez et al. A scalable CNN architecture and its application to short exposure stellar images processing on a HPRC
Patel et al. High performance robust FIR filter design using radix-8 based improved booth multiplier for signal processing application
Acharya et al. FPGA Based Non Uniform Illumination Correction in Image Processing Application 2
Zhang et al. An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels