Xu et al., 2018 - Google Patents
Toward self-tunable approximate computingXu et al., 2018
- Document ID
- 1767806541385670113
- Author
- Xu S
- Schafer B
- Publication year
- Publication venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
External Links
Snippet
Many applications show tolerance to inaccuracies. These can be exploited to build faster circuits with smaller area and lower power. This is particularly true for the hardware accelerators in heterogeneous computing systems. A major problem with approximate …
- 230000003068 static 0 abstract description 11
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Akbari et al. | X-CGRA: An energy-efficient approximate coarse-grained reconfigurable architecture | |
Xu et al. | Toward self-tunable approximate computing | |
Xu et al. | Exposing approximate computing optimizations at different levels: From behavioral to gate-level | |
Shafique et al. | Cross-layer approximate computing: From logic to architectures | |
Reda et al. | Approximate circuits | |
Abdelhalim et al. | An integrated high-level hardware/software partitioning methodology | |
Westby et al. | FPGA acceleration on a multi-layer perceptron neural network for digit recognition | |
Givargis et al. | Instruction-based system-level power evaluation of system-on-a-chip peripheral cores | |
Chen et al. | PAM: A piecewise-linearly-approximated floating-point multiplier with unbiasedness and configurability | |
Xu et al. | Approximate reconfigurable hardware accelerator: Adapting the micro-architecture to dynamic workloads | |
Chowdhury et al. | AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores | |
Park et al. | A multi-granularity power modeling methodology for embedded processors | |
Casseau et al. | Design of multi-mode application-specific cores based on high-level synthesis | |
Kim et al. | Dataflow to hardware synthesis framework on fpgas | |
Tanougast et al. | Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system | |
Soares et al. | An energy-efficient and approximate accelerator design for real-time canny edge detection | |
Zhang et al. | Exploring slice-energy saving on an video processing FPGA platform with approximate computing | |
Chowdhury et al. | Leveraging automatic high-level synthesis resource sharing to maximize dynamical voltage overscaling with error control | |
Kedem et al. | Optimizing energy to minimize errors in dataflow graphs using approximate adders | |
Mehra et al. | Algorithm and architectural level methodologies for low power | |
Park et al. | Methodology for multi-granularity embedded processor power model generation for an ESL design flow | |
Choi et al. | Domain-specific modeling for rapid energy estimation of reconfigurable architectures | |
Yan et al. | Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures | |
Mohanty et al. | A model-based methodology for application specific energy efficient data path design using FPGAs | |
Ranjan et al. | Automatic synthesis techniques for approximate circuits |