Zeghid et al., 2023 - Google Patents

Speed/area-efficient ECC processor implementation over GF (2 m) on FPGA via novel algorithm-architecture co-design

Zeghid et al., 2023

Document ID
18389565212569996754
Author
Zeghid M
Ahmed H
Chehri A
Sghaier A
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

With the rapid evolution of security technology, small field-size elliptic curve-based point multiplication (PM) has gradually become obsolete, leading to the implementation of PM with large field sizes. From this perspective, in this article, through a novel algorithm …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
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