Tawalbeh et al., 2010 - Google Patents

Efficient FPGA implementation of a programmable architecture for GF (p) elliptic curve crypto computations

Tawalbeh et al., 2010

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Document ID
2224607248508940063
Author
Tawalbeh L
Mohammad A
Gutub A
Publication year
Publication venue
Journal of Signal Processing Systems

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This paper presents a processor architecture for elliptic curve cryptography computations over GF (p). The speed to compute the Elliptic-curve point multiplication over the prime fields GF (p) is increased by using the maximum degree of parallelism, and by carefully selecting …
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Classifications

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    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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    • G06F7/724—Finite field arithmetic
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