WO2024218909A1

WO2024218909A1 - Quantum computing system, quantum computing device, quantum computing method, and program

Info

Publication number: WO2024218909A1
Application number: PCT/JP2023/015642
Authority: WO
Inventors: 薫山本; 傑遠藤; 泰成鈴木; 裕己徳永
Original assignee: 日本電信電話株式会社
Priority date: 2023-04-19
Filing date: 2023-04-19
Publication date: 2024-10-24

Abstract

A quantum computing system according to one aspect of the present disclosure includes a plurality of quantum computing devices. The quantum computing devices each include: a sharing unit that shares a two-qubit state in which fidelity between an error and a Bell state is equal to a prescribed value or greater with respect to another quantum computing device; a Twirling operation unit that performs a Twirling operation on the two-qubit state so as to achieve a prescribed state; an error rate estimation unit that estimates an error rate for the prescribed state; a quantum circuit execution unit that executes a quantum circuit including a non-local CNOT gate realized by an LOCC operation with respect to the prescribed state; and an error removal unit that removes an error of the non-local CNOT gate on the basis of the error rate.

Description

Quantum computing system, quantum computing device, quantum computing method, and program

This disclosure relates to a quantum computing system, a quantum computing device, a quantum computing method, and a program.

In quantum information processing, the controlled NOT gate (hereafter also referred to as the CNOT gate) is an essential gate for enabling arbitrary quantum computation, and methods for implementing a highly accurate CNOT gate are being researched.

On the other hand, because the number of qubits in current quantum computers is still small, distributed quantum computing is being considered, in which multiple quantum computers, each equipped with a small number of qubits, are used to effectively create a large number of qubits. In distributed quantum computing, quantum computers are generally located far apart from each other, so it is essential to execute a CNOT gate (also called a nonlocal CNOT gate) between the qubits of these quantum computers with high accuracy. Two representative methods of executing a nonlocal CNOT gate with high accuracy are known: the method described in Non-Patent Document 1 and the method described in Non-Patent Document 2.

However, both the method described in Non-Patent Document 1 and the method described in Non-Patent Document 2 have advantages and disadvantages, and there is no intermediate method between the two methods.

This disclosure has been made in consideration of the above points, and provides technology that can execute a non-local CNOT gate with high accuracy.

A quantum computing system according to one aspect of the present disclosure is a quantum computing system including a plurality of quantum computing devices, each of which has a sharing unit that shares a two-qubit state with other quantum computing devices, the two-qubit state having a fidelity to the error Bell state equal to or greater than a predetermined value, a twirling operation unit that performs a twirling operation on the two-qubit state to create a predetermined state, an error rate estimation unit that estimates the error rate of the predetermined state, a quantum circuit execution unit that executes a quantum circuit including a nonlocal CNOT gate realized by a LOCC operation on the predetermined state, and an error removal unit that removes errors in the nonlocal CNOT gate based on the error rate.

Technology is provided that can execute non-local CNOT gates with high accuracy.

1 is a diagram illustrating an example of the overall configuration of a quantum computing system according to an embodiment of the present invention. FIG. 1 is a diagram illustrating an example of the configuration of a quantum computing device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a hardware configuration of a control device according to the present embodiment. FIG. 2 is a diagram illustrating an example of a functional configuration of a control device according to the present embodiment. 1 is a flowchart showing a quantum computing process in Example 1. 13 is a flowchart showing a quantum computing process in Example 2.

Below, one embodiment of the present invention will be described.

<Typical implementation of non-local CNOT gate>
Two representative methods for implementing a highly accurate nonlocal CNOT gate are known: the method described in Non-Patent Document 1 and the method described in Non-Patent Document 2.

The method described in Non-Patent Document 1 involves sharing in advance an entangled state called a Bell state between quantum computers located at distant locations, and executing a CNOT gate using local operations within each quantum computer and classical communication between the quantum computers. Hereinafter, local operations within a quantum computer and classical communication between quantum computers will be collectively referred to as LOCC (Local operation and classical communication) operations.

Because errors generally exist in Bell states that can be shared in advance, the method described in Non-Patent Document 1 first performs an operation called entanglement distillation (Reference 1) to create a Bell state with fewer errors from multiple Bell states using the LOCC operation. This has the disadvantages that a large number of Bell states are required in the entanglement distillation process and that the distillation protocol takes time to execute. On the other hand, compared to the method described in Non-Patent Document 2, it has the advantage that the number of calculations does not increase exponentially with respect to the accuracy of the CNOT gate.

The method described in Non-Patent Document 2 is a method of executing a pseudo CNOT gate using only LOCC operations in quantum computers located at different locations. This method has the advantage of not requiring prior sharing of Bell states or entanglement distillation, but has the disadvantage that the number of calculations required to obtain calculation results of the same accuracy increases exponentially compared to the method described in Non-Patent Document 1.

As such, the method described in Non-Patent Document 1 and the method described in Non-Patent Document 2 each have their own advantages and disadvantages.

Then, in the following embodiment, a quantum computing system 1 capable of executing a highly accurate nonlocal CNOT gate using an intermediate method between these two methods will be described. For example, when executing a quantum circuit in which the number of calculations required to execute a nonlocal CNOT gate using only LOCC operations is too high while sharing a large number of Bell states and entanglement distillation is not desired, the quantum computing system 1 according to this embodiment can be used to eliminate the time cost required for entanglement distillation while also reducing the number of calculations required for the quantum circuit. Note that the following embodiment assumes a case in which quantum computation is performed to find some expected value using a quantum circuit including a nonlocal CNOT gate.

<Example of overall configuration of quantum computing system 1>
An example of the overall configuration of a quantum computing system 1 according to this embodiment is shown in Fig. 1. As shown in Fig. 1, the quantum computing system 1 according to this embodiment includes a plurality of quantum computing devices 10. In addition, each quantum computing device 10 is communicatively connected via a communication network 20 including, for example, a LAN (Local Area Network) or the like. Note that the quantum computing device 10 may be called, for example, a "quantum computer" or a "quantum computing node".

Hereinafter, when distinguishing between the multiple quantum computing devices 10, they will be referred to as "quantum computing device 10-1," "quantum computing device 10-2," etc. In addition, in the following, as an example, the quantum computing system 1 is assumed to be composed of two quantum computing devices 10, quantum computing device 10-1 and quantum computing device 10-2. However, the embodiment described below can be similarly applied to a quantum computing system 1 composed of three or more quantum computing devices 10.

<Configuration Example of Quantum Computing Device 10>
An example of the configuration of the quantum computing device 10 according to this embodiment is shown in Fig. 2. As shown in Fig. 2, the quantum computing device 10 according to this embodiment includes a control device 100 and a quantum processor 200.

The control device 100 realizes quantum computation by communicating with other control devices 100 (classical communication) and controlling the quantum processor 200. That is, to realize quantum computation, the control device 100 communicates with other control devices 100 (classical communication), transmits control signals to the quantum processor 200, and obtains computation results from the quantum processor 200. The control device 100 is realized, for example, by a classical computer.

The quantum processor 200 configures a quantum two-level system called a qubit or quantum bit (physical quantum bit), and performs initialization, gate operations (e.g., unitary transformation, etc.), physical operations, etc. on the qubit. There are no particular limitations on the physical system for realizing the qubit, and any physical system may be used. For example, superconducting circuits, ion traps, photons, quantum dots, etc. may be used as the physical system.

Hereinafter, when distinguishing between the control device 100 included in quantum computing device 10-1 and the control device 100 included in quantum computing device 10-2, the control device 100 included in quantum computing device 10-1 will be referred to as the "control device 100-1," and the control device 100 included in quantum computing device 10-2 will be referred to as the "control device 100-2." Similarly, for the quantum processor 200, the quantum processor 200 included in quantum computing device 10-1 will be referred to as the "quantum processor 200-1," and the quantum processor 200 included in quantum computing device 10-2 will be referred to as the "quantum processor 200-2."

<Example of hardware configuration of control device 100>
An example of a hardware configuration of the control device 100 according to this embodiment is shown in Fig. 3. As shown in Fig. 3, the control device 100 according to this embodiment includes an input device 101, a display device 102, an external I/F 103, a communication I/F 104, a RAM (Random Access Memory) 105, a ROM (Read Only Memory) 106, an auxiliary storage device 107, and a processor 108. Each of these pieces of hardware is connected to each other via a bus 109 so as to be able to communicate with each other.

The input device 101 is, for example, a keyboard, a mouse, a touch panel, a physical button, etc. The display device 102 is, for example, a display, a display panel, etc. Note that the control device 100 does not have to have at least one of the input device 101 and the display device 102, for example.

The external I/F 103 is an interface with external devices such as a recording medium 103a. Examples of recording media 103a include a CD (Compact Disc), a DVD (Digital Versatile Disk), an SD memory card (Secure Digital memory card), and a USB (Universal Serial Bus) memory card.

The communication I/F 104 is an interface for transmitting and receiving data (classical communication) with other control devices 100, and transmitting and receiving various signals with the quantum processor 200. The RAM 105 is a volatile semiconductor memory (storage device) that temporarily stores programs and data. The ROM 106 is a non-volatile semiconductor memory (storage device) that can store programs and data even when the power is turned off. The auxiliary storage device 107 is a non-volatile storage device (storage device) such as a HDD (Hard Disk Drive), SSD (Solid State Drive), flash memory, etc. The processor 108 is an arithmetic device such as a CPU (Central Processing Unit), etc.

Note that the hardware configuration shown in FIG. 3 is an example, and the hardware configuration of the control device 100 is not limited to this. For example, the control device 100 may have multiple auxiliary storage devices 107 or multiple processors 108, may not have some of the hardware shown in the figure, or may have various hardware other than the hardware shown in the figure.

<Example of functional configuration of control device 100>
An example of the functional configuration of the control device 100 according to this embodiment is shown in Fig. 4. As shown in Fig. 4, the control device 100 according to this embodiment has a quantum computing control unit 110 and a storage unit 120. The quantum computing control unit 110 is realized, for example, by a process in which one or more programs installed in the control device 100 are executed by the processor 108 or the like. The storage unit 120 is realized, for example, by the RAM 105, the auxiliary storage device 107, or the like.

The quantum computing control unit 110 realizes quantum computing to find a certain expected value using a quantum circuit including a non-local CNOT gate by communicating with other control devices 100 (classical communication) and controlling the quantum processor 200.

The storage unit 120 stores information necessary for the quantum computation performed by the quantum computation control unit 110.

Here, the quantum computing control unit 110 includes a state sharing unit 111, a twirling operation unit 112, an error rate estimation unit 113, a quantum circuit execution unit 114, and an error removal unit 115. The state sharing unit 111 shares a Bell state with other quantum computing devices 10 by a known method. Generally, an error may exist in this Bell state. The twirling operation unit 112 performs an operation called a twirling operation on the Bell state. The error rate estimation unit 113 estimates the error rate of the state after the twirling operation. The quantum circuit execution unit 114 executes a quantum circuit including a nonlocal CNOT gate. At this time, the quantum circuit execution unit 114 executes the nonlocal CNOT gate by performing a LOCC operation on the state after the twirling operation. The error elimination unit 115 eliminates errors in the non-local CNOT gate executed by the quantum circuit execution unit 114 based on the error rate estimated by the error rate estimation unit 113. This allows for the expected value of the quantum circuit from which errors have been eliminated (or, more accurately, reduced).

Hereinafter, when distinguishing between the quantum computing control unit 110 possessed by the control device 100-1 and the quantum computing control unit 110 possessed by the control device 100-2, the quantum computing control unit 110 possessed by the control device 100-1 will be referred to as the "quantum computing control unit 110-1," and the quantum computing control unit 110 possessed by the control device 100-2 will be referred to as the "quantum computing control unit 110-2." Similarly, for the memory unit 120, the memory unit 120 possessed by the control device 100-1 will be referred to as the "memory unit 120-1," and the memory unit 120 possessed by the control device 100-2 will be referred to as the "memory unit 120-2." Similarly, when distinguishing between the quantum computing control unit 110-1 and the quantum computing control unit 110-2, the state sharing unit 111 is represented as "state sharing unit 111-1" and "state sharing unit 111-2", the twirling operation unit 112 is represented as "twirling operation unit 112-1" and "twirling operation unit 112-2", the error rate estimation unit 113 is represented as "error rate estimation unit 113-1" and "error rate estimation unit 113-2", the quantum circuit execution unit 114 is represented as "quantum circuit execution unit 114-1" and "quantum circuit execution unit 114-2", and the error elimination unit 115 is represented as "error elimination unit 115-1" and "error elimination unit 115-2".

<Quantum computing processing>
Hereinafter, examples 1 and 2 of the quantum computing process according to this embodiment will be described.

Example 1
The quantum computing process in the first embodiment will be described with reference to FIG.

First, the state sharing unit 111-1 of the quantum computing control unit 110-1 and the state sharing unit 111-2 of the quantum computing control unit 110-2 share the two-qubit state between the quantum processor 200-1 and the quantum processor 200-2 by a known method (step S101). Here, this two-qubit state may be any state as long as the fidelity with the following error-free Bell state is 0.5 or more. However, 0.5 is just an example and is not limited to this.

Next, the twirling operation unit 112-1 of the quantum computing control unit 110-1 and the twirling operation unit 112-2 of the quantum computing control unit 110-2 perform an operation called twirling (Reference 1) in which four types of local gates are randomly applied to the state shared in the above step S101, to create a state called a Bell diagonalized state (step S102). As a result, the Bell diagonalized state is shared between the quantum processor 200-1 and the quantum processor 200-2.

Here, the above four _types of gate operations are identity operation (no gate), _BxBx , _ByBy , and _BzBz . Furthermore, for i=x, y, _z , _{B i} _is as follows:

The above B _i represents an operation of simultaneously performing a π/2 rotation operation R _i (π/2) around a local iε{x, y, z} axis on the state of quantum processor 200-1 and the state of quantum processor 200-2. Note that the following means that an A gate is applied to the state (qubit) of quantum processor 200-1, and a B gate is applied to the state (qubit) of quantum processor 200-2.

Hereinafter, in the text of this specification, the above formula 3 will be expressed as "A(x)B".

Note that during the above Twirl operation, classical communication is carried out between the Twirl operation unit 112-1 and the Twirl operation unit 112-2. This is because the type of gate operation selected by one Twirl operation unit 112 needs to be transmitted to the other Twirl operation unit 112.

The density matrix of the state after the twirling operation in step S102 above is as follows:

The state represented by the above density matrix is called the Bell diagonalized state (Reference 1), where |φ _x 〉, |φ _y 〉, and |φ _z 〉 are as follows,

Here, ε _x , ε _y , and ε _z are error rates corresponding to the respective states, and ε=ε _x +ε _y +ε _z represents the error rate from an ideal Bell state.

Next, the error rate estimation unit 113-1 of the quantum computing control unit 110-1 and the error rate estimation unit 113-2 of the quantum computing control unit 110-2 estimate the error rate of the Bell diagonalized state (step S103). The error rate estimation unit 113 may obtain the error rate by normal tomography, but may also estimate the error rate by, for example, steps 11 to 15, 21 to 25, and 31 to 35 below.

Step 11: The error rate estimation unit 113-1 prepares the state |0> in the quantum processor 200-1, and similarly the error rate estimation unit 113-2 prepares the state |0> in the quantum processor 200-2.

Step 12: The error rate estimation units 113-1 and 113-2 apply a CNOT gate n times in succession to the Bell diagonalization state shared in step S102 above using the LOCC operation. Here, n is a multiple of 2.

Step 13: The error rate estimation unit 113-1 measures the state of the quantum processor 200-1 in the |0> and |1> bases (Z measurement), and similarly the error rate estimation unit 113-2 measures the state of the quantum processor 200-2 in the |0> and |1> bases (Z measurement).

Step 14: The error rate estimation units 113-1 and 113-2 repeat steps 11 to 13 above to obtain the expected value of the state of quantum processor 200-1 and the expected value of the state of quantum processor 200-2, respectively. This expected value f(n, ε) is theoretically expressed by the following formula.

The number of times steps 11 to 13 are repeated may be determined according to the desired accuracy.

Step 15: The error rate estimation units 113-1 and 113-2 execute the above steps 11 to 14 for different values of n, and fit the resulting expected values to the theoretical formula shown in Equation 6 above to find ε _x +ε _y .

Step 21: The error rate estimation unit 113-1 prepares the state |+> in the quantum processor 200-1, and similarly, the error rate estimation unit 113-2 prepares the state |+> in the quantum processor 200-2.

Step 22: The error rate estimation units 113-1 and 113-2 apply a CNOT gate n times in succession to the Bell diagonalization state shared in step S102 above using the LOCC operation. Here, n is a multiple of 2.

Step 23: The error rate estimation unit 113-1 measures the state of the quantum processor 200-1 in the |+> and |-> basis (X measurement), and similarly the error rate estimation unit 113-2 measures the state of the quantum processor 200-2 in the |+> and |-> basis (X measurement).

Step 24: The error rate estimation units 113-1 and 113-2 repeat steps 21 to 23 above to obtain the expected value of the state of quantum processor 200-1 and the expected value of the state of quantum processor 200-2, respectively. This expected value f(n, ε) is theoretically expressed by the following formula.

The number of times steps 21 to 23 are repeated may be determined according to the desired accuracy.

Step 25: The error rate estimation units 113-1 and 113-2 execute the above steps 21 to 24 for different values of n, and fit the resulting expected values to the theoretical formula shown in Equation 7 above to find ε _y +ε _z .

Step 31: The error rate estimation unit 113-1 prepares the state |0> in the quantum processor 200-1, while the error rate estimation unit 113-2 prepares the state |+> in the quantum processor 200-2.

Step 32: The error rate estimation units 113-1 and 113-2 apply a CNOT gate n times in succession to the Bell diagonalization state shared in step S102 above using the LOCC operation. Here, n is a multiple of 2.

Step 33: The error rate estimation unit 113-1 measures the state of the quantum processor 200-1 in the |0> and |1> basis (Z measurement), while the error rate estimation unit 113-2 measures the state of the quantum processor 200-2 in the |+> and |-> basis (X measurement).

Step 34: The error rate estimation units 113-1 and 113-2 repeat steps 31 to 33 above to obtain the expected value of the state of quantum processor 200-1 and the expected value of the state of quantum processor 200-2, respectively. This expected value f(n, ε) is theoretically expressed by the following formula.

The number of times steps 31 to 33 are repeated may be determined according to the desired accuracy.

Step 35: The error rate estimation units 113-1 and 113-2 execute the above steps 31 to 34 for different n, and find ε z + ε x by fitting the expected values obtained as a result, ε _x + ε _y obtained in the above steps 11 to 15, and ε _y + ε _z obtained in the above steps ₂₁ to ₂₅ to the theoretical formula shown in the above equation 8.

Next, the quantum circuit execution unit 114-1 of the quantum computing control unit 110-1 and the quantum circuit execution unit 114-2 of the quantum computing control unit 110-2 execute a quantum circuit including a nonlocal CNOT gate (step S104). At this time, the quantum circuit execution unit 114-1 and the quantum circuit execution unit 114-2 execute the nonlocal CNOT gate by performing a LOCC operation on the Bell diagonalized state. Note that errors may exist in the nonlocal CNOT gate.

Then, the error elimination unit 115-1 of the quantum computing control unit 110-1 and the error elimination unit 115-2 of the quantum computing control unit 110-2 retroactively eliminate (reduce) the errors in the nonlocal CNOT gate executed in step S104 above based on the error rate estimated in step S103 above (step S105). The error elimination unit 115 reduces the errors using, for example, a probabilistic error elimination method (Reference 2). When using the probabilistic error elimination method, the error elimination unit 115 may reduce the errors using the following steps 41 to 43.

Step 41: Error elimination units 115-1 and 115-2 insert an I(x)I gate with probability p _II /γ, an I(x)X gate with probability |p _IX |/γ, a Z(x)X gate with probability |p _ZX |, and a Z(x)I gate with probability |p _ZI |/γ after the nonlocal CNOT gate in the quantum circuit, where p _II , p _IX , p _ZX , p _ZI , and γ are as follows, respectively.

Also, I represents an identity operation (an operation that does nothing).

When inserting a gate (operation) in step 41 above, classical communication is performed between error removal unit 115-1 and error removal unit 115-2. This is because one error removal unit 115 needs to transmit the type of gate operation selected to the other error removal unit 115.

Step 42: Error elimination units 115-1 and 115-2 multiply the measurement results of the quantum circuit by γ for the number of times an I(x)I gate was inserted, by p _IX γ/|p _IX | for the number of times an I(x)X gate was inserted, by p _ZX γ/|p _ZX | for the number of times a Z(x)X gate was inserted, and by p _ZI γ/|p _ZI | for the number of times a Z(x)I gate was inserted.

Step 43: Error elimination units 115-1 and 115-2 repeat steps 41 and 42 above to find the weighted expectation of the quantum circuit. This weighted expectation is the expectation of the quantum circuit with reduced errors in the nonlocal CNOT gate.

The number of times steps 41 and 42 are repeated may be determined according to the desired accuracy. When calculating the weighted expected value, classical communication is performed between error elimination units 115-1 and 115-2. This is to obtain the weights of the expected values calculated by error elimination units 115-1 and 115-2.

Example 2
The quantum computing process in the second embodiment will be described with reference to FIG.

First, the state sharing unit 111-1 of the quantum computing control unit 110-1 and the state sharing unit 111-2 of the quantum computing control unit 110-2 share the two-qubit state between the quantum processor 200-1 and the quantum processor 200-2 by a known method (step S201). Here, as in step S101 of FIG. 5, this two-qubit state may be any state as long as the fidelity with respect to the error-free Bell state shown in the above equation 1 is 0.5 or more. However, 0.5 is just an example and is not limited to this.

Next, twirling operation unit 112-1 of quantum computing control unit 110-1 and twirling operation unit 112-2 of quantum computing control unit 110-2 perform an operation called twirling (Reference 1) in which 12 types of local gates are randomly applied to the state shared in step S202 above, creating a state called a Werner state (step S202). As a result, the Werner state is shared between quantum processor 200-1 and quantum processor 200-2.

Here, the above 12 types of gate operations are identity operation (no gate), _BxBx , _ByBy , _BzBz, _BxBy _, _ByBz _, _BzBx _, _ByBx _, _BxByBx _, _ByBzByBz _, _BzBxBzBx _, _ByBxByBx _, _and _ByBxByBx for i ₌ x, _y _, _z _. _Bi is _as shown _in the above _formula ₂ .

The density matrix of the state after the twirling operation in step S202 above is as follows:

The state represented by the above density matrix is called the Werner state, where ε is the error rate.

Next, the error rate estimation unit 113-1 of the quantum computing control unit 110-1 and the error rate estimation unit 113-2 of the quantum computing control unit 110-2 estimate the error rate of the Werner state (step S203). The error rate estimation unit 113 may obtain the error rate by normal tomography, but may also estimate the error rate by, for example, steps 51 to 55 below.

Step 51: The error rate estimation unit 113-1 prepares the state |+> in the quantum processor 200-1, and similarly the error rate estimation unit 113-2 prepares the state |+> in the quantum processor 200-2.

Step 52: The error rate estimation units 113-1 and 113-2 apply a CNOT gate n times in succession to the Werner state shared in step S202 above using the LOCC operation. Here, n is a multiple of 2.

Step 53: The error rate estimation unit 113-1 measures the state of the quantum processor 200-1 in the |+> and |-> basis (X measurement), and similarly the error rate estimation unit 113-2 measures the state of the quantum processor 200-2 in the |+> and |-> basis (X measurement).

Step 54: The error rate estimation units 113-1 and 113-2 repeat steps 51 to 53 above to obtain the expected value of the state of quantum processor 200-1 and the expected value of the state of quantum processor 200-2, respectively. This expected value f(n, ε) is theoretically expressed by the following formula.

The number of times steps 51 to 53 are repeated may be determined according to the desired accuracy.

Step 55: The error rate estimation unit 113-1 and the error rate estimation unit 113-2 execute steps 51 to 54 for different values of n, and calculate the error rate ε by fitting each expected value obtained as a result to the theoretical formula shown in equation 11 above.

Next, the quantum circuit execution unit 114-1 of the quantum computing control unit 110-1 and the quantum circuit execution unit 114-2 of the quantum computing control unit 110-2 execute a quantum circuit including a nonlocal CNOT gate (step S204). At this time, the quantum circuit execution unit 114-1 and the quantum circuit execution unit 114-2 execute the nonlocal CNOT gate by performing a LOCC operation on the Werner state. Note that errors may exist in the nonlocal CNOT gate.

Then, the error elimination unit 115-1 of the quantum computing control unit 110-1 and the error elimination unit 115-2 of the quantum computing control unit 110-2 retroactively eliminate (reduce) the errors in the nonlocal CNOT gate executed in step S204 above based on the error rate ε estimated in step S203 above (step S205). The error elimination unit 115 reduces the errors using, for example, a probabilistic error elimination method (Reference 2). When using the probabilistic error elimination method, the error elimination unit 115 may reduce the errors using the following steps 61 to 63.

Step 61: Error elimination units 115-1 and 115-2 apply the identity operation with probability (3-ε)/(3+2ε) and the I(x)X, Z(x)X, and Z(x)I gates with probability ε/(3+2ε) after the nonlocal CNOT gate in the quantum circuit.

When inserting a gate (operation) in step 61 above, classical communication is performed between error removal unit 115-1 and error removal unit 115-2. This is because one error removal unit 115 needs to transmit the type of gate operation selected to the other error removal unit 115.

Step 62: Error elimination units 115-1 and 115-2 multiply the measurement results of the quantum circuit by γ for the number of times an identity operation was performed, and by -γ for the number of times an I(x)X, Z(x)X, or Z(x)I gate was inserted.

Step 63: Error elimination units 115-1 and 115-2 repeat steps 61 and 62 above to find the weighted expectation of the quantum circuit. This weighted expectation is the expectation of the quantum circuit with reduced errors in the nonlocal CNOT gate.

The number of times steps 61 and 62 are repeated may be determined according to the desired accuracy. When calculating the weighted expected value, classical communication is performed between error elimination units 115-1 and 115-2. This is to obtain the weights of the expected values calculated by error elimination units 115-1 and 115-2.

<Summary>
As described above, the quantum computing system 1 according to the present embodiment shares a Bell state in which an error may exist among a plurality of quantum computing devices 10, and reduces the error of the nonlocal CNOT gate derived from the error of the Bell state by an error suppression method (e.g., a probabilistic error elimination method, etc.) after the fact. In addition, in order to use an error suppression method such as a probabilistic error elimination method, the error rate of the Bell state is obtained by a method such as tomography. This makes it possible to execute a desired quantum circuit including a nonlocal CNOT gate.

Compared to the method described in Non-Patent Document 2, the quantum computing system 1 according to this embodiment makes it possible to reduce the number of times the quantum circuit is executed to obtain an expected value with sufficient accuracy, and since distillation is not required, it is also possible to reduce the cost required for distillation of erroneous Bell states. Therefore, for example, in cases where one does not want to consume a large number of Bell states and does not want to perform entanglement distillation, which takes time to execute, but executing a CNOT gate with local operations requires a large number of executions of the quantum circuit, by using the quantum computing system 1 according to this embodiment, it is possible to execute a non-local CNOT gate with a small number of executions of the quantum circuit while reducing the cost of entanglement distillation.

The present invention is not limited to the specifically disclosed embodiments above, and various modifications, changes, and combinations with known technologies are possible without departing from the scope of the claims.

[References]
Reference 1: C. H. Bennett, DP DiVincenzo, J. A. Smolin, and W. K. Wootters, "Mixed-state entanglement and quantum error correction", Physical Review A 54, 3824 (1996).
Reference 2: S. Endo, S. C. Benjamin, and Y. Li, "Practical Quantum Error Mitigation for Near-Future Applications", Physical Review X 8, 031027 (2018).

REFERENCE SIGNS LIST 1 Quantum computing system 10 Quantum computing device 100 Control device 101 Input device 102 Display device 103 External I/F
103a Recording medium 104 Communication I/F
105 RAM
106 ROM
107 Auxiliary storage device 108 Processor 109 Bus 110 Quantum computation control unit 111 State sharing unit 112 Twirl operation unit 113 Error rate estimation unit 114 Quantum circuit execution unit 115 Error removal unit 120 Storage unit 200 Quantum processor

Claims

A quantum computing system including a plurality of quantum computing devices,
The quantum computing device includes:
A sharing unit that shares a two-qubit state with another quantum computing device, the two-qubit state having a fidelity to the error Bell state of a predetermined value or more;
A twirling operation unit that performs a twirling operation on the two-qubit state to make it a predetermined state;
an error rate estimation unit that estimates an error rate in the predetermined state;
a quantum circuit execution unit that executes a quantum circuit including a nonlocal CNOT gate realized by a LOCC operation on the predetermined state;
an error removal unit that removes errors in the non-local CNOT gate based on the error rate;
A quantum computing system having
The error elimination unit is
The quantum computing system of claim 1 , wherein the error of the nonlocal CNOT gate is eliminated by a probabilistic error elimination method using the error rate.
The quantum computing system of claim 1 or 2, wherein the predetermined state is a Bell diagonalized state or a Werner state.
The error rate estimation unit
4. The quantum computing system according to claim 3, wherein the error rate is estimated by tomography of the Bell diagonalized state or the Werner state, or by fitting an expectation value obtained by measuring the Bell diagonalized state or the Werner state to a theoretical formula.
A quantum computing device connected to other quantum computing devices via a communication network,
a sharing unit that shares a two-qubit state with the other quantum computing device, the two-qubit state having a fidelity to an error-free Bell state of a predetermined value or more;
A twirling operation unit that performs a twirling operation on the two-qubit state to make it a predetermined state;
an error rate estimation unit that estimates an error rate in the predetermined state;
a quantum circuit execution unit that executes a quantum circuit including a nonlocal CNOT gate realized by a LOCC operation on the predetermined state;
an error removal unit that removes errors in the non-local CNOT gate based on the error rate;
A quantum computing device having
A quantum computing method used in a quantum computing system including a plurality of quantum computing devices, comprising:
The quantum computing device comprises:
A sharing procedure for sharing a two-qubit state with another quantum computing device, the two-qubit state having a fidelity to the error-free Bell state of a predetermined value or more;
A twirling operation procedure for performing a twirling operation on the two-qubit state to make it a predetermined state;
an error rate estimation step of estimating an error rate of the predetermined state;
a quantum circuit execution procedure for executing a quantum circuit including a nonlocal CNOT gate realized by a LOCC operation on the predetermined state;
an error removal procedure for removing errors in the non-local CNOT gate based on the error rate;
A quantum computing method for performing
A quantum computing device that is connected to other quantum computing devices via a communication network,
a sharing procedure for sharing a two-qubit state having a fidelity to an error-free Bell state of a predetermined value or more with the other quantum computing device;
A twirling operation procedure for performing a twirling operation on the two-qubit state to make it a predetermined state;
an error rate estimation step of estimating an error rate of the predetermined state;
a quantum circuit execution procedure for executing a quantum circuit including a nonlocal CNOT gate realized by a LOCC operation on the predetermined state;
an error removal procedure for removing errors in the non-local CNOT gate based on the error rate;
A program that executes the following.