WO2024180432A1

WO2024180432A1 - Semiconductor device and method for producing semiconductor device

Info

Publication number: WO2024180432A1
Application number: PCT/IB2024/051695
Authority: WO
Inventors: 山崎舜平; 村川努; 國武寛司; 手塚祐朗; 松嵜隆徳; 岡本佑樹; 宮田翔希
Original assignee: 株式会社半導体エネルギー研究所
Priority date: 2023-03-01
Filing date: 2024-02-22
Publication date: 2024-09-06

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device has a memory device, a sense amplifier, and a processing unit. The sense amplifier and the processing unit are disposed on a first layer, and the memory device is disposed on a second layer stacked on the first layer. The memory device has a first transistor, a second transistor, and a capacitor, and the second transistor and the capacitor are each provided overlapping on the first transistor. The first and second transistors are provided with source electrodes and drain electrodes overlapping at different heights with respect to the substrate surface. The gate electrode of the first transistor functions as one of the source electrode or drain electrode of the second transistor and also functions as one electrode of the capacitor. A dielectric layer of the capacitor is provided on the gate electrode of the first transistor. The other electrode of the capacitor is provided on the dielectric layer of the capacitor, with a gap between the electrode and the gate electrode of the second transistor.

Description

Semiconductor device and method for manufacturing the same

One aspect of the present invention relates to a semiconductor device. Another aspect of the present invention relates to a memory device and a method for manufacturing the memory device. Another aspect of the present invention relates to a transistor and a method for manufacturing the transistor. Another aspect of the present invention relates to a capacitor and a method for manufacturing the capacitor. Another aspect of the present invention relates to an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), electronic devices having them, driving methods thereof, or manufacturing methods thereof.

In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

In recent years, the development of semiconductor devices has progressed, and large scale integrated circuits (LSIs) are now used in semiconductor devices. For example, central processing units (CPUs) and memories are used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

Semiconductor circuits (IC chips) such as CPUs and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

In addition, technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

It is also known that transistors using oxide semiconductors have extremely small leakage currents in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.

In addition, in recent years, with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.

Furthermore, if the transistors can be made vertical, it will be possible to increase the density of integrated circuits. For example, Patent Document 4 discloses a vertical transistor in which the side of the oxide semiconductor is covered by a gate electrode via a gate insulating layer.

JP 2012-257187 A JP 2011-151383 A International Publication No. 2021/053473 JP 2013-211537 A

One aspect of the present invention has an object to provide a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Another aspect of the present invention has an object to provide a highly reliable semiconductor device, memory device, or transistor. Another aspect of the present invention has an object to provide a transistor with a large on-state current. Another aspect of the present invention has an object to provide a transistor, memory device, or semiconductor device with favorable electrical characteristics. Another aspect of the present invention has an object to provide a low-cost semiconductor device or memory device. Another aspect of the present invention has an object to provide a semiconductor device or memory device with low power consumption. Another aspect of the present invention has an object to provide a semiconductor device or memory device with high operating speed. Another aspect of the present invention has an object to provide a novel semiconductor device, memory device, or transistor.

An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device, memory device, or transistor. An object of one embodiment of the present invention is to provide a method for manufacturing a transistor with high on-state current. An object of one embodiment of the present invention is to provide a method for manufacturing a transistor, memory device, or semiconductor device with favorable electrical characteristics. An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with high yield. An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with low power consumption. An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or memory device with high operating speed. An object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device, memory device, or transistor.

Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

One aspect of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer, the second transistor and the capacitor being provided overlapping the first transistor, the source electrode and the drain electrode of each of the first transistor being located at different heights relative to the substrate surface, the first insulating layer being provided between the source electrode and the drain electrode of the first transistor and having a first opening that reaches one of the source electrode or the drain electrode of the first transistor, and the other of the source electrode or the drain electrode of the first transistor being provided on the first insulating layer. the semiconductor layer of the first transistor has a region in contact with one upper surface of the source electrode or drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, the other side surface of the source electrode or drain electrode of the first transistor in the first opening, and the other upper surface of the source electrode or drain electrode of the first transistor; the gate insulating layer of the first transistor is provided in contact with the semiconductor layer of the first transistor; and the gate electrode of the first transistor is provided on the gate insulating layer of the first transistor so as to have a region overlapping with the semiconductor layer of the first transistor. a second insulating layer is provided between the source electrode and drain electrode of the second transistor and has a second opening reaching the gate electrode of the first transistor, the other of the source electrode or drain electrode of the second transistor is provided on the second insulating layer, and the semiconductor layer of the second transistor is provided on a top surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, and the other of the source electrode or drain electrode of the second transistor in the second opening. and a region in contact with the top surface of the other of the source electrode or drain electrode of the second transistor, the gate insulating layer of the second transistor is provided in contact with the semiconductor layer of the second transistor, the gate electrode of the second transistor is provided on the gate insulating layer of the second transistor so as to have a region overlapping with the semiconductor layer of the second transistor, the dielectric layer of the capacitance is provided on the gate electrode of the first transistor, the other electrode of the capacitance has a region overlapping with the gate electrode of the first transistor, and is provided on the dielectric layer of the capacitance with a gap between it and the second opening in a plan view.

In the above, it is preferable that at least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is a transistor having a metal oxide.

Furthermore, in the above, it is preferable that the side surface of the semiconductor layer of the first transistor and the other side surface of the source electrode or drain electrode of the first transistor have a region that is approximately flush with each other, and that the side surface of the semiconductor layer of the second transistor and the other side surface of the source electrode or drain electrode of the second transistor have a region that is approximately flush with each other.

In the above, it is also preferable that the end of the other electrode of the capacitor that does not face the first opening is positioned outside the end of the gate electrode of the first transistor.

Furthermore, in the above, it is preferable that the other electrode of the capacitor is provided in two places, on a first side end of the gate electrode of the first transistor and on a second side end opposite the first side end.

In the above, it is also preferable that the other electrode of the capacitor has a region that overlaps with the upper surface of the gate electrode of the first transistor so as to surround the second opening.

In the above, the dielectric layer of the capacitor preferably comprises any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, and a nitride having silicon and hafnium.

In the above, the dielectric layer of the capacitor preferably contains any of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium tantalate bismuthate, bismuth ferrite, and barium titanate.

In the above, it is preferable that the first insulating layer and the second insulating layer have any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate, and acrylic.

Another aspect of the present invention is to form a first conductive layer, form a first insulating layer and a first conductive film on the first conductive layer, process the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, form a first opening in the first conductive film and the first insulating layer to reach the first conductive layer, process the second conductive layer to form a third conductive layer, and form an upper surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, and a side surface of the third conductive layer in the first opening. a first metal oxide film is formed in contact with the upper surface of the semiconductor layer and a third conductive layer, the first metal oxide film is processed to form a first semiconductor layer having a region overlapping with the first opening, a second insulating layer is formed in contact with the upper surface of the first semiconductor layer, a second conductive film is formed on the second insulating layer, the second conductive film is processed to form a fourth conductive layer having a region overlapping with the first semiconductor layer, a third insulating layer is formed on the fourth conductive layer and on the second insulating layer, and the third conductive film is formed on the third insulating layer. forming a sixth conductive layer from the fourth conductive layer by forming a sixth conductive layer on the fourth insulating layer and the fourth insulating layer; forming a second opening in the fourth conductive layer and the fourth insulating layer, the sixth conductive layer being processed to form a seventh conductive layer; forming a seventh conductive layer on the fourth conductive layer and the fourth insulating layer; forming a seventh conductive layer on the fourth conductive layer and the fourth insulating layer; forming a seventh conductive layer on the fourth conductive layer and the fourth insulating layer; forming a seventh conductive layer on the fourth conductive layer and the fourth insulating layer; forming a seventh conductive layer on the fourth conductive layer and the fourth insulating layer; forming a seventh conductive layer on the fourth conductive layer and the seventh conductive layer in the seventh opening; This is a method for manufacturing a semiconductor device, which includes forming a second metal oxide film in contact with the side of the third insulating layer, the side of the seventh conductive layer in the second opening, and the top surface of the seventh conductive layer, processing the second metal oxide film to form a second semiconductor layer so as to have an area overlapping with the second opening, forming a fifth insulating layer in contact with the top surface of the second semiconductor layer, forming a fifth conductive film on the fifth insulating layer, and processing the fifth conductive film to form an eighth conductive layer so as to have an area overlapping with the second semiconductor layer.

Another aspect of the present invention is to form a first conductive layer, form a first insulating layer and a first conductive film on the first conductive layer, process the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, form a first opening in the first conductive film and the first insulating layer, reaching the first conductive layer, form a first metal oxide film in contact with an upper surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and an upper surface of the second conductive layer, and form a first metal oxide film. a second insulating layer is formed on the upper surface of the first semiconductor layer; a second conductive layer is formed on the upper surface of the first semiconductor layer; a second conductive layer is formed on the second insulating layer; a fourth conductive layer is formed on the upper surface of the first semiconductor layer; a third insulating layer is formed on the fourth conductive layer and on the second insulating layer; a third conductive layer is formed on the third insulating layer; a fourth insulating layer and a fourth conductive film are formed on the fifth conductive layer and the third insulating layer, the fourth insulating layer and the fourth conductive film are processed to form a sixth conductive layer from the fourth conductive film, a second opening is formed in the fourth conductive film and the fourth insulating layer, the second opening reaches the fourth conductive layer, and a top surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth insulating layer in the second opening, and a sixth conductive layer in the second opening are processed. This is a method for manufacturing a semiconductor device, which includes forming a second metal oxide film in contact with the side surface of the insulating layer and the top surface of the sixth conductive layer, processing the second metal oxide film to form a second semiconductor layer so as to have an area overlapping with the second opening, processing the sixth conductive layer to form a seventh conductive layer so as to have an area overlapping with the second semiconductor layer, forming a fifth insulating layer in contact with the top surface of the second semiconductor layer, forming a fifth conductive layer on the fifth insulating layer, and processing the fifth conductive layer to form an eighth conductive layer so as to have an area overlapping with the second semiconductor layer.

Furthermore, one aspect of the present invention has a memory unit and a processing unit, the memory unit has a memory device and a sense amplifier, the processing unit has a CPU, MPU, or GPU, the sense amplifier and the processing unit are arranged on a first layer, the memory device is arranged on a second layer, the memory device has a first transistor, a second transistor, a capacitance, a first insulating layer, and a second insulating layer, the second layer is stacked on the first layer, the second transistor and the capacitance are each superimposed on the first transistor, the source electrode and the drain electrode of each of the first transistor and the second transistor are located at different heights with respect to the substrate surface, and the first insulating layer is a source electrode of the first transistor and a drain electrode of the second transistor. a first insulating layer provided between the source electrode and the drain electrode of the first transistor and having a first opening reaching one of the source electrode or the drain electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor being provided on the first insulating layer, the semiconductor layer of the first transistor having a region in contact with an upper surface of one of the source electrode or the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the other of the source electrode or the drain electrode of the first transistor in the first opening, and an upper surface of the other of the source electrode or the drain electrode of the first transistor, the gate insulating layer of the first transistor being provided on and in contact with the semiconductor layer of the first transistor, The gate electrode of the first transistor is provided on the gate insulating layer of the first transistor so as to have a region overlapping with the semiconductor layer of the first transistor, and also functions as one of a source electrode or a drain electrode of the second transistor and as one electrode of a capacitance. The second insulating layer is provided between the source electrode and the drain electrode of the second transistor and has a second opening reaching the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the second transistor is provided on the second insulating layer. The semiconductor layer of the second transistor is provided on an upper surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, and a second opening. The semiconductor device has a region in contact with the other side of the source electrode or drain electrode of the second transistor and the other top surface of the source electrode or drain electrode of the second transistor, the gate insulating layer of the second transistor is provided in contact with the semiconductor layer of the second transistor, the gate electrode of the second transistor is provided on the gate insulating layer of the second transistor so as to have a region overlapping with the semiconductor layer of the second transistor, the dielectric layer of the capacitance is provided on the gate electrode of the first transistor, the other electrode of the capacitance has a region overlapping with the gate electrode of the first transistor, and is provided on the dielectric layer of the capacitance with a gap between it and the second opening in a plan view.

In the above, it is preferable that the dielectric layer of the capacitor contains any one of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium tantalate bismuthate, bismuth ferrite, or barium titanate.

According to one embodiment of the present invention, a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device, memory device, or transistor can be provided. Alternatively, according to one embodiment of the present invention, a transistor with a large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor, memory device, or semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a low-cost semiconductor device or memory device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or memory device with high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device, memory device, or transistor can be provided.

Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a highly reliable semiconductor device, memory device, or transistor. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a transistor with high on-state current. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a transistor, memory device, or semiconductor device with favorable electrical characteristics. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a semiconductor device or memory device with high yield. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a semiconductor device or memory device with low power consumption. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a semiconductor device or memory device with high operating speed. Alternatively, according to one embodiment of the present invention, it is possible to provide a method for manufacturing a novel semiconductor device, memory device, or transistor.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

Fig. 1A is a block diagram for explaining an example of the configuration of a computer, and Fig. 1B and Fig. 1C are schematic diagrams for explaining an example of the configuration of a computer.
FIG. 2 is a schematic diagram illustrating an example of the configuration of a computer.
FIG. 3 is a circuit diagram illustrating an example of the configuration of a semiconductor device.
4A to 4D are circuit diagrams illustrating examples of the configuration of a semiconductor device.
Fig. 5A is a plan view showing an example of the configuration of a storage device, and Figs. 5B and 5C are cross-sectional views showing an example of the configuration of a storage device.
FIG. 6 is a cross-sectional view showing an example of the configuration of a storage device.
7A and 7B are cross-sectional and plan views illustrating an example of the configuration of a transistor.
Fig. 8A is a plan view showing an example of the configuration of a storage device, and Figs. 8B and 8C are cross-sectional views showing an example of the configuration of a storage device.
9A is a plan view showing a configuration example of a storage device, and FIGS. 9B and 9C are cross-sectional views showing the configuration example of a storage device.
Fig. 10A is a plan view showing a configuration example of a storage device, and Figs. 10B and 10C are cross-sectional views showing the configuration example of a storage device.
FIG. 11 is a circuit diagram illustrating an example of the configuration of a semiconductor device.
FIG. 12 is a timing chart illustrating an example of the operation of the semiconductor device.
FIG. 13 is a block diagram illustrating an example of the configuration of a storage device.
14A and 14B are circuit diagrams illustrating an example of the configuration of a memory device.
FIG. 15 is a schematic diagram illustrating an example of the configuration of a storage device.
FIG. 16 is a circuit diagram illustrating a configuration example of a semiconductor device.
FIG. 17 is a timing chart illustrating an example of the operation of the semiconductor device.
18A to 18D are schematic diagrams illustrating an example of the operation of the semiconductor device.
FIG. 19 is a timing chart illustrating an example of the operation of the semiconductor device.
20A to 20G are schematic diagrams illustrating an example of the operation of the semiconductor device.
FIG. 21 is a block diagram illustrating the CPU.
22A and 22B are perspective views of a semiconductor device.
23A and 23B are perspective views of a semiconductor device.
24A and 24B are diagrams showing various storage devices by hierarchical level.
25A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 26 is a cross-sectional view showing an example of a method for manufacturing a memory device.
27A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 28 is a cross-sectional view showing an example of a method for manufacturing a memory device.
29A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 30 is a cross-sectional view showing an example of a method for manufacturing a memory device.
31A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 31B and 31C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 32 is a cross-sectional view showing an example of a method for manufacturing a memory device.
33A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 33B and 33C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 34 is a cross-sectional view showing an example of a method for manufacturing a memory device.
35A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 35B and 35C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 36 is a cross-sectional view showing an example of a method for manufacturing a memory device.
37A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 37B and 37C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 38 is a cross-sectional view showing an example of a method for manufacturing a memory device.
39A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 39B and 39C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 40 is a cross-sectional view showing an example of a method for manufacturing a memory device.
41A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 41B and 41C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 42 is a cross-sectional view showing an example of a method for manufacturing a memory device.
43A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 43B and 43C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 44 is a cross-sectional view showing an example of a method for manufacturing a memory device.
45A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 45B and 45C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 46 is a cross-sectional view showing an example of a method for manufacturing a memory device.
47A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 47B and 47C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 48 is a cross-sectional view showing an example of a method for manufacturing a memory device.
49A is a plan view illustrating an example of a method for manufacturing a memory device, and FIGS. 49B and 49C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
FIG. 50 is a cross-sectional view showing an example of a method for manufacturing a memory device.
FIG. 51 is a cross-sectional view showing a configuration example of a memory device.
52A and 52B are diagrams showing an example of an electronic component.
53A and 53B are diagrams showing an example of an electronic device, and Fig. 53C to Fig. 53E are diagrams showing an example of a mainframe computer.
FIG. 54 is a diagram showing an example of space equipment.
FIG. 55 is a diagram illustrating an example of a storage system applicable to a data center.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in the actual manufacturing process, layers or resist masks, etc. may be unintentionally reduced by processes such as etching, but this may not be reflected in the drawings for ease of understanding.

In addition, in this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). Furthermore, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

In addition, in this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

In addition, the functions of "source" and "drain" may be interchangeable when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" can be used interchangeably.

Note that the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When an impurity is contained, for example, the density of defect states in the semiconductor may be increased or the crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. In addition, for example, oxygen vacancies (also referred to as V _O ) may be formed in the oxide semiconductor due to the inclusion of an impurity.

In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. An oxynitride refers to a material whose composition contains more nitrogen than oxygen.

To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in the film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. When the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more), XPS is suitable. On the other hand, when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less), SIMS is suitable. When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film", and the term "conductive film" may be changed to the term "conductive layer". Also, for example, the term "insulating film" may be changed to the term "insulating layer", and the term "insulating layer" may be changed to the term "insulating film". Furthermore, for example, the term "semiconductor film" may be changed to the term "semiconductor layer", and the term "semiconductor layer" may be changed to the term "semiconductor film".

In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In addition, in this specification, "connection" includes "electrical connection."

"A and B are electrically connected" means that, among A and B connected without an insulator (A and B connected via a conductor or semiconductor, or A and B in contact), there is a time when an electrical signal is exchanged or a potential interaction occurs between A and B during circuit operation. In other words, even if there is a time when an electrical signal is not exchanged or a potential interaction does not occur between A and B during circuit operation, if there is a time when an electrical signal is exchanged or a potential interaction occurs between A and B, it can be said that "A and B are electrically connected."

"Electrical connection" includes a connection that does not involve a circuit element (e.g., a transistor, but excluding wiring) (direct connection), and a connection that involves one or more circuit elements (indirect connection).

Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, and when A and B are connected via the source and drain of one or more transistors. However, this is subject to the premise that there is a timing when an electrical signal is exchanged or potential interaction occurs between A and B.

An example of a case where A and B are connected via an insulator and therefore it cannot be said that "A and B are electrically connected" is when there is a dielectric of a capacitive element, a gate insulating film of a transistor, etc. between A and B.

Examples of cases where A and B are connected without an insulator, but there is no timing when an electrical signal is sent or received between A and B or when potential interaction occurs between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power source, signal source, etc. (however, this does not include a case where potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, but there is no timing when both transistor TrP and transistor TrQ are on at the same time.

In addition, in this specification, the term "resistance element" may be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" may be rephrased as "resistance", "load", or "region having a resistance value". Conversely, the term "resistance", "load", or "region having a resistance value" may be rephrased as "resistance element". The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, it may be, for example, 1 Ω or more and 1×10 ⁹ Ω or less.

In addition, in this specification, a "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, the terms "capacitive element", "parasitic capacitance", and "gate capacitance" can sometimes be replaced with the term "capacitance". Conversely, the term "capacitance" can sometimes be replaced with the term "capacitive element", "parasitic capacitance", or "gate capacitance". In addition, a "capacitance" (including a "capacitance" with three or more terminals) is configured to include an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes", "pair of conductive regions", "pair of regions", or "pair of terminals". In addition, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input/output terminals of the transistor. One of the two input/output terminals becomes a source and the other becomes a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Also, when a transistor has three or more gates, in this specification, each gate may be referred to as a first gate, a second gate, a third gate, etc.

For example, in this specification, a transistor having a multi-gate structure with two or more gates can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the withstand voltage of the transistor (improve reliability). Alternatively, with the multi-gate structure, even if the voltage between the drain and source changes when operating in the saturation region, the current between the drain and source does not change much, and a voltage-current characteristic with a flat slope can be obtained. By using voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

　In addition, even when a single circuit element is shown on a circuit diagram, the circuit element may have multiple circuit elements. For example, when a single resistor is shown on a circuit diagram, this includes the case where two or more resistors are electrically connected in series. For example, when a single capacitor is shown on a circuit diagram, this includes the case where two or more capacitors are electrically connected in parallel. For example, when a single transistor is shown on a circuit diagram, this includes the case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, when a single switch is shown on a circuit diagram, this includes the case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

In addition, in this specification, a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit configuration and device structure. Also, a terminal, wiring, etc. can be referred to as a node.

In addition, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential, and if the reference potential is the ground potential, for example, "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0V. Potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, etc., and the potential output from circuits, etc. also change.

In addition, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, if two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, if two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

In addition, "current" refers to the phenomenon of charge transfer (electrical conduction), and for example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuums). Furthermore, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive/negative (or current direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Additionally, the statement "current is input to element A" can be rephrased as "current is output from element A."

In this specification and the like, unless otherwise specified, the off-state current refers to leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage _Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage _Vth (higher than _Vth for a p-channel transistor).

In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to having a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.

In this specification, when it is stated that A is in contact with B, at least a part of A is in contact with B. Therefore, for example, this can be rephrased as saying that A has an area in contact with B.

In this specification, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as saying that A has a region that is located on B.

In this specification, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.

In this specification, when it is stated that A overlaps with B, at least a portion of A overlaps with B. Therefore, for example, this can be rephrased as saying that A has an area that overlaps with B.

In addition, in this specification, terms indicating position such as "upper," "lower," "left," and "right" are used for convenience in explaining the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those explained in the specification, and can be rephrased appropriately depending on the situation.

In this specification and the like, metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS). For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a transistor is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

(Embodiment 1)
The semiconductor device according to one embodiment of the present invention can function as an electronic calculator (also referred to as a computer). At least a part of the electronic calculator according to one embodiment of the present invention can be used in, for example, a microcomputer, a personal computer, a workstation, a mainframe, a supercomputer, or the like.

In one embodiment of the semiconductor device of the present invention, among its components, a processing unit such as a CPU and a part of the memory unit (e.g., a sense amplifier) can be formed on the same layer (on the first layer). Therefore, the semiconductor device can be manufactured with fewer steps than when the processing unit and the memory unit are formed on separate layers. Furthermore, by forming the processing unit and a part of the memory unit on the same layer (on the first layer), the physical distance between them can be reduced, thereby reducing the influence of signal delays in the wiring between them. Therefore, the operating speed of the semiconductor device can be improved and power consumption can be reduced.

In addition, in a semiconductor device according to one embodiment of the present invention, a memory cell (sometimes referred to as a memory device) constituting a memory portion is provided on a layer (second layer) different from the first layer described above. Here, the second layer is a layer stacked on the first layer. In the semiconductor device according to one embodiment of the present invention, the memory cell can be formed of a fine transistor and a capacitor. The transistor and the capacitor constituting the memory cell are provided to overlap each other, and some of the respective components are formed to be shared with each other. Therefore, a fine semiconductor device with high integration can be realized. In addition, a low-cost semiconductor device can be realized with a small number of processes. Below, an electronic computer that can be applied to the semiconductor device according to one embodiment of the present invention will be described with reference to the drawings.

<Example of computer configuration>
FIG. 1A is a block diagram illustrating a configuration example of a computer 900 that can be used for a semiconductor device of one embodiment of the present invention.

As shown in FIG. 1A, the electronic computer 900 has a processing unit 910 (sometimes called a processor), a storage unit 920 (sometimes called a memory), and a control unit 930. The processing unit 910, the storage unit 920, and the control unit 930 are electrically connected to each other via a bus line 971.

Note that although not shown, the electronic calculator 900 may have, for example, an input/output unit (sometimes called an interface). The input/output unit has a function of exchanging data, etc. with functional devices (e.g., input devices, output devices, and storage devices) provided outside the electronic calculator 900.

The processing unit 910 has a function of executing a series of processes (tasks), for example, by sequentially executing processes according to a program. It also has a function of executing multiple tasks, for example. At least a part of the processing unit 910 can be used as, for example, a CPU, an MPU (Micro Processing Unit), and a GPU (Graphics Processing Unit).

The processing unit 910 has an arithmetic unit 911 (sometimes called a core), a control unit 912, and a register unit 913. The register unit 913 has one or more register units 914.

The register unit 914 has a scan flip-flop 915 and a backup memory 916. At least a portion of the register unit 914 can be used as, for example, a general-purpose register and a dedicated register (for example, a program counter (PC), an instruction register (IR), and a status register (SR)).

The calculation unit 911 may have, for example, an arithmetic logic unit (ALU) and a floating point unit (FPU).

The control unit 912 has a function of controlling the operation of the processing unit 910. For example, it has a function of controlling processing performed while switching between multiple tasks. It can also have, for example, an instruction decoder (ID: Instruction Decoder) and the like.

A specific example of the configuration of the register unit 914 will be described later.

The memory unit 920 has a function of storing, for example, programs and data. At least a portion of the memory unit 920 can be used as, for example, a main memory, a cache memory, etc.

The memory unit 920 has a memory array unit 921 and a control unit 922.

The memory array section 921 has one or more memory blocks 923. The memory block 923 has one or more memory units 924 and a sense amplifier 926. The memory unit 924 has one or more memory cells 925.

Here, the group of memory cells 925 enclosed by dotted lines in FIG. 1A is sometimes called a memory cell array.

The control unit 922 has a function of controlling the operation of the storage unit 920. For example, it has a function of controlling the writing and reading of data to and from the memory array unit 921.

Specific configuration examples of the memory block 923 and the storage unit 920 will be described later.

The control unit 930 has a function of controlling the operation of the electronic computer 900. It can also have, for example, a power management unit (PMU). The PMU has a function of controlling the operation of power gating, for example. For example, it has a function of controlling the supply of power to each component of the electronic computer 900 by putting a power switch (not shown) into a conductive or non-conductive state.

FIG. 1B is a schematic diagram illustrating an example of the layer structure of the electronic calculator 900.

As shown in FIG. 1B, the electronic calculator 900 has a layer 985 and a layer 982. The layer 982 has a layer 983 and a plurality of layers 984 (layers 984[1] to 984[K] (K is an integer of 2 or more)). Note that the electronic calculator 900 may have a configuration having a single layer 984.

Layer 983 is stacked on layer 985. Layers 984[1] to 984[K] are stacked on layer 983.

In the following description, the X, Y, and Z directions are defined to make it easier to understand the positional relationship between the components. The X, Y, and Z directions are perpendicular or approximately perpendicular to each other. Approximately perpendicular means that the angle between the two elements is between 85 degrees and 95 degrees. The Z direction is the direction in which layer 983 and layers 984[1] to 984[K] are stacked on top of layer 985. Therefore, the X and Y directions are the directions along the respective surfaces of layer 985, layer 983, and layers 984[1] to 984[K].

Layer 985 can be disposed on an insulating or semiconducting substrate including a variety of materials.

In one embodiment of the present invention, for example, layer 985 can be provided on a substrate containing silicon. That is, layer 985 can be provided with a Si transistor (a transistor containing silicon in the channel formation region). Thus, in one embodiment of the present invention, for example, a CMOS circuit (for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor in layer 985.

The layer 983 and the layers 984[1] to 984[K] can each include various materials, such as a conductor, a semiconductor, and an insulator. In addition, the layer 983 and the layers 984[1] to 984[K] can each include various elements, such as a capacitor and a transistor.

Note that the semiconductor layer including the channel formation region of the transistor provided in layer 983 and the semiconductor layer including the channel formation region of the transistor provided in layers 984[1] to 984[K] may have the same material or different materials. Furthermore, the transistor provided in layer 983 and the transistor provided in layers 984[1] to 984[K] may have the same structure or different structures.

One embodiment of the present invention can have a structure in which, for example, OS transistors (transistors including an oxide semiconductor in a channel formation region) are provided in layer 983 and layers 984[1] to 984[K].

OS transistors have the characteristic of having an extremely low off-state current. In addition, the off-state current hardly increases even in a high-temperature environment, and the on-state current is not easily decreased. Therefore, for example, when a wiring electrically connected to one of the source and drain of an OS transistor is in a floating state (also called floating), the charge accumulated in the wiring can be held for a long period of time. Therefore, in one embodiment of the present invention, for example, by forming a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.

In one embodiment of the present invention, the OS transistor may have a structure in which, for example, a planar transistor is provided in layer 983, and vertical transistors (transistors in which at least a part of a semiconductor layer including a channel formation region is provided in an opening formed in an insulating layer) are provided in layers 984[1] to 984[K]. Note that the detailed structure of the vertical transistor will be described later with reference to FIG. 7A and FIG. 7B, etc.

Vertical transistors have a structure that makes it easier to reduce the area (footprint) they occupy compared to planar transistors. In addition, because the channel length can be made small and the channel width can be made large, it is easy to reduce the on-resistance (increase the on-current). Therefore, one aspect of the present invention is that, for example, by configuring a memory cell using vertical transistors, the cell area (cell size) of the memory cell can be reduced.

Planar transistors have a structure that makes it easier to increase the channel length compared to vertical transistors, and therefore, for example, it is easy to reduce short channel effects such as drain induced barrier lowering (DIBL). In other words, it is easy to realize a transistor with high saturation (in the saturation region of the transistor, the change in drain current with respect to the drain voltage is small). Therefore, one aspect of the present invention is, for example, to improve the characteristics of a sense amplifier by configuring the sense amplifier using planar transistors.

Note that, for example, vertical transistors may be provided in layer 983. Also, for example, planar transistors may be provided in layers 984[1] to 984[K].

Although not shown, the electronic calculator 900 may have a configuration in which wiring layers are appropriately provided between each of the

layers

985, 983, and 984[1] to 984[K]. The wiring layers may include wiring for electrically connecting various elements to each other.

Also, as shown in FIG. 2, the electronic computer 900 may have a configuration in which multiple layers 983 (layers 983[1] to 983[H] (H is an integer of 2 or more)) are provided, and layers 983[1] to 983[H] are stacked.Also, the electronic computer 900 may have a configuration in which multiple layers 982 (layers 982[1] to 982[L] (L is an integer of 2 or more)) are provided, and layers 982[1] to 982[L] are stacked.

FIG. 1C is a schematic diagram illustrating an example of the arrangement of each component of the electronic calculator 900. In the electronic calculator 900, each component shown in FIG. 1A can be appropriately arranged, for example, in each layer shown in FIG. 1B. Note that FIG. 1C illustrates an arithmetic unit 911, a control unit 912, a scan flip-flop 915, and a backup memory 916 of the processing unit 910 as some of the components of the electronic calculator 900. Also illustrated is a memory cell 925 and a sense amplifier 926 of the storage unit 920.

1C shows an electronic calculator 900 having a layer 985, a layer 983, and layers 984[1] to 984[K]. As shown in FIG. 1C, the arithmetic unit 911, the control unit 912, the scan flip-flop 915, and the sense amplifier 926 are arranged in the layer 985. Although not shown, the control unit 930 and the control unit 922 of the memory unit 920 are also arranged in the layer 985. The sense amplifier 926 can be arranged, for example, between the arithmetic unit 911 and the control unit 912. The backup memory 916 is arranged in the layer 983 so as to overlap the scan flip-flop 915. The memory cell 925 is arranged in the layers 984[1] to 984[K] so as to overlap the sense amplifier 926. The memory cell 925 can be arranged, for example, so as to overlap the arithmetic unit 911 and the control unit 912. It can also be placed, for example, so that it overlaps the backup memory 916.

In other words, the electronic calculator 900 shown in FIG. 1C can be said to have a configuration in which the memory array unit 921 of the storage unit 920 is arranged inside the processing unit 910. Note that the control unit 922 may also be arranged inside the processing unit 910.

By using such an arrangement, for example, the dead space of layer 983 and layers 984[1] to 984[K] can be reduced, improving area efficiency. Therefore, the surface density (recording density) of the memory array section 921 can be improved. Therefore, the storage capacity of the storage section 920 of the electronic computer 900 can be improved, and the electronic computer 900 can be made smaller. In addition, for example, the bus line 971 between the processing section 910 and the storage section 920 can be shortened. Therefore, the access time (the time required to write and read data) and the access energy (the energy consumed by writing and reading data) can be reduced. Therefore, the operating speed of the electronic computer 900 can be improved, and power consumption can be reduced.

Below, specific configuration examples of a semiconductor device that can be used for the register unit 914, a semiconductor device that can be used for the memory block 923, and a memory device that can be used for the memory unit 920 will be described.

In the following description, the potential corresponding to binary data is set to potential VDD, which is a high power supply potential, and the potential corresponding to binary data "0" is set to potential VSS, which is a low power supply potential. The potential VDD is set to a potential higher than at least the threshold voltage of the transistor with respect to the potential VSS. The potential VSS may be, for example, a ground potential. The potential of the signal is set to potential H or potential L. The potential H is set to a potential that is applied to the gate of an n-channel transistor to make the transistor conductive, and is set to a potential that is applied to the gate of a p-channel transistor to make the transistor non-conductive. The potential L is set to a potential that is applied to the gate of an n-channel transistor to make the transistor non-conductive, and is set to a potential that is applied to the gate of a p-channel transistor to make the transistor conductive. The potential H can be set to, for example, the same potential as the potential VDD or a potential higher than the potential VDD. The potential L can be, for example, the same potential as the potential VSS or a potential lower than the potential VSS.

Note that the potential H and the potential L do not need to be the same for each of the multiple signals. The potential H and the potential L for each of the multiple signals may be different depending on the threshold voltage of the transistor to which the signal is applied. For example, the potential H and the potential L of a signal applied to the gate of a Si transistor provided in layer 985 may be different from the potential H and the potential L of a signal applied to the gate of an OS transistor provided in layer 983 and layers 984[1] to 984[K].

<Semiconductor device that can be used for the memory portion 920>
A semiconductor device 710 according to one embodiment of the present invention will be described. At least a part of the semiconductor device 710 can be used for, for example, the electronic computer 900 illustrated in FIG. 1A or the like. For example, the semiconductor device can be used for the memory block 923 included in the storage portion 920.

[Configuration example]
FIG. 3 is a circuit diagram illustrating an example of the configuration of a semiconductor device 710. As shown in FIG.

The semiconductor device 710 shown in FIG. 3 has a plurality of memory cells 741 and a sense circuit 751.

As one aspect of the present invention, when the semiconductor device 710 is used in the memory block 923 of the electronic computer 900 described above, for example, the memory cell 741 corresponds to the memory cell 925, and the sense circuit 751 corresponds to the sense amplifier 926. That is, for example, the memory cell 741 is arranged in layers 984[1] to 984[K], and the sense circuit 751 is arranged in layer 985. Therefore, for example, a vertical OS transistor can be used for the memory cell 741, and a Si transistor can be used for the sense circuit 751.

Note that FIG. 3 shows, as representative examples, eight memory cells 741 arranged in layer 984[1], eight memory cells 741 arranged in layer 984[2], and eight memory cells 741 arranged in layer 984[K].

Some of the memory cells 741 are electrically connected to the sense circuit 751 via wiring RBL that functions as a read bit line. The rest are electrically connected to the sense circuit 751 via wiring RBLB that functions as a read bit line.

When writing data, the sense circuit 751 has a function of applying a potential corresponding to the data to each of the wirings RBL and RBLB. When reading data, the sense circuit 751 has a function of outputting a potential corresponding to the data according to the potential difference between the wirings RBL and RBLB.

11 is a circuit diagram for explaining a specific example of the configuration of the semiconductor device 710 shown in FIG. 3. In FIG. 11, two memory cells (memory cell 741[1,1] and memory cell 741[1,2]) that are arranged in layer 984[1] and electrically connected to the wiring RBL, and two memory cells (memory cell 741[1,3] and memory cell 741[1,4]) that are electrically connected to the wiring RBLB are shown as representatives. In addition, two memory cells (memory cell 741[2,1] and memory cell 741[2,2]) that are arranged in layer 984[2] and electrically connected to the wiring RBL, and two memory cells (memory cell 741[2,3] and memory cell 741[2,4]) that are electrically connected to the wiring RBLB are shown.

The sense circuit 751 has a switch circuit 752, a precharge circuit 753, a precharge circuit 754, an amplifier circuit 755, and a precharge circuit 756. The switch circuit 752, the precharge circuit 753, the precharge circuit 754, the amplifier circuit 755, and the precharge circuit 756 are each electrically connected to the wiring RBL and the wiring RBLB. The switch circuit 752 is electrically connected to the wiring DBL and the wiring DBLB. The sense circuit 751 has a function of controlling writing and reading of data to the memory cell 741.

The switch circuit 752 has a function of turning on or off the wiring pair of the wiring RBL and the wiring RBLB and the wiring pair of the wiring DBL and the wiring DBLB in response to a signal provided to the wiring CSEL. Specifically, the switch circuit 752 has a transistor M721 and a transistor M722. One of the source or the drain of the transistor M721 is electrically connected to the wiring RBL. The other of the source or the drain of the transistor M721 is electrically connected to the wiring DBL. One of the source or the drain of the transistor M722 is electrically connected to the wiring RBLB. The other of the source or the drain of the transistor M722 is electrically connected to the wiring DBLB. The gate of the transistor M721 and the gate of the transistor M722 are electrically connected to the wiring CSEL. The transistors M721 and M722 are n-channel transistors.

The precharge circuit 753 has a function of precharging the wiring RBL and the wiring RBLB to a potential applied to the wiring VPRE in response to a signal applied to the wiring EQ. Specifically, the precharge circuit 753 has a transistor M731, a transistor M732, and a transistor M733. One of the source or drain of the transistor M731 is electrically connected to the wiring RBL. The other of the source or drain of the transistor M731 is electrically connected to the wiring RBLB. One of the source or drain of the transistor M732 is electrically connected to the wiring RBL. One of the source or drain of the transistor M733 is electrically connected to the wiring RBLB. The other of the source or drain of the transistor M732 and the other of the source or drain of the transistor M733 are electrically connected to the wiring VPRE. The gates of the transistors M731, M732, and M733 are electrically connected to the wiring EQ. Transistors M731, M732, and M733 are n-channel transistors.

The precharge circuit 754 has a function of precharging the wiring RBL and the wiring RBLB to a potential applied to the wiring VPRE in response to a signal applied to the wiring EQB. Specifically, the precharge circuit 754 has a transistor M741, a transistor M742, and a transistor M743. One of the source or drain of the transistor M741 is electrically connected to the wiring RBL. The other of the source or drain of the transistor M741 is electrically connected to the wiring RBLB. One of the source or drain of the transistor M742 is electrically connected to the wiring RBL. One of the source or drain of the transistor M743 is electrically connected to the wiring RBLB. The other of the source or drain of the transistor M742 and the other of the source or drain of the transistor M743 are electrically connected to the wiring VPRE. The gates of the transistors M741, M742, and M743 are electrically connected to the wiring EQB. Transistor M741, transistor M742, and transistor M743 are p-channel transistors.

The amplifier circuit 755 has a function of outputting a potential corresponding to one of the binary data to the wiring RBL and outputting a potential corresponding to the other of the binary data to the wiring RBLB by applying a predetermined potential to each of the wiring SAP and the wiring SAN. Specifically, the amplifier circuit 755 has a transistor M751, a transistor M752, a transistor M753, and a transistor M754. One of the source or drain of the transistor M751 is electrically connected to the wiring RBL. One of the source or drain of the transistor M752 is electrically connected to the wiring RBLB. One of the source or drain of the transistor M753 is electrically connected to the wiring RBL. One of the source or drain of the transistor M754 is electrically connected to the wiring RBLB. The other of the source or drain of the transistor M751 and the other of the source or drain of the transistor M752 are electrically connected to the wiring SAP. The other of the source or drain of the transistor M753 and the other of the source or drain of the transistor M754 are electrically connected to the wiring SAN. The gates of the transistors M751 and M753 are electrically connected to the wiring RBLB. The gates of the transistors M752 and M754 are electrically connected to the wiring RBL. The transistors M751 and M752 are p-channel transistors. The transistors M753 and M754 are n-channel transistors.

The precharge circuit 756 is electrically connected to the wiring RBL and the wiring RBLB. The precharge circuit 756 has a function of precharging the wiring RBL to a potential provided to the wiring VPRE2 in response to a signal provided to the wiring SW4. The precharge circuit 756 also has a function of precharging the wiring RBLB to a potential provided to the wiring VPRE2 in response to a signal provided to the wiring SW5. Specifically, the precharge circuit 756 has a transistor M771 and a transistor M772. One of the source or drain of the transistor M771 is electrically connected to the wiring RBL. One of the source or drain of the transistor M772 is electrically connected to the wiring RBLB. The other of the source or drain of the transistor M771 and the other of the source or drain of the transistor M772 are electrically connected to the wiring VPRE2. The gate of the transistor M771 is electrically connected to the wiring SW4. The gate of the transistor M772 is electrically connected to the wiring SW5. Transistor M771 and transistor M772 are p-channel transistors.

Here, in the semiconductor device 710, when any one of the multiple memory cells 741 is selected and data is written to the memory cell 741, a signal is applied to the wiring WWL electrically connected to the memory cell 741. For example, in FIG. 11, when data is written to the memory cell 741[1,1] arranged in the layer 984[1], a potential H is applied to the wiring WWL electrically connected to the memory cell 741[1,1], and a potential L is applied to the wiring WWL electrically connected to the other memory cells 741.

Furthermore, in the semiconductor device 710, when any one of the memory cells 741 is selected and data is read from the memory cell 741, a signal can be applied to the wiring RWL electrically connected to the memory cell 741. For example, in FIG. 11, when data is read from the memory cell 741[1,1] arranged in the layer 984[1], a potential H can be applied to the wiring RWL electrically connected to the memory cell 741[1,1], and a potential L can be applied to the wiring RWL electrically connected to the other memory cells 741.

<Memory Cells That Can Be Used for the Storage Unit 920>
A memory cell according to one embodiment of the present invention will be described. The memory cell can be used, for example, in the electronic computer 900 illustrated in FIG. 1A or the like. For example, the memory cell can be used as the memory cell 925 included in the storage unit 920.

Each of Figures 4A to 4D is a circuit diagram illustrating an example of the configuration of a memory cell according to one embodiment of the present invention.

The memory cell 741a shown in FIG. 4A includes a transistor 42, a transistor 41, and a capacitor 51. One of the source and drain of the transistor 42 is electrically connected to the gate of the transistor 41 and one terminal of the capacitor 51. The other of the source and drain of the transistor 42 is electrically connected to a wiring WBL that functions as a write bit line. The gate of the transistor 42 is electrically connected to a wiring WWL that functions as a write word line. One of the source and drain of the transistor 41 is electrically connected to a wiring RBL that functions as a read bit line. The other of the source and drain of the transistor 41 is electrically connected to a wiring RWL that functions as a read word line. The other terminal of the capacitor 51 is electrically connected to a wiring CL. Note that the wiring in which the one of the source and drain of the transistor 42, the gate of the transistor 41, and one terminal of the capacitor 51 are electrically connected to each other may be described as a wiring MN.

Memory cell 741a can store binary data by associating the high or low potential according to the amount of charge held in wiring MN with "1" or "0." When writing data, memory cell 741a can apply a potential corresponding to the data from wiring WBL to wiring MN by turning transistor 42 on. When reading data, memory cell 741a can extract a potential corresponding to the data to wiring RBL by turning transistor 41 on or off depending on the potential of wiring MN.

In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor 42. Also, for example, an n-channel transistor can be used as the transistor 41.

Note that in the memory cell 741a shown in FIG. 4A, a configuration in which an OS transistor is used as the transistor 42 may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. Since NOSRAM uses an OS transistor with an extremely low off-state current, it can store data for a long period of time. In addition, since the writing transistor (transistor 42) and the reading transistor (transistor 41) are different, data is read nondestructively. Therefore, for example, it can be used as a nonvolatile memory.

Memory cell 741b shown in FIG. 4B is a modified example of memory cell 741a shown in FIG. 4A, and differs in that the other of the source or drain of transistor 42 is electrically connected to wiring BL, and one of the source or drain of transistor 41 is electrically connected to wiring BL.

Memory cell 741c shown in FIG. 4C is a modified example of memory cell 741a shown in FIG. 4A, and differs in that the other of the source and drain of transistor 41 is electrically connected to wiring PL, and the other terminal of capacitor 51 is electrically connected to wiring RWL.

Memory cell 741d shown in FIG. 4D is a modification of memory cell 741c shown in FIG. 4C, and differs in that a p-channel transistor is used for transistor 41.

<Memory device that can be used for memory cell 741>
A specific configuration example of a memory device that can be used for the memory cell 741 included in the semiconductor device of one embodiment of the present invention will be described below with reference to drawings.

A memory device according to one embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer.

In a memory device according to one embodiment of the present invention, a first transistor, a capacitor, and a second transistor are arranged so as to overlap each other. Therefore, the area occupied by the memory device in a planar view can be reduced. For example, when a memory device according to one embodiment of the present invention is applied to a memory cell 741, the area occupied by the memory cell in a planar view can be reduced. Therefore, the memory cell can be miniaturized, and a semiconductor device capable of high integration can be realized.

In addition, in a memory device according to one embodiment of the present invention, a second transistor is stacked on a first transistor. The first transistor and the second transistor each have a source electrode and a drain electrode that are overlapped at different heights with respect to a substrate surface, and a drain current flows in the height direction (vertical direction) (the above-mentioned "vertical transistor"). Therefore, the transistor can be miniaturized more than a transistor (planar transistor) in which the source electrode and the drain electrode are provided on the same plane. When the memory device according to one embodiment of the present invention includes a transistor with the above-mentioned structure, a semiconductor device that can be further miniaturized and highly integrated can be realized.

In one embodiment of the memory device of the present invention, the first insulating layer is located between the source electrode and drain electrode of the first transistor, and the second insulating layer is located between the source electrode and drain electrode of the second transistor.

In addition, in a memory device according to one embodiment of the present invention, a part of a component of the first transistor (the gate electrode) also functions as a part of a component of the second transistor (either the source electrode or the drain electrode).

In other words, in a memory device according to one embodiment of the present invention, some of the components of the first transistor also serve as some of the components of the second transistor.

In addition, in a memory device according to one embodiment of the present invention, an insulating layer (third insulating layer) and a conductive layer constituting a part of the capacitance are stacked in this order on the first transistor so as to have an area overlapping with the gate electrode of the first transistor. In the capacitance of the memory device according to one embodiment of the present invention, the gate electrode of the first transistor functions as one electrode, the insulating layer (third insulating layer) functions as a dielectric layer, and the conductive layer functions as the other electrode. In other words, in the memory device according to one embodiment of the present invention, an insulating layer (third insulating layer) and a conductive layer constituting a part of the capacitance are provided so as to have an area overlapping with the first transistor, and the gate electrode of the first transistor has a configuration that also functions as one electrode of the capacitance.

In addition, in the memory device of one embodiment of the present invention, the side of the conductive layer (conductive layer constituting a part of the capacitance) and the side of a part of the gate electrode of the second transistor (a part buried in the second insulating layer) are provided to face each other through a part of the second insulating layer, a part of the semiconductor layer of the second transistor, and a part of the gate insulating layer of the second transistor. Therefore, in the memory device of one embodiment of the present invention, the region between the conductive layer and the part of the gate electrode of the second transistor (a part buried in the second insulating layer) can also function as a capacitance. That is, in the memory device of one embodiment of the present invention, it can be said that the gate electrode of the second transistor can also function as an electrode of the capacitance. Also, it can be said that the second insulating layer, the semiconductor layer of the second transistor, and the gate insulating layer of the second transistor in the region sandwiched between the conductive layer and the part of the gate electrode of the second transistor (a part buried in the second insulating layer) can also function as a dielectric layer of the capacitance.

In other words, in a memory device according to one embodiment of the present invention, some of the components of the first transistor also serve as some of the components of the capacitance. Also, some of the components of the second transistor also serve as some of the components of the capacitance.

As described above, in a memory device according to one embodiment of the present invention, the number of steps can be significantly reduced compared to the case where the first transistor and the second transistor are fabricated independently. In addition, the number of steps can be significantly reduced compared to the case where the capacitor and the first transistor are fabricated independently. In addition, the number of steps can be significantly reduced compared to the case where the capacitor and the second transistor are fabricated independently. Therefore, a low-cost memory device can be realized. In addition, a method for fabricating a memory device with high yield can be provided.

Below, we will describe a specific example of the configuration of a memory device according to one embodiment of the present invention.

<Configuration example 1 of storage device>
Fig. 5A is a plan view showing a configuration example of a memory device according to one embodiment of the present invention. In Fig. 5A, some elements such as an insulating layer are omitted for clarity of the drawing. Some elements are also omitted in the plan views shown below. Fig. 5B is a cross-sectional view taken along dashed line A1-A2 in Fig. 5A. Fig. 5C is a cross-sectional view taken along dashed line A3-A4 in Fig. 5A. Fig. 6 is a cross-sectional view taken along dashed line A5-A6 in Fig. 5A.

A memory device according to one embodiment of the present invention includes a transistor 41, a transistor 42, a capacitor 51, an insulating layer 103a, and an insulating layer 103b.

The insulating layer 103a is provided on the insulating layer 101. The transistor 41 is provided on the insulating layer 101 so that a portion of the transistor 41 is embedded in the insulating layer 103a. A portion of the components of the capacitor 51 is provided on the transistor 41 so that it has an area that overlaps with the transistor 41. The insulating layer 103b is provided so as to cover the transistor 41 and the capacitor 51. The transistor 42 is provided so as to overlap with the transistor 41 and the capacitor 51 so that a portion of the transistor 42 is embedded in the insulating layer 103b.

Here, it is preferable that insulating layer 101, insulating layer 103a, and insulating layer 103b each function as an interlayer insulating layer and are planarized. Note that the insulating layers functioning as interlayer insulating layers do not have to be planarized.

Transistor 41 has conductive layer 111a, conductive layer 112a, semiconductor layer 113a, insulating layer 105a, and conductive layer 115a.

The conductive layer 111a functions as one of the source electrode and drain electrode of the transistor 41. The conductive layer 112a functions as the other of the source electrode and drain electrode of the transistor 41. The insulating layer 105a functions as the gate insulating layer of the transistor 41. The conductive layer 115a functions as the gate electrode of the transistor 41.

The conductive layer 111a is provided on the insulating layer 101, the insulating layer 103a is provided on the insulating layer 101 and on the conductive layer 111a, and the conductive layer 112a is provided on the insulating layer 103a. The conductive layer 111a and the conductive layer 112a have an area where they overlap with each other via the insulating layer 103a. Note that in FIG. 5A and FIG. 5B, an example is shown in which the side end of the conductive layer 111a is located inside the side end of the conductive layer 112a that does not face the opening 121a in the X direction, that is, the side end of the conductive layer 112a that does not face the opening 121a does not overlap with the conductive layer 111a, and the side end of the conductive layer 111a overlaps with the conductive layer 112a, but this is not a limitation of one embodiment of the present invention. For example, the side end of the conductive layer 111a may be located outside the side end of the conductive layer 112a that does not face the opening 121a.

The insulating layer 103a and the conductive layer 112a have an opening 121a that reaches the conductive layer 111a. FIG. 5A shows an example in which the shape of the opening 121a is circular in a plan view. By making the top surface shape of the opening 121a (the outline shape in a plan view) circular, the processing accuracy when forming the opening 121a can be improved, and the opening 121a can be formed with a fine size. The top surface shape of the opening 121a may be, for example, an ellipse, a polygon such as a square, or a polygon with rounded corners.

The semiconductor layer 113a is provided so as to cover the opening 121a and have a region located inside the opening 121a. The semiconductor layer 113a has a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side of the conductive layer 112a in the opening 121a, a region in contact with the side of the insulating layer 103a in the opening 121a, and a region in contact with the upper surface of the conductive layer 111a in the opening 121a. The semiconductor layer 113a has a shape that follows the upper surface of the conductive layer 112a, the side of the conductive layer 112a in the opening 121a, the side of the insulating layer 103a in the opening 121a, and the upper surface of the conductive layer 111a in the opening 121a. As a result, the semiconductor layer 113a has a recess at a position that overlaps with the opening 121a.

Note that in FIG. 5B, the side of the semiconductor layer 113a is shown to roughly coincide with the side of the conductive layer 112a that does not face the opening 121a in the X direction, but this is not a limitation of one aspect of the present invention. For example, the side of the semiconductor layer 113a may be located outside or inside the side of the conductive layer 112a that does not face the opening 121a in the X direction.

However, it is preferable that the semiconductor layer 113a covers the side end of the conductive layer 112a on the opening 121a side. For example, in Fig. 5A and Fig. 5B, a configuration is shown in which the side end of the semiconductor layer 113a extends to the outside of the opening 121a in the X direction and roughly coincides with the side end of the conductive layer 112a that does not face the opening 121a. It can also be said that the lower end of the semiconductor layer 113a roughly coincides with the upper end of the conductive layer 112a in the X direction. That is, an example is shown in which the entire semiconductor layer 113a overlaps with the conductive layer 112a or the opening 121a. Also, Fig. 5A and Fig. 5B show a configuration in which the side end of the semiconductor layer 113a is located outside the side end of the conductive layer 111a in the X direction. That is, an example is shown in which a part of the semiconductor layer 113a overlaps with the conductive layer 111a.

In this specification, the upper end refers to the uppermost part of the side end, and the lower end refers to the lowermost part of the side end. In other words, the upper end and the lower end are each part of the side end.

Note that although the semiconductor layer 113a is shown as a single-layer structure in FIG. 5B, FIG. 5C, and FIG. 6, one embodiment of the present invention is not limited to this. The semiconductor layer 113a may have a stacked structure of two or more layers.

The insulating layer 105a, which functions as a gate insulating layer of the transistor 41, is provided so as to cover the opening 121a and have a region located inside the opening 121a. The insulating layer 105a is provided on the semiconductor layer 113a, the conductive layer 112a, and the insulating layer 103a. The insulating layer 105a has a region in contact with the upper surface of the semiconductor layer 113a, a region in contact with the side of the semiconductor layer 113a, a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side of the conductive layer 112a, and a region in contact with the upper surface of the insulating layer 103a. The insulating layer 105a has a shape that follows the upper surface of the semiconductor layer 113a, the side of the semiconductor layer 113a, the upper surface of the conductive layer 112a, the side of the conductive layer 112a, and the upper surface of the insulating layer 103a. As a result, the insulating layer 105a has a recess at a position that overlaps with the opening 121a.

The conductive layer 115a, which functions as the gate electrode of the transistor 41, is provided on the insulating layer 105a and has a region in contact with the top surface of the insulating layer 105a. The conductive layer 115a has a region that overlaps with the semiconductor layer 113a via the insulating layer 105a. Here, the semiconductor layer 113a can be configured to cover the side and bottom surfaces of the conductive layer 115a via the insulating layer 105a inside the opening 121a. For example, inside the opening 121a, the insulating layer 105a has a region in contact with the side surface of the semiconductor layer 113a, a region in contact with the top surface of the recess of the semiconductor layer 113a, a region in contact with the side surface of the conductive layer 115a, and a region in contact with the bottom surface of the conductive layer 115a.

From the above, the transistor 41 shown in Figures 5B and 5C is a transistor in which a semiconductor layer (semiconductor layer 113a), a gate insulating layer (insulating layer 105a), and a gate electrode (conductive layer 115a) are provided inside an opening (opening 121a) formed in an interlayer insulating layer (insulating layer 103a). In other words, it is a transistor in which the semiconductor layer is provided to surround the gate electrode via the gate insulating layer in a plan view. This allows the channel length direction of the transistor 41 to be along the side surface of the insulating layer 103a in the opening 121a in a cross-sectional view. Therefore, since the channel length is no longer affected by the performance of the exposure device used to manufacture the transistor 41, the channel length can be made smaller than the limit resolution of the exposure device. Therefore, the transistor 41 can be miniaturized. For example, FIG. 5A shows an example in which the entire opening 121a has an area overlapping with the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a, but a part of the opening 121a does not have to overlap with at least one of the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a.

Transistor 41 is a so-called top-gate type transistor that has a gate electrode above semiconductor layer 113a. Furthermore, since the bottom surface of semiconductor layer 113a (the surface on the insulating layer 101 side) is in contact with each of the source electrode and drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor.

As shown in Figures 5B and 5C, a portion of the insulating layer 105a is located outside the opening 121a, that is, on the conductive layer 112a and on the insulating layer 103a. At this time, it is preferable that the insulating layer 105a covers the side end portion of the semiconductor layer 113a. This can prevent the conductive layer 115a and the semiconductor layer 113a from shorting out. It is also preferable that the insulating layer 105a covers the side end portion of the conductive layer 112a. This can prevent the conductive layer 115a and the conductive layer 112a from shorting out.

Also, as shown in Figures 5B and 5C, etc., a portion of the conductive layer 115a is located outside the opening 121a, that is, on the conductive layer 112a and on the insulating layer 103a. Note that, although Figures 5B and 5C, etc., show an example in which the side end of the conductive layer 115a is located inside the side end of the semiconductor layer 113a, this is not limited thereto. The side end of the conductive layer 115a may be located outside the side end of the semiconductor layer 113a.

Insulating layer 107a is provided in contact with the top surface of insulating layer 105a, the side surface of conductive layer 115a, and the top surface of conductive layer 115a. Insulating layer 135 is provided on insulating layer 107a. Conductive layer 141 is provided on insulating layer 135 so as to have an area overlapping with conductive layer 115a. Note that conductive layer 141 is provided with a gap between insulating layer 103a and opening 121a provided in conductive layer 112a in plan view.

Capacitor 51 has conductive layer 115a, conductive layer 141, a portion of insulating layer 107a (portion sandwiched between conductive layer 115a and conductive layer 141), and a portion of insulating layer 135 (portion sandwiched between conductive layer 115a and conductive layer 141). In addition to the above, capacitor 51 has a portion of conductive layer 115b (portion located within opening 121b) that functions as the gate electrode of transistor 42, insulating layer 103b on transistor 41 in the region sandwiched between the portion of conductive layer 115b and conductive layer 141, semiconductor layer 113b that functions as the semiconductor layer of transistor 42, and insulating layer 105b that functions as the gate insulating layer of transistor 42.

The conductive layer 115a functions as one electrode of the capacitor 51. The conductive layer 141 functions as the other electrode of the capacitor 51. A portion of the insulating layer 107a (the portion sandwiched between the conductive layer 115a and the conductive layer 141) and a portion of the insulating layer 135 (the portion sandwiched between the conductive layer 115a and the conductive layer 141) function as the dielectric layer of the capacitor 51.

In addition to the above, a portion of the conductive layer 115b (the portion located within the opening 121b) can also function as an electrode of the capacitor 51. The insulating layer 103b, the semiconductor layer 113b, and the insulating layer 105b in the area sandwiched between the conductive layer 141 and the portion of the conductive layer 115b can also function as a dielectric layer of the capacitor 51.

In other words, the memory device of one embodiment of the present invention has two regions that can function as a capacitance: between the conductive layer 141 and the conductive layer 115a, and between the conductive layer 141 and a part of the conductive layer 115b (a part located in the opening 121b), and these two regions together can be said to be the capacitance 51. By having the above-mentioned configuration of the capacitor 51, even if the conductive layer 141 has a fine top surface shape, a capacitance value required for operating the memory device of one embodiment of the present invention can be ensured by adjusting the film thickness of the conductive layer 141.

An insulating layer 103b is provided on the transistor 41 and the capacitor 51.

The insulating layer 107a functions as the dielectric layer of the capacitor 51 and also has the function of suppressing the diffusion of impurities into the transistor 41. For example, it has the function of suppressing the diffusion of impurities into the semiconductor layer 113a.

As described above, the insulating layer 135 functions as the dielectric layer of the capacitor 51. For the insulating layer 135, it is preferable to use a material with a high relative dielectric constant, a so-called high-k material, as described in the [Insulator] section below. By using a material with a high relative dielectric constant for the insulating layer 135, the capacitance value of the capacitor 51 can be increased. This makes it possible to realize a storage device with a long data retention time. Furthermore, by extending the data retention time, the frequency of periodic data rewriting (refresh operation) can be reduced, making it possible to realize a storage device with low power consumption.

Insulating layer 135 may be made of a material that can have ferroelectricity, as described in the "Insulator" section below. By using a material that can have ferroelectricity for insulating layer 135, a non-volatile memory device can be realized. This makes the above-mentioned refresh operation unnecessary, and makes it possible to realize a memory device with even lower power consumption.

Note that a portion of the insulating layer 103b can also function as the dielectric layer of the capacitor 51, but as described above, the insulating layer 103b also functions as an interlayer insulating layer. Therefore, it is preferable to use a material with a low relative dielectric constant, as described in the [Insulator] section, for the insulating layer 103b. By using a material with a low relative dielectric constant for the insulating layer 103b, it is possible to reduce the parasitic capacitance that occurs between the wiring of the memory device. For the same reason, it is preferable to use a material with a low relative dielectric constant for the insulating layer 103a as well.

Transistor 42 has conductive layer 115a, conductive layer 112b, semiconductor layer 113b, insulating layer 105b, and conductive layer 115b.

The conductive layer 115a functions as one of the source electrode and drain electrode of the transistor 42. The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 42. The insulating layer 105b functions as the gate insulating layer of the transistor 42. The conductive layer 115b functions as the gate electrode of the transistor 42.

As described above, the conductive layer 115a also functions as the gate electrode of the transistor 41. Therefore, in the memory device shown in Figures 5A to 6, the conductive layer 115a functions as both the gate electrode of the transistor 41 and one of the source electrode and drain electrode of the transistor 42.

An insulating layer 103b is provided on the conductive layer 115a. A conductive layer 112b is provided on the insulating layer 103b. The conductive layer 115a and the conductive layer 112b have an overlapping region with the insulating layer 103b interposed therebetween.

The conductive layer 112b, the insulating layer 103b, the insulating layer 135, and the insulating layer 107a have an opening 121b that reaches the conductive layer 115a. FIG. 5A shows an example in which the shape of the opening 121b is circular in a plan view. Note that the opening 121b can have the same shape as the opening 121a.

The configuration of the transistor 42 can be the same as that of the transistor 41 described above, except for the configuration of one of the source electrode or drain electrode described above. The description of the configuration of the transistor 42 can be made by referring to the description of the configuration of the transistor 41, by replacing the transistor 41, insulating layer 103a, insulating layer 105a, conductive layer 112a, semiconductor layer 113a, and conductive layer 115a with the transistor 42, insulating layer 103b, insulating layer 105b, conductive layer 112b, semiconductor layer 113b, and conductive layer 115b, respectively, except for the configuration of one of the source electrode or drain electrode described above, and making appropriate necessary changes.

In this specification and the like, insulating layer 103a and insulating layer 103b may be collectively referred to as insulating layer 103. Insulating layer 105a and insulating layer 105b may be collectively referred to as insulating layer 105. Insulating layer 107a and insulating layer 107b may be collectively referred to as insulating layer 107. Conductive layer 112a and conductive layer 112b may be collectively referred to as conductive layer 112. Semiconductor layer 113a and semiconductor layer 113b may be collectively referred to as semiconductor layer 113. Conductive layer 115a and conductive layer 115b may be collectively referred to as conductive layer 115. Opening 121a and opening 121b may be collectively referred to as opening 121.

An insulating layer 107b is provided on the conductive layer 115b and the insulating layer 105b. The insulating layer 107b can be provided so as to cover the upper surface and side surfaces of the conductive layer 115b. The insulating layer 107b has a function of suppressing the diffusion of impurities into the transistor 42. For example, it has a function of suppressing the diffusion of impurities into the semiconductor layer 113b.

As described above, in a memory device according to one embodiment of the present invention, the transistor 41, the capacitor 51, and the transistor 42 are stacked. In addition, the transistor 41 and the transistor 42 each have a semiconductor layer, a gate insulating layer, and a gate electrode provided inside an opening formed in an interlayer insulating layer, and one of a source electrode or a drain electrode is provided under the opening, and the other of a source electrode or a drain electrode is provided on the interlayer insulating layer. This can reduce the area occupied by the memory device in a planar view. Therefore, the memory device can be miniaturized. Therefore, according to one embodiment of the present invention, a memory device capable of high integration can be provided.

Furthermore, in a memory device according to one embodiment of the present invention, some of the components of the transistor 41 also serve as some of the components of the transistor 42. Further, some of the components of the transistor 41 also serve as some of the components of the capacitor 51. Further, some of the components of the transistor 42 also serve as some of the components of the capacitor 51.

Therefore, in the memory device of one embodiment of the present invention, the number of steps can be significantly reduced compared to the case where the transistor 41 and the transistor 42 are fabricated independently. In addition, the number of steps can be significantly reduced compared to the case where the capacitor 51 and the transistor 41 are fabricated independently. In addition, the number of steps can be significantly reduced compared to the case where the capacitor 51 and the transistor 42 are fabricated independently. As a result, a low-cost memory device can be realized. In addition, a method for fabricating a memory device with high yield can be provided.

Note that in the cross-sectional views shown in Figures 5B to 6, the boundaries between layers may not be clearly visible. For example, the boundary between two insulating layers that contact each other may not be clearly visible. Also, the boundary between two conductive layers that contact each other may not be clearly visible. Furthermore, the boundary between two semiconductor layers that contact each other may not be clearly visible.

FIG. 7A is an enlarged view of transistor 41 shown in FIG. 5C and its vicinity. FIG. 7B shows a plan view of the XY plane of the transistor shown in FIG. 7A. Note that conductive layer 111a is not shown in FIG. 7B. The configuration shown in FIG. 7A can also be applied to transistor 42 by replacing conductive layer 111a with conductive layer 115a. The configuration shown in FIG. 7B can be applied to both transistor 41 and transistor 42.

As shown in FIG. 7A, the semiconductor layer 113 has a region 113i and regions 113na and 113nb arranged to sandwich the region 113i.

Region 113na is a region in contact with conductive layer 111a of semiconductor layer 113. At least a portion of region 113na functions as one of the source region or drain region of the transistor. Region 113nb is a region in contact with conductive layer 112 of semiconductor layer 113. At least a portion of region 113nb functions as the other of the source region or drain region of the transistor. As shown in FIG. 7B, conductive layer 112 is in contact with the entire outer periphery of semiconductor layer 113. Therefore, the other of the source region or drain region of the transistor can be formed on the entire outer periphery of a portion of semiconductor layer 113 that is formed at the same height as conductive layer 112.

Region 113i is a region between regions 113na and 113nb of the semiconductor layer 113. At least a part of region 113i functions as a channel formation region of the transistor. In other words, the channel formation region of the transistor is located in the region between conductive layer 111a and conductive layer 112 of the semiconductor layer 113. It can also be said that the channel formation region of the transistor is located in the region of the semiconductor layer 113 that is in contact with the insulating layer 103 or in a region in the vicinity of the region.

The channel length of a transistor is the distance between the source region and the drain region. In other words, it can be said that the channel length of a transistor is determined by the thickness of the insulating layer 103 on the conductive layer 111a. In FIG. 7A, the channel length L of a transistor is indicated by a solid double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the semiconductor layer 113 and the conductive layer 111a contact, and the end of the region where the semiconductor layer 113 and the conductive layer 112 contact. In other words, the channel length L corresponds to the length of the side of the insulating layer 103 on the opening 121 side in a cross-sectional view.

In planar transistors, for example, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 103. Therefore, the channel length of the transistor can be made into a very fine structure below the exposure limit of photolithography (for example, 1 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm). This increases the on-current of the transistor, and improves the frequency characteristics. Therefore, a memory device with a high operating speed can be provided. For example, the read speed and write speed of the memory device can be improved.

Here, as will be described in detail later, a transistor using a metal oxide for the semiconductor layer has higher resistance to the short channel effect than a transistor using silicon for the semiconductor layer. As described above, for example, a transistor having the configuration shown in Figures 7A and 7B can have a shorter channel length than a planar transistor. For this reason, when a transistor has the configuration shown in Figures 7A and 7B, for example, it is preferable to use a metal oxide for the semiconductor layer 113. Note that a material other than a metal oxide, such as silicon, may be used for the semiconductor layer 113.

Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 121. This allows the area occupied by the transistor to be reduced compared to a planar type transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, and therefore the memory capacity per unit area can be increased.

Also, as shown in FIG. 7B, in the XY plane including the channel formation region of the semiconductor layer 113, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged concentrically. Therefore, the side of the conductive layer 115 arranged at the center faces the side of the semiconductor layer 113 through the insulating layer 105. That is, in a plan view, the entire inner circumference of the semiconductor layer 113 becomes the channel formation region. At this time, for example, the channel width of the transistor is determined by the outer periphery length of the semiconductor layer 113. In other words, it can be said that the channel width of the transistor is determined by the size of the maximum width of the opening 121 (the diameter when the opening 121 is circular in a plan view). In FIGS. 7A and 7B, the maximum width D of the opening 121 is indicated by a double-headed arrow of a two-dot chain line. In FIG. 7B, the channel width W of the transistor is indicated by a double-dot chain line of a one-dot chain line. By increasing the size of the maximum width D of the opening 121, the channel width can be increased and the on-current can be increased.

The maximum width D of the opening 121 is preferably, for example, 5 nm to 100 nm, 10 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm. This makes it possible to realize a smaller memory device than when a planar transistor is used. Also, a memory device with a high degree of integration can be realized. As described above, when the opening 121 is circular in a planar view, the maximum width D of the opening 121 corresponds to the diameter of the opening 121, and the channel width W can be calculated as "D x π".

Furthermore, in the memory device of one embodiment of the present invention, the channel length L of the transistor is preferably at least smaller than the channel width W of the transistor. The channel length L of the transistor according to one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

Note that by providing the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 in a concentric manner, the distance between the conductive layer 115 and the semiconductor layer 113 becomes approximately uniform. Therefore, a gate electric field can be applied approximately uniformly from the conductive layer 115 to the semiconductor layer 113.

The sidewalls of the opening 121 are preferably perpendicular to the top surface of the conductive layer 111a, for example. This configuration allows for miniaturization or high integration of the memory device. The sidewalls of the opening 121 may be tapered.

<Configuration example 2 of storage device>
8A to 8C show a configuration example of a memory device according to one embodiment of the present invention, which is different from that shown in FIG. 5A to 5C. FIG. 8A is a plan view showing a configuration example of a part of a memory device. FIG. 8B is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 8A, and FIG. 8C is a cross-sectional view taken along dashed line A3-A4 shown in FIG. 8A. Note that FIG. 6 can be referred to for the cross-sectional view taken along dashed line A5-A6 shown in FIG. 8A.

The storage device shown in Figures 8A to 8C has a different configuration of the capacitor 51 than the storage device shown in Figures 5A to 5C.

Specifically, in the storage device shown in Figures 8A to 8C, the end of the capacitor 51 that does not face the opening 121b is positioned further outward than in the storage device shown in Figures 5A to 5C.

In the capacitor 51 of the memory device shown in Figures 8A to 8C, the end of the conductive layer 141 that does not face the opening 121b extends outward beyond the end of the conductive layer 115a, and the conductive layer 141 has an area that overlaps not only the conductive layer 115a, but also the conductive layer 112a and the insulating layer 103a. Therefore, the conductive layer 141 has an area that overlaps with the top surface of the conductive layer 115a, the side of the conductive layer 115a, the top surface of the conductive layer 112a, the side of the conductive layer 112a, and the top surface of the insulating layer 103a via the insulating layer 107a and the insulating layer 135.

In this case, in addition to the configuration of capacitance 51 shown in Figures 5A to 5C, the region sandwiched between conductive layer 141 and the side surface of conductive layer 115a can also function as part of capacitance 51. Also, the region sandwiched between conductive layer 141 and the top surface of conductive layer 112a located outside conductive layer 115a can also function as part of capacitance 51. Also, the region sandwiched between conductive layer 141 and the side surface of conductive layer 112a can also function as part of capacitance 51.

Therefore, the capacitance value of the capacitor 51 shown in Figures 8A to 8C can be made larger than that of the capacitor 51 shown in Figures 5A to 5C. Therefore, when the storage device shown in Figures 8A to 8C is used, it is possible to realize a storage device that has a longer data retention time and lower power consumption than when the storage device shown in Figures 5A to 5C is used.

Furthermore, the capacitor 51 shown in Figures 8A to 8C has a larger area in a plan view than the capacitor 51 shown in Figures 5A to 5C, and does not require as high a processing precision for the conductive layer 141 as the capacitor 51 shown in Figures 5A to 5C. Therefore, the yield of the memory device can be increased.

With respect to the storage device shown in Figures 8A to 8C, other than the differences mentioned above, the contents described for the storage device shown in Figures 5A to 5C can be referred to.

<Configuration example 3 of storage device>
9A to 9C show configuration examples of a memory device according to one embodiment of the present invention that are different from the configurations described above. Fig. 9A is a plan view showing a configuration example of a part of a memory device. Fig. 9B is a cross-sectional view taken along dashed line A1-A2 in Fig. 9A, and Fig. 9C is a cross-sectional view taken along dashed line A3-A4 in Fig. 9A. Note that Fig. 6 can be referred to for the cross-sectional view taken along dashed line A5-A6 in Fig. 9A.

The storage device shown in Figures 9A to 9C has a different configuration of the capacity 51 than the storage device described above.

Specifically, in the memory device shown in Figures 5A to 5C, the conductive layer 141 is formed only on the upper surface of one side end side (A1 side) of the conductive layer 115a, whereas in the memory device shown in Figures 9A to 9C, the conductive layer 141 is also formed on the upper surface of the other side end side (A2 side) of the conductive layer 115a.

In the memory device shown in Figures 9A to 9C, two conductive layers 141 are arranged in a line symmetrical manner with respect to the dashed line A3-A4 in a plan view. Therefore, it can be said that the memory device shown in Figures 9A to 9C has two of the capacitances 51 of the memory device shown in Figures 5A to 5C.

With this configuration, the capacitance 51 shown in Figures 9A to 9C can have a capacitance value twice that of the capacitance 51 shown in Figures 5A to 5C. Therefore, the memory device shown in Figures 9A to 9C can realize a memory device with a longer data retention time and lower power consumption than the memory device shown in Figures 5A to 5C.

In the storage device shown in Figures 9A to 9C, other than the differences mentioned above, the contents described in the storage device shown in Figures 5A to 5C can be referred to.

<Configuration example 4 of storage device>
10A to 10C show a configuration example of a memory device according to one embodiment of the present invention, which is different from the configuration described above. Fig. 10A is a plan view showing a configuration example of a part of a memory device. Fig. 10B is a cross-sectional view taken along dashed line A1-A2 in Fig. 10A, and Fig. 10C is a cross-sectional view taken along dashed line A3-A4 in Fig. 10A. Note that Fig. 6 can be referred to for the cross-sectional view taken along dashed line A5-A6 in Fig. 10A.

The storage device shown in Figures 10A to 10C has a different configuration of the capacity 51 than the storage device described above.

Specifically, in the memory device described above, the conductive layer 141 is configured to overlap a portion of the conductive layer 115a in a planar view, whereas in the memory device shown in Figures 10A to 10C, the conductive layer 141 is configured to overlap the entire upper surface of the conductive layer 115a so as to surround the opening 121b in a planar view.

In the memory device shown in Figures 10A to 10C, the conductive layer 141 has an opening 127 in a region that overlaps with the opening 121b in a planar view. The opening 127 is provided so as to encompass the opening 121b. That is, in the memory device shown in Figures 10A to 10C, the conductive layer 141 has a region that overlaps with the entire upper surface of the conductive layer 115a except for the region that overlaps with the opening 127 in a planar view.

Note that, although FIG. 10A shows an example in which the shape of opening 127 is circular in a plan view, this is not limiting. For example, the top surface shape of opening 127 may be an ellipse, a polygon such as a rectangle, or a polygon with rounded corners. Also, while FIG. 10A shows an example in which the top surface shape of opening 127 and the top surface shapes of

openings

121a and 121b are all the same circle, this is not limiting. The top surface shapes of opening 127 and the top surface shapes of

openings

121a and 121b may be different from each other.

With this configuration, the capacitance 51 shown in Figures 10A to 10C can have a larger capacitance value than the capacitance 51 of the storage device shown previously. Therefore, the storage device shown in Figures 10A to 10C can realize a storage device that has a longer data retention time and lower power consumption than the storage device shown previously.

In the storage device shown in Figures 10A to 10C, other than the differences mentioned above, the contents described in the storage device shown in Figures 5A to 5C can be referred to.

Below, components of the transistors (transistor 41 and transistor 42) included in a memory device according to one embodiment of the present invention will be described.

[Components of a transistor]
The semiconductor layer 113 (semiconductor layer 113a, semiconductor layer 113b) can be formed of a single layer or a stack of metal oxides described in the section [Metal Oxides] below. The semiconductor layer 113 can be formed of a single layer or a stack of materials such as silicon described in the section [Other Semiconductor Materials] below.

When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto can be used as the semiconductor layer 113. Note that the composition close thereto includes a range of ±30% of the desired atomic ratio. It is also preferable to use gallium as the element M.

When a metal oxide film is formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.

The composition of the metal oxide used in the semiconductor layer 113 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

The atomic layer deposition (ALD) method can be suitably used to form metal oxides.

Alternatively, the metal oxide may be formed by sputtering or chemical vapor deposition (CVD).

When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

The metal oxide used in the semiconductor layer 113 is preferably crystalline. Examples of crystalline oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductors, and single-crystalline oxide semiconductors. It is preferable to use CAAC-OS or nc-OS as the semiconductor layer 113, and it is particularly preferable to use CAAC-OS.

CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed. For example, it is preferable that the semiconductor layer 113 has layered crystals that are approximately parallel to the sidewall of the opening 121 (opening 121a, opening 121b), particularly the side surface of the insulating layer 103 (insulating layer 103a, insulating layer 103b). With this configuration, the layered crystals of the semiconductor layer 113 are formed approximately parallel to the channel length direction of the transistor, thereby increasing the on-current of the transistor.

CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing heat treatment at a temperature at which the metal oxide does not become polycrystallized (e.g., 400°C or higher and 600°C or lower) after the formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

In addition, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that the decrease in electron mobility caused by crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are resistant to heat and highly reliable.

In addition, by using a crystalline oxide such as CAAC-OS as the semiconductor layer 113, it is possible to suppress the extraction of oxygen from the semiconductor layer 113 by the source electrode or drain electrode. As a result, even when heat treatment is performed, it is possible to suppress the extraction of oxygen from the semiconductor layer 113, so that the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.

The crystallinity of the semiconductor layer 113 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

The thickness of the semiconductor layer 113 is preferably, for example, 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 12 nm, or 5 nm to 10 nm. This allows the semiconductor layer 113 to be formed on the sidewall of the opening 121 with good coverage even for openings 121 with a fine diameter, thereby increasing the manufacturing yield of the transistor.

Note that although the semiconductor layer 113 is shown as a single layer in Figures 5B, 5C, 7A, etc., the present invention is not limited to this. The semiconductor layer 113 may have a laminated structure of multiple oxide layers with different chemical compositions. For example, it may have a structure in which multiple types selected from the above metal oxides are appropriately laminated.

As the insulating layer 105 (insulating layer 105a, insulating layer 105b) functioning as a gate insulating layer, the insulators described in the section [Insulators] below can be used in a single layer or a stacked layer. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 105. Silicon oxide and silicon oxynitride are preferable because they are stable to heat.

In addition, the insulating layer 105 may be made of a material with a high relative dielectric constant, so-called high-k material, as described in the section on [Insulator] below. For example, hafnium oxide or aluminum oxide may be used.

The thickness of the insulating layer 105 is preferably, for example, 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. It is preferable that at least a portion of the insulating layer 105 has a region with the above-mentioned thickness. This allows the insulating layer 105 to be formed on the sidewall of the opening 121 with good coverage even for openings 121 with a fine diameter, thereby increasing the manufacturing yield of the transistor.

It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 105 is reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113.

Note that although the insulating layer 105 is shown as a single layer in Figures 5B, 5C, 7A, etc., the present invention is not limited to this. The insulating layer 105 may have a laminated structure.

The conductive layer 115 (conductive layer 115a, conductive layer 115b) functioning as a gate electrode can be a single layer or a stack of conductors described in the section [Conductors] below. For example, the conductive layer 115 can be a conductive material with high conductivity, such as tungsten, aluminum, or copper.

Furthermore, it is preferable to use a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing the diffusion of oxygen, as the conductive layer 115. Examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride, etc.), and a conductive material containing oxygen (e.g., ruthenium oxide, etc.). This can suppress a decrease in the conductivity of the conductive layer 115. Furthermore, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used as the conductive layer 115.

Note that although the conductive layer 115 is shown as a single layer in Figures 5B, 5C, 7A, etc., the present invention is not limited to this. The conductive layer 115 may have a laminated structure.

The conductive layer 111a may be a single layer or a stack of conductors described in the section [Conductor] described later. It is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 111a. For example, titanium nitride or tantalum nitride can be used. For example, a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride contacts the insulating layer 101 and the insulating layer 103a, and tantalum nitride contacts the semiconductor layer 113a. With this structure, excessive oxidation of the conductive layer 111a by the semiconductor layer 113a can be suppressed. In addition, when an oxide insulator is used for the insulating layer 101 and the insulating layer 103a, the insulating layer can suppress excessive oxidation of the conductive layer 111a. Alternatively, the conductive layer 111a may be a structure in which tungsten is stacked on titanium nitride, for example.

In addition, since the conductive layer 111a has a region in contact with the semiconductor layer 113a, it is preferable to use a conductive material containing oxygen described in the section on [Conductor] described later. By using a conductive material containing oxygen as the conductive layer 111a, the conductive layer 111a can maintain conductivity even if it absorbs oxygen. As the conductive layer 111a, for example, indium tin oxide (also referred to as ITO), indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used in a single layer or a stacked layer.

Although Figures 5B, 5C, 7A, etc. show a configuration in which the upper surface of the conductive layer 111a is flat, the present invention is not limited to this. For example, a configuration in which a recess overlapping the opening 121a is formed on the upper surface of the conductive layer 111a may be used. By forming at least a portion of the semiconductor layer 113a, the insulating layer 105a, and the conductive layer 115a so as to fill the recess, it is possible to easily apply the gate electric field of the conductive layer 115a up to the vicinity of the conductive layer 111a of the semiconductor layer 113a.

Similarly, the upper surface of the conductive layer 115a does not necessarily need to be flat. For example, the upper surface of the conductive layer 115a may be configured to have a recess that overlaps with the opening 121b. By configuring the semiconductor layer 113b, the insulating layer 105b, and at least a portion of the conductive layer 115b to fill the recess, it is possible to easily apply the gate electric field of the conductive layer 115b up to the vicinity of the conductive layer 115a of the semiconductor layer 113b.

The conductive layer 112 (conductive layer 112a, conductive layer 112b) can be a single layer or a stack of conductors described in the section [Conductors] below. For example, the conductive layer 112 can be a conductive material with high conductivity, such as tungsten, aluminum, or copper.

As with the conductive layer 111a and the conductive layer 115, the conductive layer 112 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen. For example, titanium nitride or tantalum nitride can be used. With such a structure, the conductive layer 112 can be prevented from being excessively oxidized by the semiconductor layer 113. As with the conductive layer 115, the conductive layer 112 may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

Also, for example, a structure in which tungsten is laminated on titanium nitride may be used. By providing tungsten in a laminated form in this manner, the conductivity of the conductive layer 112 can be improved.

In addition, when the conductive layer 112 is configured by stacking a first conductive layer and a second conductive layer, for example, the first conductive layer may be formed using a conductive material with high conductivity, and the second conductive layer may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductive layer, the area of which in contact with the insulating layer 105 is larger than that of the first conductive layer, it is possible to prevent oxygen in the insulating layer 105 from diffusing into the first conductive layer of the conductive layer 112. For example, it is preferable to use tungsten as the first conductive layer of the conductive layer 112, and indium tin oxide with added silicon as the second conductive layer of the conductive layer 112.

When the semiconductor layer 113a contacts the conductive layer 111a (or the semiconductor layer 113b contacts the conductive layer 115a), a metal compound or oxygen deficiency is formed in the semiconductor layer 113 (semiconductor layer 113a, semiconductor layer 113b), and the region 113na of the semiconductor layer 113 has a low resistance. When the semiconductor layer 113a contacts the conductive layer 111a (or the semiconductor layer 113b contacts the conductive layer 115a) has a low resistance, the contact resistance between the semiconductor layer 113a and the conductive layer 111a (or the contact resistance between the semiconductor layer 113b and the conductive layer 115a) can be reduced. Similarly, when the semiconductor layer 113 contacts the conductive layer 112, the region 113nb of the semiconductor layer 113 has a low resistance. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

The insulating layer 101 and insulating layer 103 (insulating layer 103a, insulating layer 103b) that function as interlayer insulating layers preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating layer, the parasitic capacitance that occurs between wirings can be reduced. For the insulating layer 101 and insulating layer 103, a single layer or a stack of insulators containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Furthermore, it is preferable that the concentrations of impurities such as water and hydrogen in the insulating layer 101 and the insulating layer 103 are reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113.

In addition, the insulating layer 103 disposed in the vicinity of the channel formation region of the semiconductor layer 113 preferably contains oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen). By performing heat treatment on the insulating layer 103 containing excess oxygen, oxygen can be supplied from the insulating layer 103 to the channel formation region of the semiconductor layer 113, and oxygen vacancies in the semiconductor layer 113 and defects in which hydrogen has entered the oxygen vacancies (hereinafter, may be referred to as _VOH ) can be reduced. This makes it possible to stabilize the electrical characteristics of the transistor and improve its reliability.

Also, as the insulating layer 103, an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below, may be used. With such a structure, hydrogen in the semiconductor layer 113 can be captured or fixed, and the hydrogen concentration in the semiconductor layer 113 can be reduced. As the insulating layer 103, magnesium oxide, aluminum oxide, or the like can be used.

Note that although the insulating layer 103 is shown as a single layer in Figures 5B, 5C, 7A, etc., the present invention is not limited to this. The insulating layer 103 may have a laminated structure.

For the insulating layer 107 (insulating layer 107a, insulating layer 107b), it is preferable to use an insulator having barrier properties against hydrogen, as described in the section on [Insulator] below. This makes it possible to suppress the diffusion of hydrogen from outside the transistor through the insulating layer 105 to the semiconductor layer 113. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 107.

Furthermore, it is preferable to use an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below, as the insulating layer 107. With such a structure, it is possible to suppress diffusion of hydrogen from above the insulating layer 107 to the semiconductor layer 113, and further to capture or fix hydrogen in the semiconductor layer 113, thereby reducing the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as the insulating layer 107. Furthermore, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 107.

5B, 5C, 7A, etc., the configuration in which the insulating layer 107 is formed on the upper surface of the transistor is illustrated, but the present invention is not limited to this. For example, the insulating layer 107 or an insulating layer having a similar function or material to the insulating layer 107 may be formed on the side and bottom surfaces of the transistor, and the transistor may be surrounded by the insulating layer 107. Alternatively, the insulating layer 107 may be formed on the upper, side, and bottom surfaces of the transistor 41 and the transistor 42, and the transistor 41 and the transistor 42 may be surrounded by the insulating layer 107. With this configuration, impurities (e.g., water, hydrogen, etc.) can be prevented from entering the inside of the transistor 41 and the transistor 42.

Below, we will explain the components of the capacity (capacity 51) of a storage device according to one embodiment of the present invention.

[Capacity components]
A single layer or a stack of conductors described in the section [Conductor] below can be used as the conductive layer 115a and the conductive layer 141. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, can be used as the conductive layer 115a and the conductive layer 141. By using such a conductive material with high conductivity, the conductivity of the conductive layer 115a and the conductive layer 141 can be improved.

The conductive layer 115a and the conductive layer 141 are preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, and are used in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide to which silicon is added may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide insulator is used for the insulating layer 135, the conductive layer 115a can be suppressed from being oxidized by the insulating layer 135. Furthermore, when an oxide insulator is used for the insulating layer 103b, the conductive layer 141 can be suppressed from being oxidized by the insulating layer 103b. Furthermore, as the conductive layer 115a and the conductive layer 141, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

For the insulating layer 107a, it is preferable to use an insulator having the above-mentioned barrier properties against hydrogen. It is also preferable to use an insulator having the above-mentioned function of capturing hydrogen or fixing hydrogen.

For the insulating layer 135, it is preferable to use a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below. By using a high-k material for the insulating layer 135, the insulating layer 135 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 51 can be sufficiently ensured.

The insulating layer 135 is preferably made of a laminated insulator made of a high-k material, and preferably has a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 135 may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, the insulating film may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, the insulating film may be made of an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 51 can be suppressed.

Also, a material that may have ferroelectricity may be used as the insulating layer 135. Examples of materials that may have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO _x (X is a real number greater than 0). Examples of materials that may have ferroelectricity include a material obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 is set to 1:1 or close thereto. Examples of materials that may have ferroelectricity include a material obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, to be 1: 1 or close to 1. As a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate (PbTiO _x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may be used.

Also, examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, and indium. Also, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2. Also, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride. Also, element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

Furthermore, examples of materials that may have ferroelectric properties include perovskite-type oxynitrides such as SrTaO ₂ N and BaTaO ₂ N, and GaFeO ₃ having a κ-alumina structure.

In the above explanation, metal oxides and metal nitrides are given as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

Also, as a material that can have ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Or, the insulating layer 135 can have a laminated structure made of multiple materials selected from the materials listed above. However, for example, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity or materials that cause ferroelectricity to be obtained.

Metal oxides containing one or both of hafnium and zirconium are preferable because they can have ferroelectricity even when processed into a thin film of a few nm. Here, the film thickness of the insulating layer 135 can be, for example, 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, the film thickness is preferably 8 nm to 12 nm. By making the ferroelectric layer thin, the capacitor 51 can be combined with a semiconductor element such as a miniaturized transistor to form a memory device. In this specification, etc., a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification, etc.

Alternatively, a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area. For example, even if the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ² or less, 10 μm ² or less, 1 μm ² or less, or 0.1 μm ² or less, it can have ferroelectricity. Also, even if it is 10,000 nm ² or less, or 1,000 nm ² or less, it may have ferroelectricity. By making the ferroelectric layer small in area, the occupied area of the capacitor 51 can be reduced.

In addition, in a metal oxide having one or both of hafnium and zirconium, the higher the oxygen vacancy (V _{2 O 3} ) concentration in the metal oxide, the more likely it is that a crystal having a cubic crystal structure will be generated. Therefore, it is preferable that an element that increases the oxygen vacancy concentration in the metal oxide is added to the metal oxide having one or both of hafnium and zirconium. As the element, there is a Group 3 element (also called Group IIIa element) in the periodic table. The Group 3 element in the periodic table added to the metal oxide is more preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium. In addition, in the present specification, the Group 3 element in the periodic table may be simply called the Group 3 element.

A ferroelectric material is an insulator that is polarized when an electric field is applied from the outside, and has the property that the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory) or a ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance 51, the memory device shown in this embodiment functions as a ferroelectric memory.

Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer by an external electric field. It is also presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer 135 to manifest ferroelectricity, the insulating layer 135 must contain crystals. In particular, it is preferable for the insulating layer 135 to contain crystals having an orthorhombic crystal structure, since ferroelectricity is manifested. The crystal structure of the crystals contained in the insulating layer 135 may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. The insulating layer 135 may have an amorphous structure. In this case, the insulating layer 135 may be a composite structure having an amorphous structure and a crystalline structure.

As mentioned above, it is preferable that the insulating layer 103b has a low dielectric constant. This makes it possible to reduce the parasitic capacitance that occurs between wiring. For the insulating layer 103b, a single layer or a multilayer of insulators containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

<Materials of the memory device>
Constituent materials that can be used for the memory device of one embodiment of the present invention are described below.

[substrate]
The substrate on which the transistor 41, the transistor 42, and the capacitor 51 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there is a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Alternatively, substrates in which elements are provided on these substrates may be used.

[Insulator]
Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

For example, as transistors become more miniaturized and highly integrated, problems such as leakage currents can occur due to thinner gate insulating layers. By using high-k materials for the insulator that functions as the gate insulating layer, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer insulating layer, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator. Note that materials with a low dielectric constant also have high dielectric strength.

Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen. Silicon oxide may be formed using an organic silane such as tetraethoxysilane (TEOS).

In addition, the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities and oxygen. As an insulator that has a function of suppressing the permeation of impurities and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator that has a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

Insulators such as a gate insulating layer that are in contact with a semiconductor or that are provided near the semiconductor layer are preferably insulators that have a region containing excess oxygen. For example, by providing an insulator that has a region containing excess oxygen in contact with the semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.

Insulators that have a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, or gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. In addition, oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

Other examples of insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.

Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but crystalline regions may be formed in some parts.

In this specification and the like, a barrier insulating film refers to an insulating film having a barrier property. The barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance). The function of capturing or fixing a corresponding substance (also referred to as gettering) can be rephrased as a barrier property. Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁻ . In addition, impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO ₂ , etc.), a copper atom, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom and an oxygen molecule. Specifically, the barrier property against oxygen refers to a property that makes it difficult for at least one of oxygen atoms and oxygen molecules to diffuse.

[conductor]
As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed. In addition, examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, conductive materials containing oxygen may be referred to as oxide conductors.

In addition, conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

Furthermore, multiple conductors made of the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

When a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed in from an external insulator, etc.

[Metal oxide]
Metal oxides may have lattice defects. Examples of lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Factors that cause the generation of lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.

When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.

In a transistor using a metal oxide, particularly when oxygen vacancies (V _O ) and impurities are present in the channel formation region in the metal oxide, the electrical characteristics may easily fluctuate and the reliability may be deteriorated. In addition, hydrogen near the oxygen vacancies may form V _O H and generate electrons that become carriers. For this reason, when oxygen vacancies are present in the channel formation region in the metal oxide, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

The types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.

Metal oxide structures are divided into single crystal structures and other structures (non-single crystal structures). Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like: amorphous-like) structures, and amorphous structures. A-like structures have a structure between the nc structure and the amorphous structure.

Also, metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Also, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

Moreover, it is preferable to use a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce the scattering factor that contributes to the transmission of carriers. Note that carriers flow from the source to the drain via the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, it is possible to increase the on-state current of the transistor.

Here, it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, it is preferable for the crystal to have a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS.

Furthermore, it is preferable that the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.

For example, the three-layered crystal structure described above will have the following structure. The first layer has an atomic coordination structure in the form of an octahedron of oxygen with the metal of the first layer at the center. The second layer has an atomic coordination structure in the form of a trigonal bipyramid or tetrahedron of oxygen with the metal of the second layer at the center. The third layer has an atomic coordination structure in the form of a trigonal bipyramid or tetrahedron of oxygen with the metal of the third layer at the center.

Examples of the crystal structure of the above crystal include a YbFe ₂ O ₄ type structure, a Yb ₂ Fe ₃ O ₇ type structure, and modified structures thereof.

Furthermore, each of the first to third layers is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen. Note that the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer. The first layer and the second layer may have the same metal element. Also, it is preferable that the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.

The above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.

Examples of the metal oxide of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

Metal oxides according to one embodiment of the present invention include, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium Aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.

In addition, the metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field effect mobility of the transistor may be increased. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

The metal oxide may also contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

In addition, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor, and increases its reliability.

In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, carrier generation caused by oxygen vacancies is suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

In addition, by increasing the ratio of the number of In atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the transistor can obtain a large on-current and high frequency characteristics.

In this embodiment, In-Ga-Zn oxide may be used as an example of a metal oxide.

To form a metal oxide having the above-mentioned layered crystal structure, it is preferable to deposit atoms one layer at a time. By using the ALD method, it is easy to form a metal oxide having the above-mentioned layered crystal structure.

Examples of the ALD method include the Thermal ALD method, in which the reaction between the precursor and reactant is carried out using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, in which a plasma-excited reactant is used.

The ALD method can deposit atoms one layer at a time, which allows for the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with fewer defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures. The PEALD method can be preferable in some cases because it uses plasma, which allows for the formation of films at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.

When using the ALD method to form metal oxide films, the amount of carbon and chlorine contained in the film can be reduced by adopting a condition in which the substrate temperature is high during film formation and/or by carrying out an impurity removal process, compared to when the ALD method is used without applying these methods.

For example, it is preferable to perform an impurity removal process intermittently in an oxygen-containing atmosphere during the formation of the metal oxide film. It is also preferable to perform an impurity removal process in an oxygen-containing atmosphere after the formation of the metal oxide film. By performing an impurity removal process either during or after the formation of the metal oxide film, impurities in the film can be removed. This makes it possible to prevent impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, it is possible to reduce the impurity concentration in the metal oxide. It is also possible to increase the crystallinity of the metal oxide.

Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

When performing plasma treatment or microwave treatment, it is preferable to set the substrate temperature to, for example, room temperature (e.g., 25°C) or higher and 500°C or lower, 100°C or higher and 450°C or lower, 200°C or higher and 450°C or lower, 300°C or higher and 450°C or lower, or 400°C or higher and 450°C or lower. It is also preferable to set the heat treatment temperature to, for example, 100°C or higher and 500°C or lower, 200°C or higher and 450°C or lower, 300°C or higher and 450°C or lower, or 400°C or higher and 450°C or lower.

The temperature during the impurity removal process is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or memory device, in particular, because the impurity content in the metal oxide can be reduced without reducing productivity. For example, the productivity of the memory device can be increased by setting the maximum temperature in the manufacturing process of a memory device according to one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

Here, microwave processing refers to processing using, for example, a device with a power source that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less.

In the microwave processing, it is preferable to use a microwave processing device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably, for example, 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves in the microwave processing device is preferably, for example, 1000 W to 10,000 W, and preferably 2000 W to 5,000 W. In addition, the microwave processing device may have a power source that applies RF to the substrate side. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the film.

The microwave treatment is preferably carried out under reduced pressure, and the pressure is, for example, preferably from 10 Pa to 1000 Pa, and more preferably from 300 Pa to 700 Pa. The treatment temperature is, for example, preferably from room temperature (25°C) to 750°C, more preferably from 300°C to 500°C, and even more preferably from 400°C to 450°C.

Furthermore, after the microwave treatment or plasma treatment, a heat treatment may be performed continuously without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

The microwave treatment can be performed using, for example, oxygen gas and argon gas. Here, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 10% and less than 40%. Even more preferably, the oxygen flow ratio ( _O2 /( _O2 +Ar)) is greater than 10% and less than 30%.

The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas concentration to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed. The heat treatment may be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).

By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as _CO2 and CO, and hydrogen in the metal oxide can be released as _H2O . Furthermore, at the same time as removing the impurities, rearrangement of metal atoms and oxygen atoms can be carried out, improving crystallinity. Therefore, a metal oxide having a highly crystalline layered crystal structure, particularly a metal oxide having the above CAAC structure, can be formed.

The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio, for example. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed. For example, a method can be used in which a first metal oxide is formed by using a sputtering method, and a second metal oxide is formed on the first metal oxide by using an ALD method. For example, if the first metal oxide has a crystal part, the second metal oxide may grow as a crystal from the crystal part as a nucleus.

The ALD method can control the composition of the resulting film by the amount of raw material gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of times it is introduced (also called the number of pulses), and the time required for one pulse (also called the pulse time). Also, for example, the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices can be increased in some cases.

[Transistors with Metal Oxides]
Next, a case where a metal oxide (oxide semiconductor) is used for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer will be referred to as an OS transistor, and a transistor using silicon for a semiconductor layer will be referred to as a Si transistor.

By using a metal oxide (oxide semiconductor) according to one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

An oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 ¹⁸ cm ⁻³ or less, preferably 1×10 ¹⁷ cm ⁻³ or less, more preferably 1×10 ¹⁵ cm ⁻³ or less, more preferably 1×10 ¹³ cm ⁻³ or less, more preferably 1×10 ¹¹ cm ⁻³ or less, and further preferably less than 1×10 ¹⁰ cm ⁻³ and 1×10 ⁻⁹ cm ⁻³ or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, it is preferable to lower the impurity concentration in the oxide semiconductor film and to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.

In addition, the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a larger band gap than silicon, the off-state current (also referred to as Ioff) of a transistor can be reduced.

Furthermore, in Si transistors, as transistors are miniaturized, a short channel effect (also referred to as SCE) occurs. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.

The short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

Furthermore, the characteristic length is widely used as an index of resistance to short channel effects. Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.

OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.

Even when the carrier concentration of the oxide semiconductor is reduced to the extent that the channel formation region becomes i-type or substantially i-type, the conduction band bottom of the channel formation region in a short-channel transistor is lowered due to the Conduction-Band-Lowering (CBL) effect, so that the energy difference between the conduction band bottom between the source region or drain region and the channel formation region can be reduced to 0.1 eV to 0.2 eV. Thus, the OS transistor can also be regarded as having an n ⁺ ^/ n − /n + accumulation-type junction-less transistor structure or an n ⁺ /n ⁻ /n ⁺ accumulation-type non-junction transistor structure in which the channel formation region is an ⁿ − type region and the source region and drain region are n ⁺ ^type regions.

By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a memory device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of an OS transistor is 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 10 nm, 5 nm to 7 nm, or 5 nm to 6 nm. On the other hand, it may be difficult to achieve a gate length of 20 nm or less or 15 nm or less in a Si transistor because of the short channel effect. Therefore, an OS transistor can be preferably used as a transistor with a short channel length compared to a Si transistor. Note that the gate length is the length of a gate electrode in a direction in which carriers move inside a channel formation region when the transistor is operating.

Furthermore, miniaturization of the OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.

As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.

[Impurities in metal oxides]
Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and further preferably 1×10 ¹⁸ atoms/cm ³ or less. The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 3×10 ¹⁸ atoms/cm ³ or less, and still more preferably 1×10 ¹⁸ atoms/cm ³ or less.

Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, a trap state may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, more preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ^{3 or} less, and further preferably 5×10 ¹⁷ atoms/cm ³ or less.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, an electron serving as a carrier may be generated. In addition, some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 5×10 ¹⁹ atoms/cm ³ , more preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , and further preferably less than 1×10 ¹⁸ atoms/cm ³ .

In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be achieved.

[Other semiconductor materials]
The semiconductor layer 113 can be rephrased as a semiconductor layer including a channel formation region of a transistor. A semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as the semiconductor. For example, a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material.

In this specification and the like, layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

Silicon and germanium are examples of elemental semiconductors that can be used in the semiconductor material. Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. The boron nitride that can be used for the semiconductor layer preferably contains an amorphous structure. The boron arsenide that can be used for the semiconductor layer preferably contains crystals with a cubic structure.

Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In the layered material boron carbonitride, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

As the semiconductor layer, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS ₂ ), molybdenum selenide (representatively MoSe ₂ ), molybdenum tellurium (representatively MoTe ₂ ), tungsten sulfide (representatively WS ₂ ), tungsten selenide (representatively WSe ₂ ), tungsten tellurium (representatively WTe ₂ ), hafnium sulfide (representatively HfS ₂ ), hafnium selenide (representatively HfSe ₂ ), zirconium sulfide (representatively ZrS ₂ ), and zirconium selenide (representatively ZrSe ₂ ). By applying the above-mentioned transition metal chalcogenide to the semiconductor layer, a transistor with a large on-current can be provided.

<Operation Example of Semiconductor Device 710>
FIG. 12 is a timing chart illustrating an example of the operation of the semiconductor device 710 shown in FIG.

In the following explanation of the operation, it is assumed that the wiring VPRE is supplied with (potential VDD - potential VSS)/2. It is also assumed that the wiring VPRE2 is supplied with a potential (for example, potential VDD) that exceeds (potential VDD - potential VSS)/2 but does not exceed potential VDD. It is also assumed that the wiring CL is supplied with an arbitrary fixed potential (for example, potential VSS).

The timing chart shown in FIG. 12 shows the state (potential H or potential L) of the signal applied to each of wiring WWL, wiring RWL, wiring SW4, wiring SW5, wiring EQ, wiring EQB, and wiring CSEL during each period of operation (periods T721 to T725). It also shows the potential applied to each of wiring SAP and wiring SAN. It also shows the change in the potential of each of wiring MN, wiring RBL, wiring RBLB, and wiring WBL when reading and writing data "1" (data 1) and when reading and writing data "0" (data 0).

Periods T721 to T724 are periods during which data is read. Period T725 is a period during which data is written.

Just before the period T721, a potential L is applied to the wiring WWL and a potential H is applied to the wiring RWL. A potential H is applied to each of the wirings SW4 and SW5. A potential H is applied to the wiring EQ and a potential L is applied to the wiring EQB. A potential L is applied to the wiring CSEL. A potential VDD-potential VSS)/2 is applied to each of the wirings SAP and SAN. At this time, the wirings RBL and RBLB are each precharged to (potential VDD-potential VSS)/2. A potential VDD (potential corresponding to data "1") or a potential VSS (potential corresponding to data "0") is held in the wiring MN of the memory cell 741. In the following description, unless otherwise specified, the previous state is maintained.

In period T721, a potential L is applied to the wiring EQ, and a potential H is applied to the wiring EQB. Then, precharging of the wirings RBL and RBLB stops. Therefore, the wirings RBL and RBLB each become floating.

In period T722, a potential L is applied to wiring SW4. Then, wiring RBL is precharged to the potential applied to wiring VPRE2. In other words, the potential of wiring RBL becomes higher than the potential of wiring RBLB.

In period T723, a potential H is applied to wiring SW4. Then, precharging of wiring RBL stops. Then, a potential L is applied to wiring RWL. Then, the potential of wiring RBL changes according to the potential of wiring MN. Therefore, wiring MN can be converted into a potential difference between wiring RBL and wiring RBLB.

Specifically, for example, when the data stored in memory cell 741 is "1" (i.e., wiring MN holds potential VDD), transistor M702 in memory cell 741 becomes conductive and current flows from wiring RBL to wiring RWL, so that the potential of wiring RBL becomes lower than the potential of wiring RBLB. Alternatively, for example, when the data stored in memory cell 741 is "0" (i.e., wiring MN holds potential VSS), transistor M702 in memory cell 741 becomes non-conductive and no current flows from wiring RBL to wiring RWL, so that the potential of wiring RBL becomes higher than the potential of wiring RBLB.

In period T724, a potential H is applied to the wiring RWL. After that, a potential VSS is applied to the wiring SAN, and a potential VDD is applied to the wiring SAP. Then, the amplifier circuit 755 operates to amplify the potential difference between the wiring RBL and the wiring RBLB that occurs due to the operation of the above-mentioned period T723. As a result, the potentials of the wirings RBL and RBLB are determined to be either the potential VDD or the potential VSS. In other words, reading of the data stored in the memory cell 741 is completed.

Specifically, for example, when the data stored in memory cell 741 is "1", the potential of wiring RBL becomes potential VSS, and the potential of wiring RBLB becomes potential VDD. Or, for example, when the data stored in memory cell 741 is "0", the potential of wiring RBL becomes potential VDD, and the potential of wiring RBLB becomes potential VSS.

In period T725, a potential H is applied to the wiring WWL. Then, the potential VDD or potential VSS of the wiring WBL is applied to the wiring MN. After that, a potential L is applied to the wiring WWL, and writing of data to the memory cell 741 is completed.

Note that in the semiconductor device 710 shown in FIG. 11, for example, the wiring WBL and the wiring RBL may be electrically connected via a switch. Or, for example, the wiring WBL and the wiring RBLB may be electrically connected via a switch. With such a configuration, for example, when writing data to the memory cell 741, a potential VDD or a potential VSS can be applied from the sense circuit 751 to the wiring WBL via the switch. For example, a transistor provided in the layer 983 or a transistor provided in the layer 985 can be used as the switch.

<Storage Devices That Can Be Used for the Storage Unit 920>
A memory device 720 of one embodiment of the present invention will be described. At least a part of the semiconductor device 710 described above can be used for the memory device 720. At least a part of the memory device 720 can be used for, for example, the computer 900 illustrated in FIG. 1A or the like. For example, the memory device 720 can be used for the memory unit 920.

FIG. 13 is a block diagram illustrating an example configuration of the storage device 720.

The memory device 720 shown in FIG. 13 has a memory array 721 and a drive circuit 722.

As one aspect of the present invention, when the memory device 720 is used as the memory unit 920 of the electronic computer 900 described above, for example, the memory array 721 corresponds to the memory array unit 921, and the drive circuit 722 corresponds to the control unit 922.

The memory array 721 has a plurality of sense circuits 751 and a plurality of memory cells 741.

As one aspect of the present invention, as described above, the sense circuit 751 is arranged in layer 985, and the memory cells 741 are arranged in layers 984[1] to 984[K].

The multiple memory cells 741 are arranged in a three-dimensional matrix of K layers x M rows x N columns (K, M, and N are each an integer greater than or equal to 1).

In FIG. 13, as representative examples, memory cell 741[1,1,1] in the first row and first column of the first layer, memory cell 741[1,1,N] in the first row and N column of the first layer, memory cell 741[1,M,1] in the first row and M column of the first layer, memory cell 741[K,1,1] in the first row and first column of the K layer, memory cell 741[K,1,N] in the first row and N column of the K layer, memory cell 741[K,M,1] in the first column of the M row of the K layer, and memory cell 741[K,M,N] in the M row and N column of the K layer.

The diagram also shows wiring WL[1,1] electrically connected to N memory cells 741 in the first row of the first layer, wiring WL[1,M] electrically connected to N memory cells 741 in the Mth row of the first layer, wiring WL[K,1] electrically connected to N memory cells 741 in the first row of the Kth layer, and wiring WL[K,M] electrically connected to N memory cells 741 in the Mth row of the Kth layer.

The drive circuit 722 has a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 has a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

As one embodiment of the present invention, for example, the driver circuit 722 is disposed in the layer 985. Therefore, for example, a Si transistor can be used for the driver circuit 722. Note that at least a part of the driver circuit 722 can also be disposed in the layer 983 and the layers 984[1] to 984[K]. Therefore, a planar OS transistor and a vertical OS transistor can also be used for at least a part of the driver circuit 722.

For example, a signal is provided to each of terminals BW, CE, GW, MCK, WAKE, ADDR, WDA, PON1, and PON2 from outside the storage device 720. Also, for example, a signal is output from terminal RDA to outside the storage device 720.

For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. Note that the signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

The control circuit 772 has a function of controlling the operation of the memory device 720. The control circuit 772 has a function of, for example, performing a logical operation on the signals provided to each of the terminals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device 720. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the corresponding operation mode is executed.

The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the drive circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal given to the terminal MCK in response to a signal given to the terminal WAKE. For example, a signal is given to the terminal WAKE that controls whether or not the clock signal given to the terminal MCK is input to the voltage generation circuit 773.

The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 741. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 741 and the sense circuit 751, for example. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

The row decoder 782 and column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying the row to be accessed. It also has the function of specifying the layer to be accessed. The column decoder 784 has the function of specifying the column to be accessed. The row driver 783 has the function of selecting the row and layer specified by the row decoder 782, and providing the desired signal to, for example, the corresponding memory cell 741 and the sense circuit 751. The column driver 785 has the function of selecting the column specified by the column decoder 784, and providing the desired signal to, for example, the corresponding sense circuit 751.

The data driver 786 has a function of writing and reading data to and from the memory cells 741 selected by the row driver and column driver. The input circuit 787 has a function of holding data provided to the terminal WDA from outside the memory device 720. The data held in the input circuit 787 (data Din) is written to the memory cells 741 via the data driver 786. The data stored in the memory cells 741 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read data (data Dout). It also has a function of outputting the held data from the terminal RDA to outside the memory device 720.

The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, the terminal VMD is supplied with a high power supply potential (for example, potential VDD) for operating the drive circuit 722, and the terminal VMS is supplied with a low power supply potential (for example, potential VSS). Also, for example, the terminal VMH is supplied with a high power supply potential (for example, potential H) for operating the memory cell 741 and the sense circuit 751, etc. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

In addition, in the drive circuit 722, each circuit and each terminal can be appropriately selected or removed as needed. In addition, other circuits and other terminals can be added as needed.

FIG. 14A is a circuit diagram of a memory unit 717 having one sub-sense circuit 736, multiple memory cells 741, and wiring LBL.

In the memory unit 717, P (P is an integer equal to or greater than 1) memory cells 741 are arranged in each of the K layers, ie, layers 984[1] to 984[K]. That is, the memory unit 717 has K×P memory cells 741.

FIG. 14A shows, as representative examples, memory cell 741[1,1] and memory cell 741[1,P] arranged in the first layer (layer 984[1]), and memory cell 741[K,1] and memory cell 741[K,P] arranged in the Kth layer (layer 984[K]).

FIG. 14B is a circuit diagram of a memory block 718 having one sense circuit 751, one switch circuit 737, multiple memory units 717, wiring GBL, wiring GBLB, wiring SA_GBL, and wiring SA_GBLB. Here, the memory block 718 corresponds to the semiconductor device 710 described above.

In memory block 718, Q memory units 717 (Q is an even number equal to or greater than 2) are arranged. That is, memory block 718 has K x P x Q memory cells 741.

FIG. 14B shows, as representative examples, memory unit 717[1] and memory unit 717[Q/2] electrically connected to wiring GBL, and memory unit 717[Q/2+1] and memory unit 717[Q] electrically connected to wiring GBLB.

FIG. 15 is a schematic diagram illustrating an example of the arrangement of each component of the memory device 720.

In the memory device 720 shown in FIG. 15, the memory array 721 has R (R is an integer equal to or greater than 1) memory subarrays 723 arranged in the column direction (X direction), and each memory subarray 723 has N memory blocks 718 arranged in the row direction (Y direction). That is, the memory array 721 has R×N memory blocks 718.

In FIG. 15, three memory subarrays 723 are shown as representatives, two of which (memory subarray 723[1] and memory subarray 723[R]) are shown surrounded by dashed lines. In addition, two memory blocks 718 (memory block 718[1] and memory block 718[N]) are shown as representatives surrounded by dashed lines.

As described above, the memory array 721 has R×N memory blocks 718 (R rows×N columns). Furthermore, the memory blocks 718 have K×P×Q memory cells 741 (K layers×(P×Q rows)). In other words, the memory device 720 has K×P×Q×R×N memory cells 741 arranged in a three-dimensional matrix of K layers×M rows (P×Q×R rows)×N columns in the memory array 721. Furthermore, since the memory device 720 has R×N sense circuits 751, the data stored in the memory array 721 can be read out in a super-parallel manner by simultaneously accessing multiple sense circuits 751.

In addition, in the memory device 720, a word line driver 724, a column driver 725, a sense amplifier driver 726, a data driver 727, and a memory controller 728 are arranged in a layer 985 around the memory array 721.

Here, for example, the word line driver 724 and the sense amplifier driver 726 correspond to the row driver 783, the column driver 725 corresponds to the column driver 785, the data driver 727 corresponds to the data driver 786, the input circuit 787, and the output circuit 788, and the memory controller 728 corresponds to the control circuit 772 and the voltage generation circuit 773.

Although not shown, the memory device 720 may have a layer selection driver disposed in layer 983 above the word line driver 724 and in layers 984[1] to 984[K]. The layer selection driver may have the function of providing a signal generated by the word line driver 724 to any layer.

In the above description of the semiconductor device according to one embodiment of the present invention, the OS transistor is a semiconductor element having three terminals, namely, a gate (first gate), a source, and a drain. However, by having a back gate (second gate), the OS transistor may have four terminals. When the OS transistor has a back gate, for example, the on-resistance can be reduced (on-current can be increased) by applying the same potential as the gate to the back gate. For example, applying the same potential as the source to the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region, so that the electrical characteristics can be stabilized and the reliability can be improved. For example, applying an arbitrary potential to the back gate can change the threshold voltage. For example, the current flowing between the source and drain can be independently controlled depending on the potentials applied to the gate and back gate.

In addition, in the above-mentioned description of the operation example of the semiconductor device, when the potential changes, for example, a rise time and a fall time may occur due to a load (parasitic capacitance and parasitic resistance) such as wiring. The time is, for example, more than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond. Even if two different operations are shown to have the same timing, for example, this does not necessarily mean that they have the same timing in the strict sense. For example, even if there is a slight time difference due to signal delay in wiring, it may be considered that they have the same timing. The time difference is, for example, more than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond.

Furthermore, the potential H or potential L applied to each of the multiple wirings does not have to be the same potential for each wiring. For example, taking into consideration the threshold voltage of the transistor to which the potential is applied, the potential may be different for each wiring. Note that the potential H or potential L applied to each wiring may include, for example, a decrease in potential due to the threshold voltage of the transistor.

In addition, even if each period is shown in the timing chart as having the same length, the length of each period may be different. In other words, when actually operating the semiconductor device, the length of each period can be set appropriately.

The electronic computer, semiconductor device, and memory device according to one embodiment of the present invention are not limited to the above description. At least a part of the configuration examples and operation examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples, operation examples, other drawings, and other embodiments described in this specification.

<Semiconductor device that can be used for the processing section 910>
A semiconductor device 810 according to one embodiment of the present invention will be described. At least a part of the semiconductor device 810 can be used for, for example, the electronic computer 900 illustrated in FIG. 1A or the like. For example, the semiconductor device can be used for the register unit 914 included in the processing unit 910.

[Configuration example]
FIG. 16 is a circuit diagram illustrating an example of the configuration of a semiconductor device 810. As shown in FIG.

The semiconductor device 810 shown in FIG. 16 has a scan flip-flop circuit 850 and a backup circuit 830.

As one aspect of the present invention, when the semiconductor device 810 is used in the register unit 914 of the electronic computer 900 described above, for example, the scan flip-flop circuit 850 corresponds to the scan flip-flop 915, and the backup circuit 830 corresponds to the backup memory 916. That is, for example, the scan flip-flop circuit 850 is arranged in the layer 985, and the backup circuit 830 is arranged in the layer 983. Therefore, for example, a Si transistor can be used for the scan flip-flop circuit 850, and an OS transistor can be used for the backup circuit 830.

The scan flip-flop circuit 850 has a selector circuit 851 and a flip-flop circuit 852. The backup circuit 830 has holding circuits 831[1] to 831[G] (G is an integer of 2 or more) and a transistor M801. Each of the holding circuits 831[1] to 831[G] has a transistor M802, a transistor M803, and a capacitance C801.

Various signals that control the operation of the semiconductor device 810 are applied to wirings BK[1] to BK[G], wirings RV[1] to RV[G], wiring SE, wiring PCK, and wiring GBK.

The semiconductor device 810 can store and hold data input from the wiring D or data input from the wiring SD in the flip-flop circuit 852 in the scan flip-flop circuit 850 in synchronization with a clock signal provided to the wiring PCK, and output the data to the wiring Q. The data held in the flip-flop circuit 852 is written to one of the holding circuits 831[1] to 831[G] in the backup circuit 830 via the wiring Q by a signal provided to the wiring BK[1] to wiring BK[G], and then held. Such an operation may be called, for example, save, evacuation, store, or backup. The data held in one of the holding circuits 831[1] to 831[G] is written back to the flip-flop circuit 852 via the wiring SD by a signal provided to the wiring RV[1] to wiring RV[G], and then held. Such an operation may be called, for example, load, return, restore, or recovery.

The flip-flop circuit 852 has a function of storing and holding data given to the input terminal Df in synchronization with a clock signal given to the wiring PCK, and outputting it from the output terminal Qf. For the flip-flop circuit 852, a flip-flop circuit provided in a standard circuit library can be used. For example, a positive edge trigger type D flip-flop can be used.

The selector circuit 851 has a function of transmitting data provided to the wiring D or the wiring SD to the flip-flop circuit 852 by a signal provided to the wiring SE. Data input from outside the semiconductor device 810 is provided to the wiring D. Data held in any one of the holding circuits 831[1] to 831[G] in the backup circuit 830 or data input from the wiring SD_IN is provided to the wiring SD_IN. Data for a scan test is provided to the wiring SD_IN.

When performing a power gating operation, the backup circuit 830 can hold the state of the scan flip-flop circuit 850 in one of the holding circuits 831[1] through 831[G]. In addition, when performing processing while switching between multiple tasks, the backup circuit 830 can hold the state of the scan flip-flop circuit 850 for each task in one-to-one correspondence with each of the holding circuits 831[1] through 831[G].

When the backup circuit 830 saves data, one of the holding circuits 831[1] to 831[G] is selected by a signal provided to the wirings BK[1] to BK[G]. When the backup circuit 830 loads data, one of the holding circuits 831[1] to 831[G] is selected by a signal provided to the wirings RV[1] to RV[G]. Signals are provided to the wirings BK[1] to BK[G] and the wirings RV[1] to RV[G], respectively, so that they correspond one-to-one to the holding circuits 831[1] to 831[G], respectively.

Note that the contents common to each of the holding circuits 831[1] to 831[G] may be described as the holding circuit 831. In that case, each of the wirings BK[1] to BK[G] may be described as the wiring BK, and each of the wirings RV[1] to RV[G] may be described as the wiring RV.

As shown in FIG. 16, the holding circuit 831 is electrically connected to each of the wiring Q and the wiring SD. In the holding circuit 831, the terminal (wiring) electrically connected to the wiring Q is the input terminal, and the terminal (wiring) electrically connected to the wiring SD is the output terminal. That is, in the semiconductor device 810, the output terminal Qf of the flip-flop circuit 852 is electrically connected to the input terminal of the holding circuit 831, and the input terminal Df of the flip-flop circuit 852 is electrically connected to the output terminal of the holding circuit 831 via the selector circuit 851.

In the holding circuit 831, one of the source and drain of the transistor M802 is electrically connected to one terminal of the capacitor C801. One of the source and drain of the transistor M803 is electrically connected to one terminal of the capacitor C801. The other terminal of the capacitor C801 is electrically connected to the wiring CM. The other of the source and drain of the transistor M802 is electrically connected to the input terminal of the holding circuit 831 (i.e., the wiring Q). The other of the source and drain of the transistor M803 is electrically connected to the output terminal of the holding circuit 831 (i.e., the wiring SD). The gate of the transistor M802 is electrically connected to the wiring BK. The gate of the transistor M803 is electrically connected to the wiring RV.

Note that in each of the holding circuits 831[1] to 831[G], the wirings through which one of the source or drain of the transistor M802, one of the source or drain of the transistor M803, and one terminal of the capacitor C801 are electrically connected to each other may be described as wirings SN[1] to SN[G]. Furthermore, when describing content common to each of the holding circuits 831[1] to 831[G], each of the wirings SN[1] to SN[G] may be described as wirings SN.

In the backup circuit 830, one of the source and drain of the transistor M801 is electrically connected to the wiring SD. The other of the source and drain of the transistor M801 is electrically connected to the wiring SD_IN.

The gate of transistor M801 is electrically connected to wiring GBK. A signal that controls whether or not to perform a scan test is provided to wiring GBK.

In one embodiment of the present invention, for example, OS transistors can be used as the transistors M801, M802, and M803. OS transistors have a characteristic of having an extremely low off-state current. In addition, even in a high-temperature environment, the off-state current hardly increases and the on-state current is not easily reduced.

As a result, the holding circuit 831 can hold the data written to the wiring SN for a long period of time by turning off the transistors M802 and M803. For example, the data can be held even when power is not supplied to the scan flip-flop circuit 850 due to the power gating operation. In other words, the holding circuit 831 can be used as a non-volatile memory.

In the semiconductor device 810, when data held in the wiring SN is written back to the flip-flop circuit 852, the potential of the data may change due to the parasitic capacitance of the wiring SD. Therefore, it is preferable to make the capacitance of the capacitor C801 larger than the parasitic capacitance of the wiring SD so that the amount of change in the potential of the data is smaller than the logical threshold value of the flip-flop circuit 852, for example.

As another example of the configuration of the semiconductor device 810, for example, a transistor M801 may be provided for each of the multiple holding circuits 831. Also, for example, a Si transistor may be used for the transistor M801.

In addition, in the semiconductor device 810, in order to increase the number of holding circuits 831 without increasing the area overhead, multiple layers 983 may be stacked and a backup circuit 830 may be provided in each layer 983.

In one embodiment of the present invention, the backup circuit 830 can be provided in the semiconductor device 810 without changing the circuit configuration and layout of the scan flip-flop circuit 850. In other words, the backup circuit 830 is a highly versatile circuit.

In addition, in the semiconductor device 810, the backup circuit 830 is stacked on top of the scan flip-flop circuit 850, so the distance of the wiring electrically connecting them can be shortened. This makes it possible to reduce the energy (access energy) required to save and load data. This makes it possible to reduce the power consumption of the semiconductor device 810.

[Operation example 1]
FIG. 17 is a timing chart for explaining an example of the operation of the semiconductor device 810 shown in FIG.

In this operation example 1, for example, an operation example of the semiconductor device 810 when performing a power gating operation in the electronic computer 900 described above will be described.

Here, as an example to explain the operation of the semiconductor device 810, the number of holding circuits 831 in the backup circuit 830 will be explained as four (G=4).

In the following explanation of the operation, the flip-flop circuit 852 stores data given to the input terminal Df and outputs the data from the output terminal Qf in synchronization with the timing (rising edge) at which the clock signal given to the wiring PCK switches from potential L to potential H. It is also assumed that a potential L is given to the wiring GBK. It is also assumed that a constant potential (for example, potential VSS) is given to the wiring CM.

The timing chart shown in FIG. 17 illustrates the state (potential H or potential L) of the signal provided to each of the wiring PCK, wiring BK[1], wiring RV[1], and wiring SE during each period of operation (periods T811 to T814). Note that wirings BK[2] to BK[4] and wirings RV[2] to RV[4] are not shown. The diagram also illustrates the state of data provided to each of the wirings D, Q, SD, and SN[1] (any one of data D1 to D3). Note that wirings SN[2] to SN[4] are not shown. The diagram also illustrates the state in which power is supplied to the scan flip-flop circuit 850 (Power on) or not supplied (Power off).

18A to 18D are schematic diagrams showing how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] of the backup circuit 830 during each period of the timing chart shown in FIG. 17. In the schematic diagrams, the way data is input and output (data flow) is shown by dashed arrows.

Just before the period T811, a potential L is applied to each of the wirings BK[1] to BK[4], the wirings RV[1] to RV[4], and the wiring SE. The state of the data applied to each of the wirings SN[1] and SN[2] is undefined (none of the data D1 to D3 is shown). A clock signal is applied to the wiring PCK. Power is supplied to the scan flip-flop circuit 850. Data D1 is stored in the scan flip-flop circuit 850. In the following description, unless otherwise specified, the previous state is maintained.

In period T811, first, the clock signal provided to the wiring PCK is stopped.

Next, by applying a potential H to the wiring BK[1], the data D1 output to the wiring Q is stored in the wiring SN[1] of the holding circuit 831[1]. After that, by applying a potential L to the wiring BK[1], the data D1 stored in the wiring SN[1] is held.

In period T812, the power supply to the scan flip-flop circuit 850 is cut off. Then, the data D1 stored in the scan flip-flop circuit 850 is lost. At this time, the data D1 held in the wiring SN[1] of the holding circuit 831[1] is held.

In period T813, first, the supply of power to the scan flip-flop circuit 850 is resumed.

Next, by applying a potential H to the wiring RV[1], the data D1 stored in the wiring SN[1] of the holding circuit 831[1] is applied to the wiring SD, and by applying a potential H to the wiring SE, the wiring SD is selected.

Next, a pulse signal is applied to the wiring PCK, and in synchronization with the rising edge, data D1 applied to the wiring SD is stored in the scan flip-flop circuit 850 and output to the wiring Q. Then, a potential L is applied to the wiring RV[1] and the wiring SE.

In period T814, first, the clock signal provided to the wiring PCK is resumed. Also, assume that data D2 is provided to the wiring D. Then, in synchronization with the rising edge of the clock signal, the data D2 provided to the wiring D is stored in the scan flip-flop circuit 850 and output to the wiring Q.

As described above, the semiconductor device 810 can be operated as shown in the timing chart in FIG. 17. As a result, when a power gating operation is performed in the electronic computer 900, for example, when the scan flip-flop circuit 850 is powered on, it can be quickly restored to the state it was in immediately before it was powered off, shortening the time required to resume processing.

[Operation example 2]
FIG. 19 is a timing chart for explaining an example of the operation of the semiconductor device 810 shown in FIG.

In this operation example 2, for example, an operation example of the semiconductor device 810 in the above-mentioned electronic computer 900 is described when processing is performed while switching between multiple tasks.

The timing chart shown in FIG. 19 illustrates the state (potential H or potential L) of the signal provided to each of wiring PCK, wiring BK[1], wiring BK[2], wiring RV[1], wiring RV[2], and wiring SE during each period of operation (periods T821 to T827). Note that wirings BK[3], wiring BK[4], wiring RV[3], and wiring RV[4] are not shown. Also, the state of data provided to each of wirings D, wiring Q, wiring SD, wiring SN[1], and wiring SN[2] (any one of data D1 to data D7) is illustrated. Note that wirings SN[3] and wiring SN[4] are not shown.

20A to 20G are schematic diagrams showing how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] of the backup circuit 830 during each period of the timing chart shown in FIG. 19. In the schematic diagrams, the way data is input and output (data flow) is shown by dashed arrows.

Just before the period T821, a potential L is applied to each of the wirings BK[1] to BK[4], the wirings RV[1] to RV[4], and the wiring SE. The state of the data applied to each of the wirings SN[1] and SN[2] is undefined (none of the data D1 to D7 is shown). In the following description, unless otherwise specified, the previous state is maintained.

During period T821, in synchronization with the rising edge of the signal provided to wiring PCK, data D1 provided to wiring D is stored in the scan flip-flop circuit 850 and output to wiring Q.

During period T822, in synchronization with the rising edge of the signal provided to wiring PCK, data D2 provided to wiring D is stored in the scan flip-flop circuit 850 and output to wiring Q.

At this time, by applying a potential H to the wiring BK[1], the data D2 output to the wiring Q is stored in the wiring SN[1] of the holding circuit 831[1]. Then, by applying a potential L to the wiring BK[1], the data D2 stored in the wiring SN[1] is held.

During period T823, in synchronization with the rising edge of the signal provided to wiring PCK, data D3 provided to wiring D is stored in the scan flip-flop circuit 850 and output to wiring Q.

At this time, by applying a potential H to the wiring BK[2], the data D3 output to the wiring Q is stored in the wiring SN[2] of the holding circuit 831[2]. Then, by applying a potential L to the wiring BK[2], the data D3 stored in the wiring SN[2] is held.

During period T824, in synchronization with the rising edge of the signal provided to wiring PCK, data D4 provided to wiring D is stored in the scan flip-flop circuit 850 and output to wiring Q.

In the period T825, first, a potential H is applied to the wiring RV[1], so that the data D2 stored in the wiring SN[1] of the holding circuit 831[1] is applied to the wiring SD. Note that data D5 is applied to the wiring D, but the wiring SD is selected by applying a potential H to the wiring SE.

Next, in synchronization with the rising edge of the wiring PCK, the data D2 provided to the wiring SD is stored in the scan flip-flop circuit 850 and output to the wiring Q. After that, a potential L is provided to the wiring RV[1].

In the period T826, first, a potential H is applied to the wiring RV[2], so that the data D3 stored in the wiring SN[2] of the holding circuit 831[2] is applied to the wiring SD. Note that data D6 is applied to the wiring D, but the wiring SD is selected by applying a potential H to the wiring SE.

Next, in synchronization with the rising edge of the wiring PCK, the data D3 provided to the wiring SD is stored in the scan flip-flop circuit 850 and output to the wiring Q. After that, a potential L is provided to the wiring RV[2], and a potential L is provided to the wiring SE.

During period T827, in synchronization with the rising edge of the signal provided to wiring PCK, data D7 provided to wiring D is stored in the scan flip-flop circuit 850 and output to wiring Q.

As described above, the semiconductor device 810 can be operated as shown in the timing chart in FIG. 19. As a result, when the electronic computer 900 performs processing while switching between multiple tasks, it can be configured to, for example, save data for an interrupted task and load data for a task to be resumed.

This embodiment can be combined with other embodiments as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 2)
In this embodiment, an example of a processing device that can include the memory device 720 of one embodiment of the present invention will be described.

FIG. 21 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in FIG. 21 can be applied to, for example, a CPU. The arithmetic unit 960 can also be applied to processors such as a GPU, a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

The arithmetic device 960 shown in FIG. 21 has an ALU 991 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc., via the bus interface 998.

As described below, a memory array 721 can be provided by stacking it on the arithmetic unit 960. The memory array 721 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 721 to the cache 999. In this case, it is also preferable that a drive circuit 722 is provided as part of the cache interface 989.

It is also possible to use only the memory array 721 as a cache without providing the cache 999.

The arithmetic device 960 shown in FIG. 21 is merely one example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 21 as one core, and to use a so-called multi-core configuration in which multiple cores are included and each core operates in parallel. The more cores there are, the higher the arithmetic performance can be. The more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. In addition, when extremely high arithmetic performance is required for server applications, etc., it is preferable to use a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state. The register controller 997 generates the address of the register 996, and reads or writes to the register 996 depending on the state of the arithmetic unit 960.

The timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the arithmetic unit 960 shown in FIG. 21, the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

The memory array 721 and the arithmetic device 960 can be provided overlapping each other. Figs. 22A and 22B show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 933 on which a memory array is provided, on the arithmetic device 960. The layer 933 has memory arrays 721L1, 721L2, and 721L3. The arithmetic device 960 and each memory array have overlapping areas. To make the configuration of the semiconductor device 970A easier to understand, Fig. 22B shows the arithmetic device 960 and layer 933 separated.

By stacking the layer 933 having the memory array and the computing device 960, the connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows power consumption to be reduced.

As a method for stacking the layer 933 having a memory array and the arithmetic device 960, a method of stacking the layer 933 having a memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 933 on different substrates, bonding the two substrates, and electrically connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method not only reduces the chip size but also reduces manufacturing costs because there is no need to consider misalignment during bonding.

Here, the arithmetic device 960 does not have a cache 999, and the memory arrays 721L1, 721L2, and 721L3 provided in the layer 933 can each be used as a cache. In this case, for example, the memory array 721L1 can be used as an L1 cache (also called a level 1 cache), the memory array 721L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 721L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 721L3 has the largest capacity and is accessed the least frequently. Also, the memory array 721L1 has the smallest capacity and is accessed the most frequently.

When the cache 999 provided in the computing device 960 is used as an L1 cache, each memory array provided in the layer 933 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

Also, as shown in FIG. 22B, a driving circuit 722L1, a driving circuit 722L2, and a driving circuit 722L3 are provided. The driving circuit 722L1 is connected to the memory array 721L1 via a connection electrode 940L1. Similarly, the driving circuit 722L2 is connected to the memory array 721L2 via a connection electrode 940L2, and the driving circuit 722L3 is connected to the memory array 721L3 via a connection electrode 940L3.

Note that although three memory arrays functioning as caches are shown here, the number may be one or two, or four or more.

When memory array 721L1 is used as a cache, drive circuit 722L1 may function as part of cache interface 989, or may be configured to be connected to cache interface 989. Similarly, drive circuit 722L2 and drive circuit 722L3 may also function as part of cache interface 989, or may be configured to be connected to it.

Whether the memory array 721 functions as a cache or as a main memory is determined by the control circuit 772 of each drive circuit 722. The control circuit 772 can cause some of the memory cells 741 in the storage device 720 to function as RAM based on a signal supplied from the arithmetic device 960.

The memory device 720 can cause some of the multiple memory cells 741 to function as a cache, and the other part to function as a main memory. In other words, the memory device 720 can function both as a cache and as a main memory. The memory device 720 according to one aspect of the present invention can function as a universal memory, for example.

Also, a layer 933 having one memory array 721 may be provided over the computing device 960. Figure 23A shows a perspective view of the semiconductor device 970B.

In the semiconductor device 970B, one memory array 721 can be divided into multiple areas, each of which can be used for a different function. Figure 23A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.

In addition, in the semiconductor device 970B, the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.

Also, multiple memory arrays may be stacked. Figure 23B shows a perspective view of semiconductor device 970C.

The semiconductor device 970C has a layer 933L1 having a memory array 721L1 stacked on top of a layer 933L2 having a memory array 721L2, and a layer 933L3 having a memory array 721L3 stacked on top of that. The memory array 721L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory array 721L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.

This embodiment can be combined with other embodiments as appropriate.

(Embodiment 3)
In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

Generally, various storage devices are used in semiconductor devices such as computers depending on the application. Figure 24A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required. In Figure 24A, from the top layer, there are memories embedded as registers in a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.

Memory integrated as a register in a processor such as a CPU is used for temporary storage of calculation results, and is therefore accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. Registers also have the function of storing setting information for the processor.

A cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory. In addition, data that is rewritten in the cache is duplicated and supplied to the main memory.

The main memory has the function of holding programs, data, etc. read from storage.

Storage has the function of holding data that requires long-term storage and various programs used by processing units. Therefore, storage requires a larger memory capacity and higher recording density than operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

A storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 24A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. The storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.

FIG. 24B also shows an example in which SRAM is used as part of the cache and an OS memory according to one aspect of the present invention is used as the other part.

The lowest level cache can be called an LLC (Last Level Cache). Although an LLC is not required to operate faster than higher level caches, it is desirable for it to have a large storage capacity. The OS memory of one embodiment of the present invention is suitable for use as an LLC because it operates quickly and can retain data for long periods of time. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level Cache).

For example, as shown in FIG. 24B, a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.), and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 24B, in addition to the OS memory, DRAM can also be used for the main memory.

This embodiment can be combined with other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a manufacturing method of a memory device of one embodiment of the present invention will be described with reference to drawings.

<Example of a method for manufacturing a memory device>
As a manufacturing method of a memory device of one embodiment of the present invention, an example of a manufacturing method of the memory device illustrated in FIGS.

Figures 25A, 27A, 29A, 31A, 33A, 35A, 37A, 39A, 41A, 43A, 45A, 47A, and 49A are plan views. Also, Figures 25B, 27B, 29B, 31B, 33B, 35B, 37B, 39B, 41B, 43B, 45B, 47B, and 49B are cross-sectional views corresponding to the portions indicated by the dashed line A1-A2 in Figures 25A, 27A, 29A, 31A, 33A, 35A, 37A, 39A, 41A, 43A, 45A, 47A, and 49A, respectively. In addition, Figures 25C, 27C, 29C, 31C, 33C, 35C, 37C, 39C, 41C, 43C, 45C, 47C, and 49C are cross-sectional views corresponding to the areas indicated by the dotted line A3-A4 in Figures 25A, 27A, 29A, 31A, 33A, 35A, 37A, 39A, 41A, 43A, 45A, 47A, and 49A, respectively. 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, and 50 are cross-sectional views corresponding to the portions indicated by the dashed lines A5-A6 in FIGS. 25A, 27A, 29A, 31A, 33A, 35A, 37A, 39A, 41A, 43A, 45A, 47A, and 49A, respectively. Note that in the plan views of FIGS. 25A, 27A, 29A, 31A, 33A, 35A, 37A, 39A, 41A, 43A, 45A, 47A, and 49A, some elements are omitted for clarity.

In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed into films using appropriate film formation methods such as sputtering, CVD, MBE, PLD, or ALD.

Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.

CVD methods can be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. Furthermore, they can be classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.

The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) contained in a memory device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements contained in the memory device. On the other hand, with the thermal CVD method, which does not use plasma, such plasma damage does not occur, and the yield of memory devices can be increased. Furthermore, with the thermal CVD method, no plasma damage occurs during film formation, so films with fewer defects can be obtained.

Also, the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.

The CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

Also, with the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, with the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transportation or pressure adjustment. Therefore, the productivity of storage devices can be increased in some cases.

Also, in the ALD method, by simultaneously introducing multiple different types of precursors, it is possible to deposit a film of any composition. Or, when multiple different types of precursors are introduced, it is possible to deposit a film of any composition by controlling the number of cycles of each precursor.

First, a substrate (not shown) is prepared, and an insulating layer 101 is formed on the substrate. The insulating material described above can be used as appropriate for the insulating layer 101. The insulating layer 101 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

Next, a conductive layer 111a is formed on the insulating layer 101 (FIGS. 25A to 26). For example, a conductive film that will become the conductive layer 111a is formed, and the conductive film is processed to form the conductive layer 111a. The conductive film that will become the conductive layer 111a can be made of any of the conductive materials that can be used for the conductive layer 111a described above.

The conductive film that becomes the conductive layer 111a can be formed by appropriately using a film formation method such as sputtering, CVD, MBE, PLD, or ALD. For example, a laminated film in which tungsten and titanium nitride are deposited in this order can be formed as the conductive film that becomes the conductive layer 111a using a CVD method. After the conductive film that becomes the conductive layer 111a is formed, a pattern is formed by lithography, for example, and the conductive film is processed using a dry etching method or a wet etching method based on the pattern, thereby forming the conductive layer 111a. Here, if the conductive film is processed by a dry etching method, fine processing can be performed, which is preferable.

In the lithography method, the resist is first exposed to light through a mask. Next, the exposed areas are removed or left to form a resist mask using a developer. This forms a pattern.

For example, a resist mask is formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV light, or the like. Also, a liquid immersion technique may be used in which exposure is performed by filling the space between the substrate and the projection lens with liquid (e.g., water). Also, an electron beam or ion beam may be used instead of the light described above. Note that when an electron beam or ion beam is used, a mask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.

Next, an etching process is performed through the resist mask. This allows the conductive layer, semiconductor layer, insulating layer, etc. to be processed into the desired shape.

When performing dry etching as the etching process, an etching gas containing halogen can be used as the etching gas, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, _C4F6 gas, _C5F6 gas _{, C4F8 gas, CF4 gas, SF6 gas, NF3 gas, CHF3} _gas _, _Cl2 _gas _, _BCl3 _gas _, _SiCl4 gas, _CCl4 gas, or _BBr3 gas can be used alone or in combination of two or more gases. In addition, oxygen gas, carbon _dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. The etching conditions can be appropriately set according to the object to be etched.

As the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching device having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Or, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Or, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Or, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Or, a dry etching device having a high density plasma source can be used. As the dry etching device having a high density plasma source, for example, an inductively coupled plasma (ICP) etching device can be used.

Next, an insulating layer 103a functioning as an interlayer insulating layer is formed on the insulating layer 101 and the conductive layer 111a. The insulating layer 103a can be formed using the insulating material described above as appropriate. The insulating layer 103a can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a silicon oxide film is formed as the insulating layer 103a by a sputtering method. Note that it is preferable to planarize the upper surface of the insulating layer 103a by performing a chemical mechanical polishing (CMP) process after the film formation. By performing a planarization process on the insulating layer 103a, a conductive layer 112a functioning as the other of the source electrode or drain electrode of the transistor 41 can be suitably formed in a later process. In addition, after aluminum oxide is formed on the insulating layer 103a by, for example, a sputtering method, CMP processing may be performed until the insulating layer 103a is reached. By performing this CMP processing, the surface of the insulating layer 103a can be planarized and smoothed. By placing the aluminum oxide on the insulating layer 103a and performing the CMP processing, it becomes easier to detect the end point of the CMP processing.

In some cases, it is not necessary to perform the CMP process. In this case, the upper surface of the insulating layer 103a has a convex curved shape. By not performing the planarization process, it is possible to reduce the manufacturing cost and increase the production yield.

In addition, a recess may be provided in the insulating layer 101, and the conductive layer 111a may be formed to fill the recess. The height of the upper surface of the insulating layer 101 and the height of the upper surface of the conductive layer 111a may be formed to be roughly the same, and then the insulating layer 103a may be formed on the insulating layer 101 and the conductive layer 111a.

In addition, the insulating layer 103a containing excess oxygen can be formed by depositing the insulating layer 103a by a sputtering method in an atmosphere containing oxygen. In addition, the hydrogen concentration in the insulating layer 103a can be reduced by using a sputtering method in which molecules containing hydrogen are not required for deposition gas. By depositing the insulating layer 103a in this manner, oxygen can be supplied from the insulating layer 103a to a channel formation region of the semiconductor layer 113a to be formed in a later step, and oxygen vacancies and _VOH can be reduced.

Next, a conductive film 112A that will later become the conductive layer 112a is formed on the insulating layer 103a (FIGS. 27A to 28). The conductive film 112A can be formed using any of the conductive materials that can be used for the conductive layer 112 described above. The conductive film 112A can be formed using any of a variety of deposition methods, such as sputtering, CVD, MBE, PLD, or ALD.

Next, a part of the conductive film 112A and a part of the insulating layer 103a are processed to form an opening 121a that reaches the conductive layer 111a (FIGS. 29A to 30). The opening 121a can be formed by using, for example, lithography and etching. Through this processing, a conductive layer 112f having an opening is formed from the conductive film 112A.

Here, it is preferable that the sidewall of the opening 121a is perpendicular to the upper surface of the conductive layer 111a. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Furthermore, the sidewall of the opening 121a may be tapered. By making the sidewall of the opening 121a tapered, for example, the coverage of a metal oxide film or the like that becomes the semiconductor layer 113a described below can be improved, and defects such as voids can be reduced.

The size of the maximum width of the opening 121a (diameter when the opening 121a is circular in plan view) is preferably minute. For example, the maximum width of the opening 121a is preferably 1 nm or more and 60 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 40 nm or less, 5 nm or more and 30 nm or less, or 5 nm or more and 20 nm or less.

Because the aspect ratio of the opening 121a is large, it is preferable to process a portion of the conductive film 112A and a portion of the insulating layer 103a using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions. Note that depending on the conditions for processing the portion of the conductive film 112A and the portion of the insulating layer 103a, the inclination of the side surface of the conductive layer 112f in the opening 121a and the inclination of the side surface of the insulating layer 103a in the opening 121a may differ from each other.

Then, a heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in, for example, a nitrogen gas or inert gas atmosphere. The heat treatment may be performed under reduced pressure. By performing the heat treatment as described above, impurities such as water contained in the insulating layer 103a and the like can be reduced before the formation of a metal oxide film that becomes the semiconductor layer 113a described later.

In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, for example, it is possible to prevent moisture from being absorbed into the insulating layer 103a as much as possible.

Then, the conductive layer 112f is processed to form the conductive layer 112a so as to have an area that overlaps with the conductive layer 111a in a plan view. For example, a pattern is formed by lithography, and the conductive layer 112f is processed based on the pattern using a dry etching method or a wet etching method, thereby forming the conductive layer 112a. Here, it is preferable to process the conductive layer 112f by a dry etching method, since this allows fine processing.

Next, a metal oxide film that will later become the semiconductor layer 113a is formed in contact with the upper surface of the conductive layer 112a, the side surface of the conductive layer 112a in the opening 121a, the side surface of the insulating layer 103a in the opening 121a, and the upper surface of the conductive layer 111a in the opening 121a. The metal oxide film that will become the semiconductor layer 113a can be appropriately formed using a metal oxide that can be applied to the semiconductor layer 113 described above. The metal oxide film that will become the semiconductor layer 113a can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, it is preferable that the metal oxide film that will become the semiconductor layer 113a is formed in contact with the side surface of the conductive layer 112a, the side surface of the insulating layer 103a, and the upper surface of the conductive layer 111a in the opening 121a with a large aspect ratio. Therefore, the metal oxide film that becomes the semiconductor layer 113a is preferably formed using a film formation method that has good coverage, and it is more preferable to use a CVD method, an ALD method, or the like. For example, an In-Ga-Zn oxide film is formed by the ALD method as the metal oxide film that becomes the semiconductor layer 113a.

When the sidewall of the opening 121a is tapered, the deposition of the metal oxide film that becomes the semiconductor layer 113a is not limited to the CVD method or the ALD method. For example, a sputtering method may be used.

In addition, when the semiconductor layer 113a has a laminated structure, the deposition method of each layer included in the semiconductor layer 113a may be the same or different. For example, when the semiconductor layer 113a has a laminated structure of two layers, the lower layer of the metal oxide film that becomes the semiconductor layer 113a may be deposited by a sputtering method, and the upper layer may be deposited by an ALD method. Metal oxide films deposited by a sputtering method tend to have crystallinity. Therefore, by providing a crystalline metal oxide film as the lower layer of the metal oxide film that becomes the semiconductor layer 113a, the crystallinity of the upper layer can be increased. In addition, even if pinholes or discontinuities are formed in the lower layer of the metal oxide film deposited by the sputtering method, the parts that overlap with them can be blocked by the upper layer of the metal oxide film deposited by the ALD method, which has good coverage.

Here, the metal oxide film that becomes the semiconductor layer 113a is preferably formed in contact with the top surface of the conductive layer 111a in the opening 121a, the side surface of the insulating layer 103a in the opening 121a, the side surface of the conductive layer 112a in the opening 121a, and the top surface of the conductive layer 112a. By forming the metal oxide film in contact with the conductive layer 111a, the conductive layer 111a functions as one of the source electrode or drain electrode of the transistor 41.

Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the metal oxide film that becomes the semiconductor layer 113a does not become polycrystallized, and may be performed at 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. For details of the heat treatment, refer to the above description.

Here, the heat treatment is preferably performed in a state where the insulating layer 103a containing excess oxygen is provided in contact with the metal oxide film to be the semiconductor layer 113a. By performing the heat treatment in this manner, oxygen can be supplied from the insulating layer 103a to the metal oxide film to be the semiconductor layer 113a, and oxygen vacancies and _VOH in the semiconductor layer 113a to be formed later can be reduced.

In the above, the heat treatment is performed after the metal oxide film that becomes the semiconductor layer 113a is formed, but the present invention is not limited to this. It is also possible to perform the heat treatment in a later process.

Next, the metal oxide film that will become the semiconductor layer 113a is processed to form the semiconductor layer 113a so as to have an area that overlaps with the opening 121a in a plan view (FIGS. 31A to 32). For example, the metal oxide film that will become the semiconductor layer 113a is patterned by lithography, and then processed by etching based on the pattern. This allows the semiconductor layer 113a to be formed so as to have an area that overlaps with the opening 121a. As a result, a part of the semiconductor layer 113a is formed in the opening 121a. Also, the semiconductor layer 113a contacts the upper surface of the conductive layer 112a. As a result, the semiconductor layer 113a is formed to have an area that contacts the upper surface of the conductive layer 111a in the opening 121a, an area that contacts the side surface of the insulating layer 103a in the opening 121a, an area that contacts the side surface of the conductive layer 112a in the opening 121a, and an area that contacts the upper surface of the conductive layer 112a.

Note that, although Figs. 31A and 31B show an example in which the end of the semiconductor layer 113a is formed so as to roughly coincide with the end of the conductive layer 112a in the X direction, this is not a limitation. The end of the semiconductor layer 113a may be located inside the end of the conductive layer 112a in the X direction. Also, the end of the semiconductor layer 113a may be located outside the end of the conductive layer 112a in the X direction, and the lower surface of the semiconductor layer 113a may be in contact with the side of the conductive layer 112a that does not face the opening 121a and the upper surface of the insulating layer 103a.

In the above, the example in which the semiconductor layer 113a is formed after the conductive layer 112a is formed has been described, but this is not the only possible example. For example, in one embodiment of the present invention, after the opening 121a is formed (FIGS. 29A to 30), a metal oxide film that will become the semiconductor layer 113a may be formed, the metal oxide film may be processed to form the semiconductor layer 113a, and then the conductive layer 112f may be processed to form the conductive layer 112a.

Next, the insulating layer 105a is formed in contact with the upper surface of the semiconductor layer 113a (FIGS. 33A to 34). The insulating layer 105a can be formed using any of the insulating materials described above. The insulating layer 105a can be formed using any of a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the insulating layer 105a is preferably formed in contact with the upper surface of the semiconductor layer 113a in the opening 121a having a large aspect ratio. Therefore, the insulating layer 105a is preferably formed using a method with good coverage, and more preferably using a CVD method, an ALD method, or the like. For example, silicon oxide is formed as the insulating layer 105a using the ALD method.

If the sidewall of the opening 121a is tapered, the deposition of the insulating layer 105a is not limited to the CVD or ALD method. For example, a sputtering method may be used.

By forming the insulating layer 105a after forming the semiconductor layer 113a, the side end of the semiconductor layer 113a is covered with the insulating layer 105a. This makes it possible to prevent a short circuit between the semiconductor layer 113a and the conductive layer 115a that will be formed in a later step. Furthermore, by using the above configuration, the side end of the conductive layer 112a is covered with the insulating layer 105a. This makes it possible to prevent a short circuit between the conductive layer 112a and the conductive layer 115a.

Next, a conductive film that will become the conductive layer 115a is formed on the insulating layer 105a so as to fill the opening 121a. The conductive film that will become the conductive layer 115a can be formed using any of the conductive materials that can be used for the conductive layer 115 described above. The conductive film that will become the conductive layer 115a can be formed using any of a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the conductive film that will become the conductive layer 115a is preferably formed in contact with the insulating layer 105a provided in the opening 121a with a large aspect ratio. Therefore, the conductive film that will become the conductive layer 115a is preferably formed using a film formation method that has good coverage or filling properties, and more preferably using a CVD method, an ALD method, or the like.

Note that when a conductive film that becomes the conductive layer 115a is formed by using a CVD method, the average surface roughness of the upper surface of the conductive film may become large. In this case, it is preferable to planarize the conductive film by using a CMP method. At this time, before performing the CMP process, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film, and the CMP process may be performed until the silicon oxide film or the silicon oxynitride film is removed. Note that the CMP process does not have to be performed.

In the above, the conductive film that becomes conductive layer 115a is provided so as to fill opening 121a, but the present invention is not limited to this. For example, a recess reflecting the shape of opening 121a may be formed on the upper part of the conductive film that becomes conductive layer 115a. The recess may also be filled with, for example, an inorganic insulating material. Note that the recess does not have to be filled with an inorganic insulating material, etc.

Next, a part of the conductive film that will become the conductive layer 115a is processed to form the conductive layer 115a (Figures 35A to 36). The conductive layer 115a can be formed, for example, by forming a pattern by lithography, and then processing the conductive film that will become the conductive layer 115a by etching based on the pattern. For example, dry etching or wet etching can be used for this processing, but processing by dry etching is preferable because it is suitable for fine processing. The conductive layer 115a is formed on the insulating layer 105a so as to have an area that overlaps with the semiconductor layer 113a.

In this manner, a transistor 41 can be formed having a conductive layer 111a, a conductive layer 112a, a semiconductor layer 113a, an insulating layer 105a, and a conductive layer 115a.

As described above, the conductive layer 111a functions as one of the source electrode and drain electrode of the transistor 41. The conductive layer 112a functions as the other of the source electrode and drain electrode of the transistor 41. The insulating layer 105a functions as the gate insulating layer of the transistor 41. The conductive layer 115a functions as the gate electrode of the transistor 41.

Next, insulating layer 107a is formed to cover conductive layer 115a and insulating layer 105a. After that, insulating layer 135 is formed on insulating layer 107a. For insulating layer 107a and insulating layer 135, insulating materials applicable to insulating layer 107 and insulating layer 135 described above can be appropriately used. Insulating layer 107a and insulating layer 135 can be formed by appropriately using a film formation method such as sputtering, CVD, MBE, PLD, or ALD.

Next, a conductive film 141f, which will later become the conductive layer 141, is formed on the insulating layer 135 (FIGS. 37A to 38). The conductive film 141f can be formed using any conductive material that can be used for the conductive layer 141 described above. The conductive film 141f can be formed using any film formation method, such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

Next, the conductive film 141f is processed to form the conductive layer 141 so as to have an area overlapping with the conductive layer 115a in a planar view (FIGS. 39A to 40). The conductive layer 141 can be formed, for example, by forming a pattern by lithography, and then processing the conductive film 141f by etching based on the pattern. For example, a dry etching method or a wet etching method can be used for this processing, but processing by a dry etching method is preferable because it is suitable for fine processing. The conductive layer 141 is formed with a gap between it and the opening 121a in a planar view.

Next, an insulating layer 103b that functions as an interlayer insulating layer is formed on the conductive layer 141 and the insulating layer 135. The insulating layer 103b can be formed using the same material and by the same method as the insulating layer 103a described above. Note that it is preferable to planarize the upper surface of the insulating layer 103b by performing a CMP process after the film formation. By performing the planarization process on the insulating layer 103b, the conductive layer 112b that functions as the other of the source electrode or drain electrode of the transistor 42 can be preferably formed in a later process.

In some cases, it is not necessary to perform the CMP process. In this case, the upper surface of the insulating layer 103b has a convex curved shape. By not performing the planarization process, it is possible to reduce the manufacturing cost and increase the production yield.

In addition, the insulating layer 103b containing excess oxygen can be formed by depositing the insulating layer 103b by a sputtering method in an atmosphere containing oxygen. In addition, the hydrogen concentration in the insulating layer 103b can be reduced by using a sputtering method in which molecules containing hydrogen are not required for deposition gas. By depositing the insulating layer 103b in this manner, oxygen can be supplied from the insulating layer 103b to a channel formation region of the semiconductor layer 113b to be formed in a later step, and oxygen vacancies and _VOH can be reduced.

Next, a conductive film 112B, which will later become the conductive layer 112b, is formed on the insulating layer 103b (FIGS. 41A to 42). The conductive film 112B can be formed using the same material and method as the conductive film 112A described above.

Next, a part of the conductive film 112B, a part of the insulating layer 103b, a part of the insulating layer 135, and a part of the insulating layer 107a are processed to form an opening 121b that reaches the conductive layer 115a (Figures 43A to 44). The same method as used to form the opening 121a described above can be used to form the opening 121b. Through this processing, a conductive layer 112s having an opening is formed from the conductive film 112B.

Here, it is preferable that the sidewall of the opening 121b is perpendicular to the upper surface of the conductive layer 115a. With such a configuration, it is possible to miniaturize or highly integrate the memory device. The sidewall of the opening 121b may also be tapered. By making the sidewall of the opening 121b tapered, for example, the coverage of a metal oxide film or the like that becomes the semiconductor layer 113b described below can be improved, and defects such as voids can be reduced.

The size of the maximum width of the opening 121b (diameter when the opening 121b is circular in plan view) is preferably minute. For example, the maximum width of the opening 121b is preferably 1 nm or more and 60 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 40 nm or less, 5 nm or more and 30 nm or less, or 5 nm or more and 20 nm or less.

Because the aspect ratio of the opening 121b is large, it is preferable to process a part of the conductive film 112B, a part of the insulating layer 103b, a part of the insulating layer 135, and a part of the insulating layer 107a by anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions. Note that depending on the conditions for processing the part of the conductive film 112B, the part of the insulating layer 103b, the part of the insulating layer 135, and the part of the insulating layer 107a, the inclination of the side surface of the conductive layer 112s in the opening 121b, the inclination of the side surface of the insulating layer 103b in the opening 121b, the inclination of the side surface of the insulating layer 135 in the opening 121b, and the inclination of the side surface of the insulating layer 107a in the opening 121b may differ from each other.

Then, a heat treatment may be performed. For details of the heat treatment, the description of the heat treatment that can be performed after the formation of the opening 121a described above can be referred to. By performing the heat treatment, impurities such as water contained in the insulating layer 103b and the like can be reduced before the formation of a metal oxide film that becomes the semiconductor layer 113b described later.

Then, the conductive layer 112s is processed to form the conductive layer 112b so as to have an area that overlaps with the conductive layer 115a in a plan view. For example, a pattern is formed by lithography, and the conductive layer 112s is processed based on the pattern using a dry etching method or a wet etching method, etc., to form the conductive layer 112b. Here, it is preferable to process the conductive layer 112s by a dry etching method, since this allows fine processing.

Next, a metal oxide film that will later become the semiconductor layer 113b is formed in contact with the upper surface of the conductive layer 112b, the side of the conductive layer 112b in the opening 121b, the side of the insulating layer 103b in the opening 121b, the side of the insulating layer 135 in the opening 121b, the side of the insulating layer 107a in the opening 121b, and the upper surface of the conductive layer 115a in the opening 121b. The metal oxide film that will become the semiconductor layer 113b can be formed using the same material and by the same method as the metal oxide film that will become the semiconductor layer 113a described above. Here, it is preferable that the metal oxide film that will become the semiconductor layer 113b is formed in contact with the side of the conductive layer 112b, the side of the insulating layer 103b, the side of the insulating layer 135, the side of the insulating layer 107a, and the upper surface of the conductive layer 115a in the opening 121b with a large aspect ratio. Therefore, the metal oxide film that becomes the semiconductor layer 113b is preferably formed using a film formation method that has good coverage, and it is more preferable to use a CVD method, an ALD method, or the like. For example, an In-Ga-Zn oxide film is formed by the ALD method as the metal oxide film that becomes the semiconductor layer 113b.

When the sidewall of the opening 121b is tapered, the deposition of the metal oxide film that becomes the semiconductor layer 113b is not limited to the CVD method or the ALD method. For example, a sputtering method may be used.

The semiconductor layer 113b may have a laminated structure. For the method of forming each layer when the semiconductor layer 113b has a laminated structure, the description of the method of forming each layer when the semiconductor layer 113a has a laminated structure can be referred to.

Here, the metal oxide film that becomes the semiconductor layer 113b is preferably formed in contact with the top surface of the conductive layer 115a in the opening 121b, the side surface of the insulating layer 107a in the opening 121b, the side surface of the insulating layer 135 in the opening 121b, the side surface of the insulating layer 103b in the opening 121b, the side surface of the conductive layer 112b in the opening 121b, and the top surface of the conductive layer 112b. By forming the metal oxide film in contact with the conductive layer 115a, the conductive layer 115a that functions as the gate electrode of the transistor 41 also functions as one of the source electrode or drain electrode of the transistor 42.

Next, it is preferable to perform a heat treatment. For details of the heat treatment, the description of the heat treatment that can be performed after the formation of the metal oxide film that becomes the semiconductor layer 113a described above can be referred to.

Next, the metal oxide film that will become semiconductor layer 113b is processed to form semiconductor layer 113b so that it has an area that overlaps with opening 121b in a planar view (Figures 45A to 46). For a method of forming semiconductor layer 113b, the description of the method of forming semiconductor layer 113a above can be referred to. In this way, semiconductor layer 113b can be formed so that it has an area that overlaps with opening 121b. In this way, a portion of semiconductor layer 113b is formed in opening 121b. In addition, semiconductor layer 113b contacts the upper surface of conductive layer 115a. As a result of the above, semiconductor layer 113b is formed, which has a region in contact with the top surface of conductive layer 115a in opening 121b, a region in contact with the side surface of insulating layer 107a in opening 121b, a region in contact with the side surface of insulating layer 135 in opening 121b, a region in contact with the side surface of insulating layer 103b in opening 121b, a region in contact with the side surface of conductive layer 112b in opening 121b, and a region in contact with the top surface of conductive layer 112b.

Note that although Figures 45A and 45B show an example in which the end of the semiconductor layer 113b is formed so as to roughly coincide with the end of the conductive layer 112b in the X direction, this is not a limitation. The end of the semiconductor layer 113b may be located inside the end of the conductive layer 112b in the X direction. Also, the end of the semiconductor layer 113b may be located outside the end of the conductive layer 112b in the X direction, and the lower surface of the semiconductor layer 113b may be in contact with the side of the conductive layer 112b that does not face the opening 121b and the upper surface of the insulating layer 103b.

In the above, the example in which the semiconductor layer 113b is formed after the conductive layer 112b is formed has been described, but this is not the only possible example. For example, in one embodiment of the present invention, after the opening 121b is formed (FIGS. 43A to 44), a metal oxide film that will become the semiconductor layer 113b may be formed, the metal oxide film may be processed to form the semiconductor layer 113b, and then the conductive layer 112s may be processed to form the conductive layer 112b.

Next, the insulating layer 105b is formed in contact with the upper surface of the semiconductor layer 113b (FIGS. 47A to 48). The insulating layer 105b can be formed using the same material and method as the insulating layer 105a described above. Here, the insulating layer 105b is preferably formed in contact with the upper surface of the semiconductor layer 113b in the opening 121b with a large aspect ratio. Therefore, the insulating layer 105b is preferably formed using a film formation method with good coverage, and more preferably using a CVD method, ALD method, or the like. For example, silicon oxide is formed as the insulating layer 105b using the ALD method.

If the sidewall of the opening 121b is tapered, the method for forming the insulating layer 105b is not limited to the CVD method or the ALD method. For example, a sputtering method may be used.

By forming the insulating layer 105b after forming the semiconductor layer 113b, the side end of the semiconductor layer 113b is covered with the insulating layer 105b. This makes it possible to prevent a short circuit between the semiconductor layer 113b and the conductive layer 115b that will be formed in a later process. Furthermore, by using the above configuration, the side end of the conductive layer 112b is covered with the insulating layer 105b. This makes it possible to prevent a short circuit between the conductive layer 112b and the conductive layer 115b.

Next, a conductive film that will become conductive layer 115b is formed on insulating layer 105b so as to fill opening 121b. The conductive film that will become conductive layer 115b can be formed using the same material and method as the conductive film that will become conductive layer 115a described above. Here, the conductive film that will become conductive layer 115b is preferably formed in contact with insulating layer 105b provided in opening 121b with a large aspect ratio. Therefore, the conductive film that will become conductive layer 115b is preferably formed using a film formation method that has good coverage or filling properties, and more preferably using a CVD method, ALD method, or the like.

Note that when a conductive film that becomes the conductive layer 115b is formed by using a CVD method, the average surface roughness of the upper surface of the conductive film may become large. In this case, it is preferable to planarize the conductive film by using a CMP method. At this time, before performing the CMP process, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film, and the CMP process may be performed until the silicon oxide film or the silicon oxynitride film is removed. Note that the CMP process does not have to be performed.

In the above, the conductive film that becomes conductive layer 115b is provided so as to fill opening 121b, but the present invention is not limited to this. For example, a recess reflecting the shape of opening 121b may be formed on the upper part of the conductive film that becomes conductive layer 115b. The recess may also be filled with, for example, an inorganic insulating material. Note that the recess does not have to be filled with an inorganic insulating material, etc.

Next, a part of the conductive film that will become the conductive layer 115b is processed to form the conductive layer 115b (Figures 49A to 50). The conductive layer 115b can be formed using the same method as that used to form the conductive layer 115a described above. The conductive layer 115b is formed on the insulating layer 105b so as to have an area that overlaps with the semiconductor layer 113b.

In this manner, a transistor 42 having a conductive layer 115a, a conductive layer 112b, a semiconductor layer 113b, an insulating layer 105b, and a conductive layer 115b can be formed.

As described above, the conductive layer 115a functions as one of the source electrode and drain electrode of the transistor 42. The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 42. The insulating layer 105b functions as the gate insulating layer of the transistor 42. The conductive layer 115b functions as the gate electrode of the transistor 42.

In addition, a capacitor 51 can be formed having the insulating layer 103b, the semiconductor layer 113b, and the insulating layer 105b in the area sandwiched between the conductive layer 115a, the conductive layer 141, a portion of the insulating layer 107a (portion sandwiched between the conductive layer 115a and the conductive layer 141), a portion of the insulating layer 135 (portion sandwiched between the conductive layer 115a and the conductive layer 141), a portion of the conductive layer 115b (portion located within the opening 121b), and the portion of the conductive layer 115b and the conductive layer 141.

As described above, conductive layer 115a functions as one electrode of capacitance 51. Conductive layer 141 functions as the other electrode of capacitance 51. A portion of insulating layer 107 (portion sandwiched between conductive layer 115a and conductive layer 141) and a portion of insulating layer 135 (portion sandwiched between conductive layer 115a and conductive layer 141) function as dielectric layers of capacitance 51.

In addition to the above, a portion of the conductive layer 115b (a portion located within the opening 121b) functions as the gate electrode of the transistor 42 and can also function as one or the other electrode of the capacitor 51. The insulating layer 103b, the semiconductor layer 113b, and the insulating layer 105b in the region sandwiched between the conductive layer 141 and the portion of the conductive layer 115b function as an interlayer insulating layer, a semiconductor layer of the transistor 42, and a gate insulating layer of the transistor 42, respectively, and can also function as a dielectric layer of the capacitor 51.

Next, an insulating layer 107b is formed on the conductive layer 115b and on the insulating layer 105b (FIGS. 5A to 6). The insulating layer 107b can be formed using the same material and method as the insulating layer 107a described above.

As described above, a memory device having a transistor 41, a transistor 42, a capacitor 51, an insulating layer 103a, and an insulating layer 103b as shown in Figures 5A to 6 can be manufactured.

(Embodiment 5)
In this embodiment mode, a configuration example of a memory device in which a plurality of layers including the memory cell 741 described in the above embodiment mode are stacked will be described with reference to drawings.

FIG. 51 is a cross-sectional view showing an example of the configuration of layers 984[1] to 984[n] (n is an integer of 1 or more) of the electronic calculator 900 shown in FIG. 1B, showing the XZ plane. As shown in FIG. 51, layer 984[1] is provided on insulating layer 101, layer 984[2] is provided on layer 984[1], and layer 984[n] is provided on the top layer. As described above, memory cells 741 are provided in layer 984. FIG. 51 shows an example of the configuration of memory cells 741 in n rows and 2 columns. This makes it possible to reduce the area occupied by the memory device. In addition, the memory capacity per unit area can be increased.

The memory cell 741 has a transistor 41, a transistor 42, and a capacitor 51. In this embodiment, for example, the transistor 41, the transistor 42, and the capacitor 51 in the layer 984[1] are transistor 41[1], transistor 42[1], and capacitor 51[1], respectively, the transistor 41, the transistor 42, and the capacitor 51 in the layer 984[2] are transistor 41[2], transistor 42[2], and capacitor 51[2], respectively, and the transistor 41, the transistor 42, and the capacitor 51 in the layer 984[n] are transistor 41[n], transistor 42[n], and capacitor 51[n], respectively. The transistor 41[1], the transistor 42[1], and the capacitor 51[1] constitute the memory cell 741[1] in the layer 984[1]. The transistor 41[2], the transistor 42[2], and the capacitor 51[2] constitute a memory cell 741[2] in the layer 984[2]. The transistor 41[n], the transistor 42[n], and the capacitor 51[n] constitute a memory cell 741[n] in the layer 984[n]. As described above, an insulating layer 107b is provided on the transistor 42. In this embodiment, for example, the insulating layer 107b provided on the transistor 42[1] is the insulating layer 107b[1], the insulating layer 107b provided on the transistor 42[2] is the insulating layer 107b[2], and the insulating layer 107b provided on the transistor 42[n] is the insulating layer 107b[n].

Here, an insulating layer 139 that functions as an interlayer insulating layer is provided on the insulating layer 107b. In this embodiment, for example, the insulating layer 139 provided in the layer 984[1] is referred to as an insulating layer 139[1], the insulating layer 139 provided in the layer 984[2] is referred to as an insulating layer 139[2], and the insulating layer 139 provided in the layer 984[n] is referred to as an insulating layer 139[n]. For example, a transistor 41[2] is provided on the insulating layer 139[1]. The insulating layer 139 can be made of the same material as that which can be used for the interlayer insulating layer shown in the above embodiment.

(Embodiment 6)
In this embodiment, an application example of a memory device of one embodiment of the present invention will be described with reference to drawings. The memory device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, large scale computers, space equipment, and data centers using the memory device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[Electronic Components]
FIG. 52A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 52A has a semiconductor device 710 in a mold 711. In FIG. 52A, some parts are omitted in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

The semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration can be formed in which the memory is formed directly on the processor. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.

In addition, by configuring the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSVs, and therefore to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as monolithic stacks, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.

The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip, for example, by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, a perspective view of electronic component 730 is shown in FIG. 52B. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

In electronic component 730, an example is shown in which semiconductor device 710 is used as a high bandwidth memory (HBM). In addition, semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode. In addition, in a silicon interposer, a TSV can also be used as the through electrode.

In an HBM, many wiring connections are required to achieve a wide memory bandwidth. For this reason, the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.

Furthermore, in SiP and MCM using silicon interposers, deterioration of reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.

On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be used that combines a memory cell array stacked using TSVs with a monolithic stacking memory cell array.

A heat sink (heat sink) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. FIG. 52B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Electronic devices]
Next, a perspective view of an electronic device 6500 is shown in FIG. 53A. The electronic device 6500 shown in FIG. 53A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The storage device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

The electronic device 6600 shown in FIG. 53B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 has a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, and the like. Note that the control device 6616 has, for example, one or more selected from a CPU, a GPU, and a storage device. The storage device of one embodiment of the present invention can be applied to the display unit 6615, the control device 6616, and the like. Note that the use of the storage device of one embodiment of the present invention for the control device 6509 and the control device 6616 described above is preferable because power consumption can be reduced.

[Mainframe computers]
Next, Fig. 53C shows a perspective view of the large scale computer 5600. The large scale computer 5600 shown in Fig. 53C has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

Computer 5620 can have the configuration shown in the perspective view of FIG. 53D, for example. In FIG. 53D, computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

The PC card 5621 shown in FIG. 53E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 53E illustrates semiconductor devices other than the

semiconductor devices

5626, 5627, and 5628, but for those semiconductor devices, the explanations of the

semiconductor devices

5626, 5627, and 5628 described below can be referred to.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

Connection terminals

5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621 and inputting signals, for example. They can also be interfaces for outputting signals calculated by PC card 5621, for example. Standards for

connection terminals

5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When a video signal is output from

connection terminals

5623, 5624, and 5625, the standard for each can be, for example, HDMI (registered trademark).

The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.

[Space equipment]
The memory device of one embodiment of the present invention can be suitably used in space equipment.

A storage device according to one embodiment of the present invention includes an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation and can be preferably used in an environment where radiation may be incident. For example, the OS transistor can be preferably used in outer space. Specifically, the OS transistor can be used as a transistor constituting a storage device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.

FIG. 54 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that FIG. 54 also shows a planet 6804 in space.

Although not shown in FIG. 54, the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit. The use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.

In addition, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. The signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a storage device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object located on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.

Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.

[Data Center]
The storage device according to one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring the immutability of the data. When managing long-term data, it is necessary to increase the size of the building, such as by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.

By using a storage device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the storage device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.

In addition, the memory device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the memory device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.

Figure 55 shows a storage system applicable to a data center. The storage system 7000 shown in Figure 55 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. In storage systems, to solve the problem of the long access speed of storage 7003, cache memory is usually provided within the storage to reduce the time required to store and output data.

The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

By using OS transistors as transistors for storing data in the cache memory, which hold a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced. In addition, by stacking the memory cell array, miniaturization is possible.

Note that the application of the memory device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the performance or integration of memory devices, the use of the memory device of one embodiment of the present invention can reduce emissions of greenhouse gases such as carbon dioxide (CO ₂ ). In addition, the memory device of one embodiment of the present invention is also effective as a measure against global warming because of its low power consumption.

This embodiment can be combined with other embodiments as appropriate.

41[1]: transistor, 41[2]: transistor, 41[n]: transistor, 41: transistor, 42[1]: transistor, 42[2]: transistor, 42[n]: transistor, 42: transistor, 51[1]: capacitance, 51[2]: capacitance, 51[n]: capacitance, 51: capacitance, 101: insulating layer, 103a: insulating layer, 103b: insulating layer, 103: insulating layer, 105a: insulating layer, 105b: insulating layer, 105: insulating layer, 107a: insulating layer, 107b[1]: insulating layer, 107b[2]: insulating layer, 107b[n]: insulating layer, 107b: insulating layer, 107: insulating layer, 111a: conductive layer, 112a: conductive layer, 112f: conductive layer, 112s: conductive layer, 112A: conductive film, 112b: conductive layer, 112B: conductive film, 112: conductive layer, 113a: semiconductor layer, 113b: semiconductor layer, 113i: region, 113na: region, 113nb: region, 113: semiconductor layer, 115a: conductive layer, 115b: conductive layer, 115: conductive layer, 121a: opening, 121b: opening, 121: opening, 127: opening, 135: insulating layer, 139[1]: insulating layer, 139[2]: insulating layer, 139[n]: insulating layer, 139: insulating layer, 141f: conductive film, 141: conductive layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 7 15: driving circuit layer, 716: memory layer, 717: memory unit, 718[1]: memory block, 718[N]: memory block, 718: memory block, 720: memory device, 721L1: memory array, 721L2: memory array, 721L3: memory array, 721: memory array, 722: driving circuit, 723[1]: memory sub-array, 723[R]: memory sub-array, 723: memory sub-array, 724: word line driver, 725: column driver, 726: sense amplifier driver, 727: data driver, 728: memory controller, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 7 35: semiconductor device, 736: sub-sense circuit, 737: switch circuit, 741a: memory cell, 741b: memory cell, 741c: memory cell, 741d: memory cell, 741[1]: memory cell, 741[2]: memory cell, 741[n]: memory cell, 741: memory cell, 751: sense circuit, 752: switch circuit, 753: precharge circuit, 754: precharge circuit, 755: amplifier circuit, 756: precharge circuit, 761: power switch, 762: power switch, 771: peripheral circuit, 772: control circuit, 773: voltage generation circuit, 781: peripheral circuit, 782: row decoder, 783: row driver, 784: column decoder, 78 5: column driver, 786: data driver, 787: input circuit, 788: output circuit, 810: semiconductor device, 830: backup circuit, 831[1]: holding circuit, 831[2]: holding circuit, 831[3]: holding circuit, 831[4]: holding circuit, 831[G]: holding circuit, 831: holding circuit, 850: scan flip-flop circuit, 851: selector circuit, 852: flip-flop circuit, 900: electronic computer, 910: processing unit, 911: arithmetic unit, 912: control unit, 913: register unit, 914: register unit, 915: scan flip-flop, 916: backup memory, 920: storage unit, 921: memory array unit, 922: control control unit, 923: memory block, 924: memory unit, 925: memory cell, 926: sense amplifier, 930: control unit, 933: layer, 940L1: connection electrode, 940L2: connection electrode, 940L3: connection electrode, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 971: bus line, 982[1]: layer, 982[L]: layer, 982: layer, 983[1]: layer, 983[H]: layer, 983: layer, 984[1]: layer, 984[2]: layer, 984[K]: layer, 984[n]: layer, 984: layer, 985: layer, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller , 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button Tan, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: storage, 7004: storage area network

Claims

a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer;
the second transistor and the capacitor are provided on and overlap the first transistor,
the first transistor and the second transistor each have a source electrode and a drain electrode located at different heights with respect to a substrate surface;
the first insulating layer is provided between a source electrode and a drain electrode of the first transistor and has a first opening reaching one of the source electrode or the drain electrode of the first transistor;
the other of the source electrode and the drain electrode of the first transistor is provided on the first insulating layer;
the semiconductor layer of the first transistor has a region in contact with an upper surface of one of the source electrode or the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the other of the source electrode or the drain electrode of the first transistor in the first opening, and an upper surface of the other of the source electrode or the drain electrode of the first transistor;
a gate insulating layer of the first transistor is provided on and in contact with a semiconductor layer of the first transistor;
a gate electrode of the first transistor is provided on a gate insulating layer of the first transistor so as to have a region overlapping with a semiconductor layer of the first transistor, and has a function as one of a source electrode or a drain electrode of the second transistor and a function as one electrode of the capacitance;
the second insulating layer is provided between a source electrode and a drain electrode of the second transistor and has a second opening reaching a gate electrode of the first transistor;
the other of the source electrode and the drain electrode of the second transistor is provided on the second insulating layer;
the semiconductor layer of the second transistor has a region in contact with an upper surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, a side surface of the other of the source electrode or drain electrode of the second transistor in the second opening, and an upper surface of the other of the source electrode or drain electrode of the second transistor;
a gate insulating layer of the second transistor is provided on and in contact with a semiconductor layer of the second transistor;
a gate electrode of the second transistor is provided on a gate insulating layer of the second transistor so as to have a region overlapping with a semiconductor layer of the second transistor;
the dielectric layer of the capacitor is provided on a gate electrode of the first transistor;
the other electrode of the capacitor has a region overlapping with the gate electrode of the first transistor, and is provided on the dielectric layer of the capacitor with a gap between it and the second opening in a plan view;
Semiconductor device.
In claim 1,
At least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is a transistor including a metal oxide.
Semiconductor device.
In claim 1 or 2,
a side surface of the semiconductor layer of the first transistor and a side surface of the other of the source electrode or the drain electrode of the first transistor have a region that is substantially flush with each other;
a side surface of the semiconductor layer of the second transistor and a side surface of the other of the source electrode or the drain electrode of the second transistor have a region that is substantially flush with each other;
Semiconductor device.
In claim 1 or 2,
an end of the other electrode of the capacitor that does not face the first opening is positioned outside an end of the gate electrode of the first transistor;
Semiconductor device.
In claim 1 or 2,
the other electrode of the capacitor is provided at two locations, that is, on a first side end of the gate electrode of the first transistor and on a second side end opposite to the first side end;
Semiconductor device.
In claim 1 or 2,
the other electrode of the capacitor has a region overlapping an upper surface of the gate electrode of the first transistor so as to surround the second opening;
Semiconductor device.
In claim 1 or 2,
the dielectric layer of the capacitor comprises any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, and a nitride having silicon and hafnium;
Semiconductor device.
In claim 1 or 2,
the dielectric layer of the capacitor comprises any of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium tantalate bismuthate, bismuth ferrite, or barium titanate;
Semiconductor device.
In claim 1 or 2,
The first insulating layer and the second insulating layer each include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate, and acrylic.
Semiconductor device.
forming a first conductive layer;
forming a first insulating layer and a first conductive film on the first conductive layer;
forming a second conductive layer from the first conductive film by processing the first insulating layer and the first conductive film; and forming a first opening in the first conductive film and the first insulating layer, the first opening reaching the first conductive layer;
processing the second conductive layer to form a third conductive layer;
forming a first metal oxide film in contact with an upper surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the third conductive layer in the first opening, and an upper surface of the third conductive layer;
forming a first semiconductor layer by processing the first metal oxide film so as to have a region overlapping with the first opening;
forming a second insulating layer in contact with an upper surface of the first semiconductor layer;
forming a second conductive film on the second insulating layer;
forming a fourth conductive layer by processing the second conductive film so as to have a region overlapping with the first semiconductor layer;
forming a third insulating layer on the fourth conductive layer and on the second insulating layer;
forming a third conductive film on the third insulating layer;
forming a fifth conductive layer by processing the third conductive film so as to have a region overlapping with the fourth conductive layer;
forming a fourth insulating layer and a fourth conductive film on the fifth conductive layer and the third insulating layer;
forming a sixth conductive layer from the fourth conductive film by processing the fourth insulating layer and the fourth conductive film; and forming a second opening in the fourth conductive film and the fourth insulating layer, the second opening reaching the fourth conductive layer;
processing the sixth conductive layer to form a seventh conductive layer;
forming a second metal oxide film in contact with an upper surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the seventh conductive layer in the second opening, and an upper surface of the seventh conductive layer;
forming a second semiconductor layer by processing the second metal oxide film so as to have a region overlapping with the second opening;
forming a fifth insulating layer in contact with an upper surface of the second semiconductor layer;
forming a fifth conductive film on the fifth insulating layer;
forming an eighth conductive layer by processing the fifth conductive film so as to have a region overlapping with the second semiconductor layer;
A method for manufacturing a semiconductor device.
forming a first conductive layer;
forming a first insulating layer and a first conductive film on the first conductive layer;
forming a second conductive layer from the first conductive film by processing the first insulating layer and the first conductive film; and forming a first opening in the first conductive film and the first insulating layer, the first opening reaching the first conductive layer;
forming a first metal oxide film in contact with an upper surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and an upper surface of the second conductive layer;
forming a first semiconductor layer by processing the first metal oxide film so as to have a region overlapping with the first opening;
forming a third conductive layer by processing the second conductive layer so as to have a region overlapping with the first semiconductor layer;
forming a second insulating layer in contact with an upper surface of the first semiconductor layer;
forming a second conductive film on the second insulating layer;
forming a fourth conductive layer by processing the second conductive film so as to have a region overlapping with the first semiconductor layer;
forming a third insulating layer on the fourth conductive layer and on the second insulating layer;
forming a third conductive film on the third insulating layer;
forming a fifth conductive layer by processing the third conductive film so as to have a region overlapping with the fourth conductive layer;
forming a fourth insulating layer and a fourth conductive film on the fifth conductive layer and the third insulating layer;
forming a sixth conductive layer from the fourth conductive film by processing the fourth insulating layer and the fourth conductive film; and forming a second opening in the fourth conductive film and the fourth insulating layer, the second opening reaching the fourth conductive layer;
forming a second metal oxide film in contact with an upper surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth insulating layer in the second opening, a side surface of the sixth conductive layer in the second opening, and an upper surface of the sixth conductive layer;
forming a second semiconductor layer by processing the second metal oxide film so as to have a region overlapping with the second opening;
forming a seventh conductive layer by processing the sixth conductive layer so as to have a region overlapping with the second semiconductor layer;
forming a fifth insulating layer in contact with an upper surface of the second semiconductor layer;
forming a fifth conductive film on the fifth insulating layer;
forming an eighth conductive layer by processing the fifth conductive film so as to have a region overlapping with the second semiconductor layer;
A method for manufacturing a semiconductor device.
A storage unit and a processing unit are included,
the storage unit includes a storage device and a sense amplifier;
The processing unit has a CPU, an MPU, or a GPU,
the sense amplifier and the processing unit are disposed on a first layer;
the memory device is disposed on a second layer and includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer;
The second layer is provided on the first layer,
the second transistor and the capacitor are provided on and overlap the first transistor,
the first transistor and the second transistor each have a source electrode and a drain electrode located at different heights with respect to a substrate surface;
the first insulating layer is provided between a source electrode and a drain electrode of the first transistor and has a first opening reaching one of the source electrode or the drain electrode of the first transistor;
the other of the source electrode and the drain electrode of the first transistor is provided on the first insulating layer;
the semiconductor layer of the first transistor has a region in contact with an upper surface of one of the source electrode or the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the other of the source electrode or the drain electrode of the first transistor in the first opening, and an upper surface of the other of the source electrode or the drain electrode of the first transistor;
a gate insulating layer of the first transistor is provided on and in contact with a semiconductor layer of the first transistor;
a gate electrode of the first transistor is provided on a gate insulating layer of the first transistor so as to have a region overlapping with a semiconductor layer of the first transistor, and has a function as one of a source electrode or a drain electrode of the second transistor and a function as one electrode of the capacitance;
the second insulating layer is provided between a source electrode and a drain electrode of the second transistor and has a second opening reaching a gate electrode of the first transistor;
the other of the source electrode and the drain electrode of the second transistor is provided on the second insulating layer;
the semiconductor layer of the second transistor has a region in contact with an upper surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, a side surface of the other of the source electrode or drain electrode of the second transistor in the second opening, and an upper surface of the other of the source electrode or drain electrode of the second transistor;
a gate insulating layer of the second transistor is provided on and in contact with a semiconductor layer of the second transistor;
a gate electrode of the second transistor is provided on a gate insulating layer of the second transistor so as to have a region overlapping with a semiconductor layer of the second transistor;
the dielectric layer of the capacitor is provided on a gate electrode of the first transistor;
the other electrode of the capacitor has a region overlapping with the gate electrode of the first transistor, and is provided on the dielectric layer of the capacitor with a gap between it and the second opening in a plan view;
Semiconductor device.
In claim 12,
At least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is a transistor including a metal oxide.
Semiconductor device.
In claim 12 or 13,
a side surface of the semiconductor layer of the first transistor and a side surface of the other of the source electrode or the drain electrode of the first transistor have a region that is substantially flush with each other;
a side surface of the semiconductor layer of the second transistor and a side surface of the other of the source electrode or the drain electrode of the second transistor have a region that is substantially flush with each other;
Semiconductor device.
In claim 12 or 13,
an end of the other electrode of the capacitor that does not face the first opening is positioned outside an end of the gate electrode of the first transistor;
Semiconductor device.
In claim 12 or 13,
the other electrode of the capacitor is provided at two locations, that is, on a first side end of the gate electrode of the first transistor and on a second side end opposite to the first side end;
Semiconductor device.
In claim 12 or 13,
the other electrode of the capacitor has a region overlapping an upper surface of the gate electrode of the first transistor so as to surround the second opening;
Semiconductor device.
In claim 12 or 13,
the dielectric layer of the capacitor comprises any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, and a nitride having silicon and hafnium;
Semiconductor device.
In claim 12 or 13,
the dielectric layer of the capacitor comprises any of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium tantalate bismuthate, bismuth ferrite, or barium titanate;
Semiconductor device.
In claim 12 or 13,
The first insulating layer and the second insulating layer each include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate, and acrylic.
Semiconductor device.