WO2024140504A1 - Memory array and preparation method, storage circuit and read-write method, and electronic device - Google Patents

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a memory array and a preparation method, a storage circuit and a read-write method, and an electronic device, which are used for improving the storage density of a memory. The memory array comprises a plurality of memory cells. Each of the plurality of memory cells comprises a transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor; the transistor comprises a conductive gate, as well as a first doped region and a second doped region which are adjacently arranged; the conductive gate is located above a gap between the first doped region and the second doped region; the first doped region and the second doped region are a source doped region and a drain doped region; a first end of the first ferroelectric capacitor is coupled to the conductive gate, and a second end of the first ferroelectric capacitor is used for receiving a signal of a word line; a first end of the second ferroelectric capacitor is coupled to the first doped region, and a second end of the second ferroelectric capacitor is used to communicate signals with a bit line. The described memory array is applicable in a ferroelectric memory.

Description

Storage array and preparation method, storage circuit and reading and writing method, electronic device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 29, 2022, with application number 202211705791.9 and application name “Memory Array and Preparation Method, Storage Circuit and Reading and Writing Method, Electronic Device”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a storage array and a preparation method thereof, a storage circuit and a reading and writing method thereof, and an electronic device.

Background technique

Memory is a device used to store information. Usually, information is digitized and then stored in electrical, magnetic or optical media. Ferroelectric random access memory (FRAM) is a new type of memory that has the advantage of non-volatility over traditional dynamic random access memory (DRAM) or static random access memory (SRAM), and is increasingly being used.

However, the storage density of the memory itself will greatly affect the market prospects of the memory.

Summary of the invention

Embodiments of the present application provide a storage array and a preparation method, a storage circuit and a reading and writing method, and an electronic device for increasing the storage density of a memory.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect of an embodiment of the present application, a memory array is provided, the memory array comprising a plurality of memory cells. Each of the plurality of memory cells comprises a transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor; the transistor comprises a conductive gate and a first doped region and a second doped region disposed adjacently; the conductive gate is located above a gap between the first doped region and the second doped region; for example, the first doped region and the second doped region are mutually a source doped region and a drain doped region; the first end of the first ferroelectric capacitor is coupled to the conductive gate, and the second end of the first ferroelectric capacitor is used to receive a signal of a word line. The first end of the second ferroelectric capacitor is coupled to the first doped region, and the second end of the second ferroelectric capacitor is used to communicate a signal with a bit line.

In the memory array provided by the embodiment of the present application, the transistor included in each memory cell is coupled to two ferroelectric capacitors, the conductive gate is coupled to the first ferroelectric capacitor, and the first doped region is coupled to the second ferroelectric capacitor. Therefore, the number of bits of each memory cell is greater than 1, which can increase the storage density of the memory cell. Thus, the capacity of the memory array can be increased without increasing the area of the memory array.

In a possible implementation manner, the first ferroelectric capacitor and the second ferroelectric capacitor are located on a side of the conductive gate away from the first doped region and the second doped region.

The first ferroelectric capacitor and the second ferroelectric capacitor are both located above the transistor. Compared with the manufacturing process of FeRAM, the preparation of the first ferroelectric capacitor and the second ferroelectric capacitor are both located in the back-end process, which will not increase the process flow and process difficulty too much. Compared with the manufacturing process of FeFET, the preparation of the first ferroelectric capacitor and the second ferroelectric capacitor in the embodiment of the present application does not need to be mixed in the front-end process, and the process flow is highly compatible with the CMOS logic part. In other words, the storage array provided in the embodiment of the present application can increase the capacity of the storage array without increasing the process difficulty, process cost, and the number of transistors in the storage unit.

In a possible implementation, the first ferroelectric capacitor and the second ferroelectric capacitor are formed synchronously (in the same process step), thereby reducing process difficulty and process cost.

In a possible implementation manner, the second doped region is used to receive a signal of a plate line.

In a possible implementation, the storage array further includes a first wiring layer, and the first ferroelectric capacitor and the second ferroelectric capacitor are arranged on a side of the first wiring layer away from the transistor. By arranging one or more first wiring layers between the first ferroelectric capacitor and the second ferroelectric capacitor and the transistor, the interference of the first ferroelectric capacitor and the second ferroelectric capacitor on the transistor can be reduced, thereby improving Reading accuracy.

In a possible implementation, the storage array further includes a second wiring layer; the first ferroelectric capacitor and the second ferroelectric capacitor are located between the second wiring layer and the first wiring layer, and the second wiring layer is arranged adjacent to the first wiring layer. In this way, it is possible to avoid wasting metal wiring in the wiring layer that is crossed due to the first ferroelectric capacitor and the second ferroelectric capacitor being arranged across the wiring layer.

In a possible implementation, the number of bits of the storage unit is 2 bits or log ₂ 3 bits. The number of bits of each storage unit is greater than 1, which can increase the storage density of the storage array.

According to a second aspect of the embodiment of the present application, a storage circuit is provided, including: a plurality of storage branches, each of the plurality of storage branches includes a transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor; the transistor includes a control electrode, a first input-output electrode, and a second input-output electrode; a first end of the first ferroelectric capacitor is coupled to the control electrode, and a second end of the first ferroelectric capacitor is used to receive a signal of a word line; a first end of the second ferroelectric capacitor is coupled to the first input-output electrode, and a second end of the second ferroelectric capacitor is used to communicate a signal with a bit line.

In the storage circuit provided by the embodiment of the present application, the transistor included in each storage branch is coupled to two ferroelectric capacitors, the control electrode is coupled to the first ferroelectric capacitor, and the first input-output electrode is coupled to the second ferroelectric capacitor. Therefore, the number of bits of each storage branch is greater than 1. Thus, the storage density of the storage circuit can be increased without increasing the area of the storage array.

In a possible implementation, the second input-output pole is used to receive a signal of a plate line.

In one possible implementation, the first input-output electrode and the second input-output electrode include a first doping region and a second doping region that are adjacent to each other, for example, the first doping region and the second doping region are each other's source doping region and drain doping region; the control electrode includes a conductive gate, and the conductive gate is located above the gap between the first doping region and the second doping region.

In a possible implementation, the first ferroelectric capacitor and the second ferroelectric capacitor are located at a conductive gate away from the first doping region and the second doping region.

In one possible implementation, the first ferroelectric capacitor and the second ferroelectric capacitor are formed simultaneously (in the same process flow step).

In one possible implementation, the storage circuit also includes a first wiring layer, and the first ferroelectric capacitor and the second ferroelectric capacitor are arranged on the side of the first wiring layer away from the transistor, the first ferroelectric capacitor is coupled to the control electrode via the first wiring layer, and the second ferroelectric capacitor is coupled to the first input and output electrode via the first wiring layer.

In a possible implementation, the memory array further includes a second wiring layer; the first ferroelectric capacitor and the second ferroelectric capacitor are located between the second wiring layer and the first wiring layer, and the second wiring layer is disposed adjacent to the first wiring layer.

According to a third aspect of the embodiments of the present application, a memory is provided, comprising: a controller and a storage array according to any one of the first aspects coupled to the controller.

In a possible implementation, the memory further includes a charge detection circuit; the charge detection circuit is coupled to the storage cells of the storage array and is used to detect the amount of charge output by the storage cells.

In a possible implementation, the memory further includes a current detection circuit; the current detection circuit is coupled to the memory cells of the memory array and is used to detect the current output by the memory cells.

According to a fourth aspect of the embodiments of the present application, a memory is provided, comprising: a controller and the storage circuit of any one of the second aspects coupled to the controller.

In a possible implementation, the memory further includes a charge detection circuit; the charge detection circuit is coupled to a storage branch of the storage circuit and is used to detect the amount of charge output by the storage branch.

In a possible implementation, the memory further includes a current detection circuit; the current detection circuit is coupled to a storage branch of the storage circuit and is used to detect a current output by the storage branch.

According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising: a circuit board and a memory, wherein the circuit board and the memory are coupled; and the memory comprises the memory of any one of the third aspect or any one of the fourth aspect.

According to a sixth aspect of the embodiments of the present application, a method for preparing a memory array is provided, wherein the memory array includes a plurality of memory cells; the method for preparing the memory array includes: forming a transistor and forming a first ferroelectric capacitor and a second ferroelectric capacitor to form a memory cell; wherein the memory cell includes a conductive gate and a first doped region and a second doped region disposed adjacent to each other; the conductive gate is located above a gap between the first doped region and the second doped region; a first end of the first ferroelectric capacitor is coupled to the conductive gate, and a second end of the first ferroelectric capacitor is used to receive a signal of a word line; a first end of the second ferroelectric capacitor is coupled to the first doped region, and a second end of the second ferroelectric capacitor is used to receive a signal of a word line; The memory array provided by the embodiment of the present application can be formed by using the existing ferroelectric memory process, which has mature technology and low process difficulty.

In one possible implementation, forming a first ferroelectric capacitor and a second ferroelectric capacitor includes: forming the first ferroelectric capacitor and the second ferroelectric capacitor on the side of the conductive gate away from the first doped region and the second doped region. The first ferroelectric capacitor and the second ferroelectric capacitor are both located above the transistor. Compared with the manufacturing process of FeRAM, the preparation of the first ferroelectric capacitor and the second ferroelectric capacitor are both located in the back-end process, which will not increase the process flow and process difficulty too much. Compared with the manufacturing process of FeFET, the preparation of the first ferroelectric capacitor and the second ferroelectric capacitor in the embodiment of the present application does not need to be mixed in the front-end process, and the process flow is highly compatible with the CMOS logic part.

In a possible implementation, the first ferroelectric capacitor and the second ferroelectric capacitor are formed simultaneously (in the same process step), thereby simplifying the manufacturing process.

In a possible implementation, the memory array further includes a first wiring layer; and the preparation method further includes: before forming the first ferroelectric capacitor and the second ferroelectric capacitor, forming the first wiring layer on the transistor.

In the seventh aspect of the embodiment of the present application, a method for reading and writing a storage circuit is provided, wherein the storage circuit includes the storage circuit of any one of the second aspects; the method for reading and writing includes: in the writing stage: when writing data to the first ferroelectric capacitor, applying a reference ground voltage to the first input and output pole and the second input and output pole of the transistor; applying a first voltage to the control pole of the transistor to write the first data; applying a second voltage to the control pole to write the second data; when writing data to the second ferroelectric capacitor, applying a reference ground voltage to the control pole and the second input and output pole; applying a third voltage to the first input and output pole to write the first data; applying a fourth voltage to the first input and output pole to write the second data. In the reading stage: applying a reference ground voltage to the second input and output pole, applying a reference voltage to the control pole, applying a read voltage (which can be a positive voltage or a negative voltage) to the first input and output pole, and reading the signal of the first input and output pole. In the data holding stage: applying a reference ground voltage to the control pole, the first input and output pole, and the second input and output pole to hold the storage of the storage circuit. In the reading and writing method of the storage circuit provided by the embodiment of the present application, during the reading and writing operation, the information stored in the storage branch of more than 1 bit can be completed by writing in batches and reading once, without multiple readings. Compared with splicing two storage units into a storage unit with a bit number greater than 1 in the related art and then reading and writing it twice, the reading and writing process of the storage branch in the embodiment of the present application is simple and has a fast response speed.

In a possible implementation, the first data and the second data are “logic 1” and “logic 0” to each other.

In a possible implementation manner, the absolute value of the first voltage, the third voltage, the second voltage, and the absolute value of the fourth voltage are greater than the coercive voltage.

In a possible implementation, the reference voltage is smaller than the coercive voltage, and the absolute value of the read voltage is larger than the coercive voltage.

In a possible implementation manner, the first voltage and the second voltage have opposite polarities; and the third voltage and the fourth voltage have opposite polarities.

In an eighth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes computer instructions. When the computer instructions are executed on a device, the device executes a reading and writing method as described in any one of the sixth aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an electronic device according to an embodiment of the present application;

FIG2 is a circuit diagram of a storage unit provided in an embodiment of the present application;

FIG3 is a graph showing the relationship between polarization intensity and applied electric field provided in an embodiment of the present application;

FIG4 is another diagram showing the relationship between polarization intensity and applied electric field provided in an embodiment of the present application;

FIG5A is a schematic diagram of the structure of a storage unit provided in an embodiment of the present application;

FIG5B is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application;

FIG6A is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application;

FIG6B is a schematic diagram of a topology of a storage branch provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of a preparation process of a storage array provided in an embodiment of the present application;

8 to 14 are schematic diagrams of a preparation process of a storage array provided in an embodiment of the present application;

FIG15A is a schematic diagram of a correspondence relationship between storage data and read/write data provided in an embodiment of the present application;

FIG. 15B is a schematic diagram of another correspondence relationship between storage data and read/write data provided in an embodiment of the present application.

Detailed ways

The technical solution in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described The embodiments described are only part of the embodiments of the present application, rather than all the embodiments.

In the following, the terms "second", "first", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

In the embodiments of the present application, "and/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. Below, some terms in the embodiments of the present application are explained.

Memory: In a chip, memory is a memory component used to store programs and data information. The information stored in common memory is stored in the chip in binary units, that is, it is stored in the memory as "logic 0" or "logic 1". In physical devices, it is usually achieved by high or low voltage, large or small resistance, more or less charge, etc.

Bit: is the smallest unit of information stored in a memory. n bits can represent 2 ⁿ states. For example, one bit can represent two states, 0 or 1. Two bits can represent four states, 00, 01, 10, 11, and so on. In other words, if a memory stores physical information in m states, it is a log ₂ m-bit memory.

Volatile memory and non-volatile memory (NVM): According to whether the stored signal still exists after the external power supply of the chip is removed, the memory can be divided into volatile memory and non-volatile memory. Volatile memory is represented by static random access memory (SRAM) or dynamic random access memory (DRAM), and the storage of information requires continuous external power supply. When there is no external power supply, the stored information will no longer exist. Non-volatile memory is represented by traditional read-only memory (ROM) and flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor, FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM) and phase-change random access memory (PCRAM). These non-volatile memories all use their unique physical principles to achieve the characteristic of not losing information when power is off.

Coercive voltage (Vc): equal to coercive electric field (Ec) * thickness of ferroelectric layer.

The embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Among them, consumer electronic products are, for example, mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products are, for example, smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are, for example, vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc. Financial terminal products are, for example, automated teller machines (ATMs), self-service terminals, etc. Communication electronic products such as servers, storage devices, radars, base stations and other communication equipment.

An electronic device is shown in FIG1 , and the electronic device 1 includes components such as a memory 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art can understand that the architecture of the electronic device 1 shown in FIG1 does not constitute a limitation on the electronic device 1, and the electronic device 1 may include more or fewer components than those shown in FIG1, or may be composed of Some of the components shown in FIG. 1 may be combined, or the components may be arranged differently from those shown in FIG. 1 .

The memory 11 is used to store software programs and modules. The memory 11 mainly includes a program storage area and a data storage area. The program storage area can store and back up an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc.

The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and/or modules stored in the memory 11, and calling data stored in the memory 11, it executes various functions of the electronic device 1 and processes data, thereby monitoring the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application programs, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12. The above-mentioned application processor may be, for example, a central processing unit (CPU).

The input device 13 is used to receive input digital or character information, and to generate key signal input related to user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. A touch screen, also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen), and drive corresponding connection devices according to a pre-set program.

The output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the memory 11. For example, the output device 14 outputs a sound signal or a video signal.

As a new type of memory, ferroelectric memory has become one of the mainstream memories due to its characteristics such as non-volatility of stored data.

1 , the memory 11 includes a controller and a storage array or a storage circuit. The controller is used to control the reading and writing of the storage array and the storage circuit.

The memory array includes a plurality of memory cells arranged in an array, and the storage density of the memory cells 200 directly affects the storage density of the memory array.

Regarding the structure of the memory cell, in some embodiments, as shown in FIG. 2 , the memory cell 200 has a 1T1C (1-transistor-1-capacitor) structure, that is, the memory cell 200 includes a transistor T and a ferroelectric capacitor C. The source of the transistor T is electrically connected to a plate line (PL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the conductive gate is electrically connected to a word line (WL), and the other electrode of the ferroelectric capacitor C is electrically connected to a bit line (BL). The circuit architecture of the memory cell 200 in the embodiments of the present application is not limited thereto.

The transistor T may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET or MOS), which is a basic unit device of integrated circuits. According to the type of carriers, it is divided into N-channel type (NMOS) and P-channel type (PMOS).

The transistor T mainly includes a control electrode (e.g., a conductive gate), a first input-output electrode (e.g., a source electrode), and a second input-output electrode (e.g., a drain electrode). As shown in FIG2 , for example, the control electrode of the transistor T is coupled to the word line WL, the first input-output electrode of the transistor T is coupled to the ferroelectric capacitor C, and the second input-output electrode of the transistor T is coupled to the plate line PL. By changing the voltage of the control electrode, the resistance between the first input-output electrode and the second input-output electrode is controlled, and then the current flowing through the first input-output electrode and the second input-output electrode is controlled, so as to realize the switching characteristics of the transistor T.

Taking transistor T as an N-type transistor as an example, the voltage of the transition between the on state and the off state is called the threshold voltage (Vt). When the control electrode voltage is greater than the threshold voltage, the transistor T is turned on, a current flows between the first input-output electrode and the second input-output electrode, and the corresponding storage unit 200 is selected. When the control electrode voltage is less than the threshold voltage, the transistor T is turned off, the current flows between the first input-output electrode and the second input-output electrode to almost zero, and the corresponding storage unit 200 is not selected.

Of course, transistor T can also be a P-type transistor. N-type transistor is a high-on low-off transistor, and P-type transistor is a low-on high-off transistor. The turn-on voltage received by the N-type transistor and P-type transistor controllers is opposite to the threshold voltage. When the storage cell 200 is selected, an electric field (voltage) is applied to the ferroelectric capacitor C. At this time, the polarized charges inside the ferroelectric material move relatively, and the electric polarization intensity is generated.

As shown in FIG3 , the relationship between the change of the polarization intensity (polarization, P) of an ordinary dielectric and the change of the external electric field E is a linear relationship. When the external electric field is 0, the polarization intensity P is 0. As shown in FIG4 , when a ferroelectric material is used as a dielectric, the relationship between the change of the polarization intensity P and the change of the external electric field E is nonlinear. In the art, the change of the polarization intensity P of a ferroelectric dielectric with the external electric field E is called a hysteresis loop.

In Figure 4, two variables can be defined, remnant polarization (Pr) and coercive electric field Ec. The remnant polarization Pr is the intersection of the hysteresis loop and the vertical axis (P axis). There are two intersections of +Pr and -Pr in the hysteresis loop, which are used to indicate that when the external electric field E is 0, the remnant polarization Pr may be positive or negative. The sign of the polarization P can be used to define whether the stored information is 0 or 1. The coercive electric field Ec is the intersection of the hysteresis loop and the horizontal axis (E axis). There are two intersections of +Ec and -Ec in the hysteresis loop Ec. The stored information can be changed by applying a positive or negative electric field with an absolute value greater than Ec.

The hysteresis loop moves according to the following rules: When the applied positive electric field is greater than Ec, the polarization intensity P is positive and is in the first quadrant. As the applied electric field decreases, the polarization intensity P decreases accordingly. When the applied electric field decreases to 0, the polarization intensity P is +Pr. Then, when the applied electric field changes direction (changes to negative), the polarization intensity P starts to decrease from +Pr and enters the second quadrant. If the electric field (absolute value) is less than Ec, the applied electric field disappears and the polarization intensity P returns to +Pr. When the applied electric field (negative) is greater than Ec and continues to increase, the polarization intensity P will change from positive to negative and enter the third quadrant. At this point, the reversal of the polarity of the ferroelectric material from positive to negative is completed. The reversal of the polarity of the ferroelectric material from negative to positive is similar. If the applied positive electric field does not exceed Ec, then when the electric field disappears, the polarization intensity P is -Pr. If the applied positive electric field exceeds Ec, it enters the first quadrant from the fourth quadrant.

The non-volatility of ferroelectric materials comes from the hysteresis loop. When the external electric field disappears, the polarization intensity P of the material is either in the +Pr or -Pr state, thus achieving the characteristic of not losing information when the power is off.

Regarding the structures of the transistor T and the ferroelectric capacitor C, in some technologies, as shown in FIG. 5A , a structure of a memory cell 200 included in a FeRAM is exemplified.

The memory cell 200 includes a transistor T (metal oxide field effect transistor) and a ferroelectric capacitor C. The transistor T includes a conductive gate G, a source doping region S and a drain doping region D. The ferroelectric capacitor C is coupled to the drain doping region D of the transistor T.

During the information writing process, the source doped region S and the conductive gate G are grounded, and a voltage with an absolute value greater than the coercive voltage Vc is applied to the drain doped region D to flip the polarity of the ferroelectric capacitor C. If the polarity of the applied voltage is positive (negative), the polarity of the information stored in the ferroelectric material is upward (downward).

When information needs to be retained (not in the reading or writing process), a reference ground voltage is applied to the conductive gate G, the source doping region S, and the drain doping region D. Due to the hysteresis loop, the ferroelectric material has +Pr or -Pr, and the information is preserved.

In the process of reading information, a reference ground voltage is applied to the source doping area S, a voltage greater than the threshold voltage Vt is applied to the conductive gate G, and a forward voltage (greater than the coercive voltage Vc) is applied to the drain doping area D, so that the polarity of the ferroelectric capacitor C is forced to be flipped upward. If the polarity of the original stored information is upward, a small amount of charge will flow from the end of the drain doping area D. If the polarity of the original stored information is downward, a large amount of charge will flow from the end of the drain doping area D because the polarity of the ferroelectric capacitor C is flipped. The current flowing through the end of the drain doping area D is read by an external circuit to determine whether the originally stored information is 0 or 1. After the ferroelectric information is read, the originally stored information is destroyed because the reading process flips the polarity of the ferroelectric capacitor C to the upward direction, and the originally stored information needs to be written into the ferroelectric capacitor C again. This reading process is called "destructive reading".

Although the FeRAM shown in FIG. 5A can implement non-volatile storage, each storage unit 200 can only store 1 bit of information, and the density of the memory is relatively low.

In some other technologies, as shown in FIG. 5B , a structure of a memory cell 200 included in a FeFET is exemplified.

The memory cell 200 includes a transistor T (metal oxide field effect transistor) and a ferroelectric capacitor C. The transistor T includes a conductive gate G, a source doping region S and a drain doping region D. The ferroelectric capacitor C is coupled to the conductive gate G of the transistor T. The ferroelectric capacitor C is located on the conductive gate G near the source doping region S and the drain doping region D.

During the information writing process, a reference ground voltage is applied to the source doping region S and the drain doping region D, and a voltage with an absolute value greater than the coercive voltage Vc is applied to the conductive gate G to flip the polarity of the ferroelectric capacitor C. If the applied voltage polarity is positive (negative), the polarity of the information stored in the ferroelectric capacitor C is upward (downward).

When information needs to be retained (not in the reading or writing process), a reference ground voltage is applied to the conductive gate G, the source doping region S, and the drain doping region D. Due to the hysteresis loop, the ferroelectric material has +Pr or -Pr, and the information is preserved.

In the process of reading information, a reference ground voltage is applied to the source doping region S, and an appropriate reference voltage is applied to the conductive gate G. A reference voltage (Vref) is applied to the drain doping region D, and a read voltage (Vread) is applied to the drain doping region D. Due to the effect of ferroelectric polarity, the positive (negative) polarity will increase (decrease) the threshold voltage Vt of the transistor T accordingly. Under the appropriate reference voltage Vref, when the polarity of the ferroelectric capacitor is upward, the drain current (drain current, Id) is almost 0, and when the polarity of the ferroelectric capacitor is downward in another state, the drain current Id is not 0. By reading the size of the drain current Id, it is possible to determine whether the originally stored information is 0 or 1.

Although the FeFET shown in FIG5B can perform non-volatile storage, each memory cell 200 can only store 1 bit of information, and the density of the memory is relatively low. Moreover, the ferroelectric capacitor C is located below the conductive gate G, and the preparation of the ferroelectric capacitor C is mixed in the front end of line (FEOL) process of the complementary metal oxide semiconductor (Complementary, CMOS) preparation process, and the process flow has low compatibility with the CMOS logic part.

Based on this, an embodiment of the present application provides a storage unit, and the number of bits of the storage unit is greater than 1 bit. When the storage unit is applied to the storage array provided by the embodiment of the present application, the storage density of the storage array can be increased.

An embodiment of the present application provides a storage array, which can be applied to the memory 11 shown in FIG. 1 , for example.

The memory array includes a plurality of memory cells arranged on a substrate. The substrate may belong to the memory array or may not belong to the memory array.

For the sake of convenience, the accompanying drawings of the embodiments of the present application take a memory cell disposed on a substrate as an example to schematically illustrate the memory array provided by the embodiments of the present application. The structure of each of the multiple memory cells included in the memory array may be the same as the structure of the memory cell described in detail in the embodiments of the present application. Of course, the memory array may include memory cells of other structures on the basis of including the multiple memory cells illustrated in the embodiments of the present application, and the embodiments of the present application do not limit this.

Regarding the structure of the memory cell, as shown in FIG. 6A , the memory cell 200 includes a transistor T, a first ferroelectric capacitor C1 , and a second ferroelectric capacitor C2 .

The transistor comprises a conductive gate and a first doping region and a second doping region which are adjacently arranged. The conductive gate is located above a gap between the first doping region and the second doping region.

The material of the conductive gate can be, for example, conductive materials such as metal and polysilicon. The first doping region and the second doping region are mutually a source doping region and a drain doping region, and the first doping region and the second doping region can be, for example, both N-type doping regions or both P-type doping regions.

The conductive gate serves as a control electrode t1 of the transistor T, the drain doping region serves as a first input-output electrode t2 of the transistor T, and the source doping region serves as a second input-output electrode t3 of the transistor T.

The first end of the first ferroelectric capacitor C1 is coupled to the conductive gate, and the first end of the second ferroelectric capacitor C2 is coupled to the first doped region. In other words, the first ferroelectric capacitor C1 is coupled to the control electrode t1, and the second ferroelectric capacitor C2 is coupled to the first input-output electrode t2.

In the memory array provided by the embodiment of the present application, the transistor T included in each memory cell 200 is coupled to two ferroelectric capacitors, the conductive gate is coupled to the first ferroelectric capacitor C1, and the first doped region is coupled to the second ferroelectric capacitor C2. Therefore, the number of bits of each memory cell 200 is greater than 1, which can increase the storage density of the memory cell 200. Thus, the capacity of the memory array can be increased without increasing the area of the memory array.

The storage array provided in the embodiment of the present application can be topologically a storage circuit provided in the embodiment of the present application. As shown in FIG6B , the embodiment of the present application also provides a storage circuit, the storage circuit includes a plurality of storage branches 200 ′, each storage branch 200 ′ in the plurality of storage branches 200 ′ includes a transistor T, a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2.

The transistor T includes a control electrode t1, a first input-output electrode t2, and a second input-output electrode t3. The first end of the first ferroelectric capacitor C1 is coupled to the control electrode t1, and the second end of the first ferroelectric capacitor C1 is used to receive a signal of the word line WL. The first end of the second ferroelectric capacitor C2 is coupled to the first input-output electrode t2, and the second end of the second ferroelectric capacitor C2 is used to communicate a signal with the bit line BL.

In some embodiments, the storage branch 200' further includes a word line WL, a plate line PL and a bit line BL. The second input-output electrode t3 is coupled to the plate line PL, the second end of the first ferroelectric capacitor C1 is coupled to the word line WL, and the second end of the second ferroelectric capacitor C2 is coupled to the bit line BL.

In some embodiments, the first ferroelectric capacitor C1 is located on a side of the conductive gate G facing the channel region, and the second ferroelectric capacitor C2 is located on a side of the drain doping region D away from the substrate 300 .

In some other embodiments, as shown in FIG. 6A , the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are located on a side of the transistor T away from the substrate 300 .

The first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located on the side of the transistor T away from the substrate 300. Compared with the manufacturing process of FeRAM, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located in the back end of line (BEOL), which will not increase the process flow and process difficulty too much. Compared with the manufacturing process of FeFET, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the embodiment of the present application does not need to be mixed in the front end process FEOL, and the process flow is highly compatible with the CMOS logic part. In other words, the storage array provided in the embodiment of the present application can improve the storage density of the storage array without increasing the process difficulty, process cost, read and write complexity, and the number of transistors in the storage unit.

The following is a schematic illustration of the storage array and the method for manufacturing the same provided in the embodiments of the present application using specific examples.

The embodiment of the present application provides a method for preparing a memory array, wherein the memory array includes a plurality of memory cells 200, and the method for preparing the memory array includes:

A transistor T is formed and a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are formed to form the memory cell 200 .

The transistor T includes a conductive gate, a gate oxide layer, a channel region, and a first doped region and a second doped region disposed adjacent to each other, wherein the first doped region and the second doped region are mutually a source doped region and a drain doped region. The channel region is located between the first doped region and the second doped region, and the gate oxide layer is located between the conductive gate and the channel region. The first end of the first ferroelectric capacitor C1 is coupled to the conductive gate, and the first end of the second ferroelectric capacitor C2 is coupled to the first doped region.

In some embodiments, as shown in FIG. 7 , a method for preparing a memory array includes:

S10 , as shown in FIG. 8 , a transistor T is formed on a substrate 300 .

For example, the transistor T includes a complementary metal oxide semiconductor device (CMOS), a fin field-effect transistor (FinFET), etc.

FIG8 takes a transistor T including a CMOS as an example for illustration, and the transistor T includes a conductive gate G, a gate oxide layer, a channel region, and a first doping region and a second doping region that are adjacently arranged.

The first doping region and the second doping region are mutually the source doping region S and the drain doping region D. For example, if the first doping region is the source S doping region, then the second doping region is the drain D doping region. If the first doping region is the drain doping region D, then the second doping region is the source doping region S. In the embodiment of the present application, the first doping region is the drain doping region D and the second doping region is the source doping region S as an example for illustration.

The channel region is located between the first doping region (drain doping region D) and the second doping region (source doping region S), and the gate oxide layer is located between the conductive gate G and the channel region.

The material of the substrate 300 may be silicon, for example. A third doping region is further provided on the substrate 300. The source doping region S and the third doping region are N-type doping regions and P-type doping regions, respectively. The source doping region S and the drain doping region D are doping regions of the same type. When the source doping region S is an N-type doping region and the third doping region is a P-type doping region, the transistor T is an N-type transistor. When the source doping region S is a P-type doping region and the third doping region is an N-type doping region, the transistor T is a P-type transistor. The doping type of the channel region is the same as the doping type of the third doping region, or the portion of the third doping region between the source doping region S and the drain doping region D is used as the channel region of the transistor T.

In some embodiments, the transistor T includes a conductive gate G, a source doped region S, a drain doped region D, and a gate oxide layer, and further includes a sidewall located on the side of the conductive gate G, and the sidewall is used to block and protect the conductive gate.

The structure of the transistor T shown in FIG8 is only an illustration and is not intended to be limiting. Any method of forming the transistor T using the front-end FEOL process in the related art is applicable to step S10 of the embodiment of the present application.

S20 , as shown in FIG. 9 , a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are formed on a side of the transistor T away from the substrate 300 to form a memory cell 200 .

The first ferroelectric capacitor C is coupled to the conductive gate G, and the second ferroelectric capacitor C2 is coupled to the drain doping region D.

The memory array includes a plurality of memory cells 200 . The preparation of the memory array can be completed by forming the plurality of memory cells 200 on the substrate 300 simultaneously (in the same process step).

In some embodiments, the memory array further includes a multi-layer wiring layer, which is disposed on a side of the transistor T away from the substrate 300, and the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are disposed between the two wiring layers.

Then, in the process of preparing the storage array, the method for preparing the storage array further includes:

A plurality of wiring layers are formed on the side of the transistor T away from the substrate 300 ; wherein the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are formed between the two wiring layers.

The memory array includes multiple wiring layers, and the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can be located at any two wiring layers. Of course, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can be located between the same two wiring layers, for example, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located between the second wiring layer and the third wiring layer. The first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can also be located between two different wiring layers, for example, the first ferroelectric capacitor C1 is located between the third wiring layer and the fourth wiring layer. The second ferroelectric capacitor C2 is located between the fourth wiring layer and the fifth wiring layer.

In some embodiments, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are disposed between two adjacent wiring layers.

In this way, it is possible to avoid the waste of metal wiring of the wiring layer that is crossed due to the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 being arranged across the wiring layer. For example, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are arranged between the third wiring layer and the fifth wiring layer, which will waste the metal wiring of the fourth wiring layer.

In some embodiments, as shown in FIG10 , the multi-layer wiring layer in the ferroelectric memory array includes a first wiring layer P1 and a second wiring layer P2. One or more layers of the first wiring layer P1 are arranged between the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and the transistor T, and one or more layers of the second wiring layer P2 are arranged on the side of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 away from the transistor T.

FIG10 is a diagram showing an example in which a first wiring layer P1 is provided between the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and the transistor T, and a second wiring layer P2 is provided on the side of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 away from the transistor T. Then, the first wiring layer P1 can be used as the first wiring layer in the multi-layer wiring layer, and the second wiring layer P2 can be used as the top wiring layer in the multi-layer wiring layer.

A multi-layer first wiring layer P1 may be arranged between the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and the transistor T, and a multi-layer second wiring layer P2 may be arranged on the side of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 away from the transistor T. Then, the first wiring layer P1 can be used as the first wiring layer, the second wiring layer, ..., etc. in the multi-layer wiring layer, and the second wiring layer P2 can be used as the top wiring layer, the second top wiring layer, ..., etc. in the multi-layer wiring layer.

By providing one or more first wiring layers P1 between the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 and the transistor T, the interference of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 on the transistor can be reduced, thereby improving the reading accuracy.

Based on this, an exemplary method for preparing a ferroelectric memory array includes:

S21 . As shown in FIG. 11 , a first wiring layer P1 is formed on a side of the transistor T away from the substrate 300 .

The formation of the first wiring layer P1 means that the preparation of the memory array enters the back-end process of the CMOS. The first wiring layer P1 can be coupled to the transistor T through a contact layer (CT), for example.

The periphery of the via layer CT and the first wiring layer P1 is filled with dielectric layers (inter layer dielectrics, ILD).

The first wiring layer P1 includes a first routing line p1, a second routing line p2, and a third routing line p3, wherein the first routing line p1 is coupled to the conductive gate G, the second routing line p2 is coupled to the drain doping region D, and the third routing line p3 is coupled to the source doping region S. The shapes of the first routing line p1, the second routing line p2, and the third routing line p3 are not limited, and the shapes of the first routing line p1, the second routing line p2, and the third routing line p3 can realize signal transfer.

S22 , as shown in FIG. 12 , a first via hole v1 and a second via hole v2 are formed on a side of the first wiring layer P1 away from the substrate 300 .

For example, step S22 includes:

S221. Form a first dielectric film IMD1' located on the side of the first wiring layer P1 away from the substrate 300, and use a chemical mechanical polishing (CMP) process to flatten the top of the first dielectric film IMD1'.

S222, perform a first photolithography step to form a photoresist mask PH. The photoresist mask PH exposes the connecting vias above the first wiring p1 and the second wiring p2, and the rest is covered by photoresist.

S223, etching the portion of the first dielectric film IMD1' exposed by the photoresist mask PH, forming a first opening and a second opening on the first dielectric film IMD1', exposing the first wiring p1 and the second wiring p2 respectively, and forming a first dielectric layer (inter-metal dielectric, IMD1).

S224, removing the photoresist mask PH.

S225 , forming a via film V′, wherein the via film V′ fills the first opening and the second opening.

S226 , CMP is used to grind away the excess via film V′, leaving the portion located in the first opening and the second opening, thereby forming a first via hole v1 and a second via hole v2 .

The first via v1 is coupled to the conductive gate G through the first wiring p1, and the second via v2 is coupled to the drain doping region D through the second wiring p2.

If multiple first wiring layers P1 are provided between the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and the transistor T, step S21 and step S22 may be repeated multiple times before step S23 is started.

If a first wiring layer P1 is disposed between the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and the transistor T, step S21 and step S22 are performed once, and then step S23 is started.

S23 . As shown in FIG. 13 , a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are formed.

In some embodiments, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are formed simultaneously (in the same process flow step).

In this way, the preparation process of the memory array can be simplified. Compared with the related art which only includes one ferroelectric capacitor C, the memory array provided by the present application can increase the storage density of the memory array without increasing the process steps.

In other embodiments, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are formed separately.

Since the manufacturing process of ferroelectric capacitors is relatively mature, even if the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are formed separately, the process difficulty will not be excessively increased.

In some embodiments, as shown in FIG. 13 , the first ferroelectric capacitor C1 includes a first electrode 201 , a second electrode 202 and a first ferroelectric layer 203 , wherein the first ferroelectric layer 203 is located between the first electrode 201 and the second electrode 202 , and the first electrode 201 is coupled to a control electrode (eg, a conductive gate G).

The second ferroelectric capacitor C2 includes a third electrode 204 , a fourth electrode 205 and a second ferroelectric layer 206 . The second ferroelectric layer 206 is located between the third electrode 204 and the fourth electrode 205 . The third electrode 204 is coupled to the first input/output electrode (eg, the drain doping region D).

For example, the first electrode 201 , the second electrode 202 , and the first ferroelectric layer 203 are all parallel to the substrate 300 . The third electrode 204 , the fourth electrode 205 , and the second ferroelectric layer 206 are all parallel to the substrate 300 .

Alternatively, for example, the first electrode 201 surrounds a groove, and the second electrode 202 and the first ferroelectric layer 203 are located in the groove. Alternatively, the second electrode 202 surrounds a groove, and the first electrode 201 and the first ferroelectric layer 203 are located in the groove.

Similarly, the third electrode 204 surrounds a groove, and the fourth electrode 205 and the second ferroelectric layer 206 are located in the groove. Alternatively, the fourth electrode 205 surrounds a groove, and the third electrode 204 and the second ferroelectric layer 206 are located in the groove.

Of course, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can also be ferroelectric capacitors of any other structure, and the structures of ferroelectric capacitors in the related art are all applicable to the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the embodiment of the present application. In addition, the structures of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can be the same, and the structures of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can also be different, which is not limited in the embodiment of the present application.

For example, step S23 includes:

S231 , forming a first electrode film 201 ′, a ferroelectric film 203 ′ and a second electrode film 202 ′ on a side of the transistor T away from the substrate 300 .

S232, perform a second photolithography step to form a photoresist mask PH. The region where the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are to be formed is covered by the photoresist mask PH, and the rest of the region is exposed.

S233, etching the first electrode film 201', the ferroelectric film 203' and the second electrode film 202', leaving only the portions of the first electrode film 201', the ferroelectric film 203' and the second electrode film 202' covered by the photoresist, to form a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2.

The etching of the first electrode film 201 ′, the ferroelectric film 203 ′ and the second electrode film 202 ′ may be completed in the same etching process to simultaneously form the first electrode 201 , the third electrode 204 , the first ferroelectric layer 203 , the second ferroelectric layer 206 , the second electrode 202 and the fourth electrode 205 .

The first electrode film 201', the ferroelectric film 203' and the second electrode film 202' are etched, and the second electrode film 202' may be patterned first to form the second electrode 202 and the fourth electrode 205. The second electrode 202 and the fourth electrode 205 may be formed simultaneously, for example. Then the ferroelectric film 203' is patterned to form the first ferroelectric layer 203 and the second ferroelectric layer 206. The first ferroelectric layer 203 and the second ferroelectric layer 206 may be formed simultaneously, for example. Then the first electrode film 201' is patterned to form the first electrode 201 and the third electrode 204. The first electrode 201 and the third electrode 204 may be formed simultaneously, for example.

S234, removing the photoresist mask PH.

S24, as shown in FIG. 14, a second ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are formed on the side away from the substrate 300. Wiring layer P2.

For example, step S24 includes:

S241, forming a second dielectric film IMD2', and using a CMP process to planarize the top of the second dielectric film IMD2'.

S242, performing a third photolithography step to form a photoresist mask PH. The photoresist mask PH exposes the first ferroelectric capacitor C1, the second ferroelectric capacitor C2 and a portion above the third wiring p3.

S243, etching the second dielectric film IMD2' to form a plurality of openings on the second dielectric film IMD2' to form a second dielectric layer IMD2. The plurality of openings respectively expose the third wiring p3, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2.

S244, removing the photoresist mask PH.

S245. Form a second wiring film P2'.

S246, CMP smoothes out the excess second wiring film P2', leaving the portion located in the opening.

S247 , forming a second wiring layer P2 .

The process of forming the second wiring layer P2 may be the same as the process of forming the first wiring layer P1 , and reference may be made to the above description on the formation of the first wiring layer P1 .

In the case where the memory array includes multiple layers of the second wiring layer P2, step S24 may be repeatedly performed multiple times.

In some embodiments, as shown in Figure 14, the second wiring layer P2 includes a plate line PL, a word line WL and a bit line BL, the plate line PL is coupled to the source doping region S via a third routing p3, the word line WL is coupled to the second end of the first ferroelectric capacitor C1, and the bit line BL is coupled to the second end of the second ferroelectric capacitor C2.

Of course, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can also be formed asynchronously (in the same process flow step), and the process of forming the first ferroelectric capacitor C1 separately and the process of forming the second ferroelectric capacitor C2 separately are the same as the above-mentioned process of forming the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2.

In the embodiment of the present application, the single damascene process is used as an example to form the second wiring layer P2. The dual damascene process may also be used to form the second wiring layer P2, which is not limited in the embodiment of the present application.

In some embodiments, based on the structure of the storage unit 200 provided in the embodiments of the present application, the number of bits of the storage unit 200 may be 2 bits or log ₂ 3 bits.

In the embodiment of the present application, the transistor T of each storage unit 200 is coupled to two ferroelectric capacitors (the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2). Therefore, the number of bits of each storage unit 200 is greater than 1. Thus, the capacity of the storage array can be increased without increasing the area of the storage array. On this basis, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located on the side of the transistor T away from the substrate 300. Compared with the manufacturing process of FeRAM, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located in the back-end process BEOL, which will not increase the process flow and process difficulty too much. Compared with the manufacturing process of FeFET, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the embodiment of the present application does not need to be mixed in the front-end process FEOL, and the process flow is highly compatible with the CMOS logic part and the process cost is low. In other words, the storage array provided in the embodiment of the present application can increase the capacity of the storage array without increasing the process difficulty, process cost and the number of transistors in the storage unit.

The embodiment of the present application further provides a storage circuit, which includes a plurality of storage branches 200 ′. Each storage branch 200 ′ in the plurality of storage branches 200 ′ includes a transistor T, a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 .

The transistor T includes a control electrode t1 , a first input-output electrode t2 , and a second input-output electrode t3 . A first end of the first ferroelectric capacitor C1 is coupled to the control electrode t1 , and a first end of the second ferroelectric capacitor C2 is coupled to the first input-output electrode t2 .

In some embodiments, the storage branch 200' further includes a word line WL, a plate line PL and a bit line BL. The second input-output electrode t3 is coupled to the plate line PL, the second end of the first ferroelectric capacitor C1 is coupled to the word line WL, and the second end of the second ferroelectric capacitor C2 is coupled to the bit line BL.

In some embodiments, the first input-output electrode t2 and the second input-output electrode t3 are adjacently arranged first doped regions and second doped regions, the first doped regions and the second doped regions are each other's source doped regions S and drain doped regions D, the transistor T also includes a gate oxide layer and a channel region, the channel region is located between the first doped region and the second doped region, and the gate oxide layer is located between the control electrode and the channel region.

The structure of the transistor T in the storage branch 200 ′ may be the same as the structure of the transistor T illustrated in the above storage unit 200 , and reference may be made to the above related description. The control electrode in the transistor T may be understood as the conductive gate G in the transistor T.

In some embodiments, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the storage branch 200' are located far from the control electrode. Off the gate oxide side.

In some embodiments, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the storage branch 200 ′ are formed simultaneously (in the same process step) and are disposed in the same layer.

In some embodiments, the storage circuit also includes a first wiring layer P1, a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are arranged on the side of the first wiring layer P1 away from the transistor T, the first ferroelectric capacitor C1 is coupled to the control electrode t1 via the first wiring layer P1, and the second ferroelectric capacitor C2 is coupled to the first input-output electrode t2 via the first wiring layer P1.

By way of example, the storage circuit also includes a first wiring layer P1, a first ferroelectric capacitor C1 and a second ferroelectric capacitor C2 are arranged on a side of the first wiring layer P1 away from the transistor T, the first ferroelectric capacitor C1 is coupled to the conductive gate G via the first wiring layer P1, and the second ferroelectric capacitor C2 is coupled to the drain doped region D via the first wiring layer P1.

It can be known from the above preparation process that the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located on the side of the transistor T away from the substrate 300. Compared with the manufacturing process of FeRAM, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 are both located in the back-end process BEOL, which will not increase the process flow and process difficulty too much. Compared with the manufacturing process of FeFET, the preparation of the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 in the embodiment of the present application does not need to be mixed in the front-end process FEOL, the process flow is highly compatible with the CMOS logic part, and the process cost is low. Moreover, the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 can be formed synchronously. In other words, the storage array provided in the embodiment of the present application can increase the capacity of the storage array without increasing the process difficulty, process cost and the number of transistors in the storage unit.

The following is a schematic illustration of a method for reading a storage circuit provided in an embodiment of the present application.

According to different input read information, the number of bits of the storage branch 200 ′ in the storage circuit provided in the embodiment of the present application can be 2 bits or log ₂ 3 bits.

In the first case, the number of bits of the storage branch 200' may be 2 bits.

Then, in the embodiment of the present application, 2 bits of information are stored in the first ferroelectric capacitor C1 and the second ferroelectric capacitor C2 respectively. Since the polarity of the ferroelectric capacitor facing up or down can represent 1 or 0. In the embodiment of the present application, the first ferroelectric capacitor C1 stores high-bit information, the second ferroelectric capacitor C2 stores low-bit information, the polarity of the ferroelectric capacitor facing up is 1, and the polarity of the ferroelectric capacitor facing down is 0. Of course, the first ferroelectric capacitor C1 can also store low-bit information, the second ferroelectric capacitor C2 can store high-bit information, the polarity of the ferroelectric capacitor facing up is 0, and the polarity of the ferroelectric capacitor facing down is 1, and the principle remains unchanged.

The method for reading the storage branch 200' provided in the embodiment of the present application includes:

During the write phase:

When writing data to the first ferroelectric capacitor C1, a reference ground voltage GND is applied to the first input and output electrode (e.g., drain doping region D) and the second input and output electrode (e.g., source doping region S) of the transistor T. A first voltage is applied to the control electrode (e.g., conductive gate G) of the transistor T to write the first data. A second voltage is applied to the control electrode (e.g., conductive gate G) to write the second data.

In some embodiments, the first data and the second data are 1 and 0 respectively. In the embodiment of the present application, the first data is 1 and the second data is 0 for illustration.

In some embodiments, the first voltage is greater than the coercive voltage Vc, and the absolute value of the second voltage is greater than the coercive voltage Vc.

For example, when data needs to be written to the high-order bit, the reference ground voltage GND is applied to the drain doping region D and the source doping region S of the transistor T, and a voltage with an absolute value greater than the coercive voltage Vc is applied to the conductive gate G of the transistor T, so that the first ferroelectric capacitor C1 is forcibly flipped. If a first voltage greater than the coercive voltage Vc is applied to the conductive gate G of the transistor T, the polarity of the first ferroelectric capacitor C1 is reversed upward, and 1 is written. If a second voltage with an absolute value greater than the coercive voltage Vc is applied to the conductive gate G of the transistor T, the polarity of the first ferroelectric capacitor C1 is reversed downward, and 0 is written.

When writing data to the second ferroelectric capacitor C2, a reference ground voltage GND is applied to the control electrode (e.g., conductive gate G) and the second input-output electrode (e.g., source doping region S). A third voltage is applied to the first input-output electrode (e.g., drain doping region D) to write the first data. A fourth voltage is applied to the first input-output electrode (e.g., drain doping region D) to write the second data.

In some embodiments, the third voltage is greater than the coercive voltage Vc, and an absolute value of the fourth voltage is greater than the coercive voltage Vc.

For example, when data needs to be written to the low-order bit, the reference ground voltage GND is applied to the conductive gate G and the source doping region S of the transistor T, and a voltage with an absolute value greater than the coercive voltage Vc is applied to the drain doping region D of the transistor T, so that the ferroelectric capacitor is forcibly flipped. If a third voltage is applied to the drain doping region D of the transistor T, the polarity of the second ferroelectric capacitor C2 is reversed upward, and 1 is written. If a fourth voltage is applied to the drain doping region D of the transistor T, the polarity of the second ferroelectric capacitor C2 is reversed downward, and 1 is written. Enter 0.

During the read phase:

A reference ground voltage GND is applied to the second input and output electrode (e.g., the source doping region S), a reference voltage Vref is applied to the control electrode (e.g., the conductive gate G), a read voltage Vread is applied to the first input and output electrode (e.g., the drain doping region D), and the signal of the first input and output electrode (e.g., the drain doping region D) is read.

In some embodiments, the reference voltage Vref is less than the coercive voltage Vc, and the absolute value of the read voltage Vread is greater than the coercive voltage Vc.

For example, when data needs to be read, a reference ground voltage GND is applied to the source doping region S of the transistor T, and a reference voltage Vref with a voltage value less than the coercive voltage Vc is applied to the conductive gate G. Since the ferroelectric polarity will change the threshold voltage Vt of the transistor T, and the trends of changes in different polarities are opposite. Taking NMOS as an example, when the polarity of the first ferroelectric capacitor C1 is upward, the threshold voltage Vt increases, and the current flowing through the drain doping region D is larger. When the polarity of the first ferroelectric capacitor C1 is downward, the threshold voltage Vt decreases, and the current flowing through the drain doping region D is smaller. Therefore, by selecting an appropriate reference voltage Vref, the magnitude of the current flowing through the drain doping region D can be clearly distinguished. By reading the magnitude of the current flowing through the drain doping region D, it can be determined whether the first ferroelectric capacitor C1 stores 0 or 1.

Then, a read voltage Vread with a voltage value greater than the coercive voltage Vc is applied to the drain doping region D. The read voltage Vread will force the second ferroelectric capacitor C2 coupled to the drain doping region D to flip to an upward state. If the polarity of the second ferroelectric capacitor C2 is originally upward, the total amount of charge flowing through the drain doping region D is small. If the polarity of the second ferroelectric capacitor C2 is originally downward, a large amount of charge will flow through the drain doping region D due to the reversal of the ferroelectric polarity. By reading the charge amount of the drain doping region D, it can be determined whether the second ferroelectric capacitor C stores 0 or 1.

In some embodiments, when the memory array or memory circuit provided in the embodiments of the present application is applied to the memory provided in the embodiments of the present application, the charge detection circuit included in the memory is coupled to the transistor T to detect the amount of charge output by the transistor T. The current detection circuit included in the memory is coupled to the transistor T to detect the current output by the transistor T.

Based on this, there are four situations in the reading process, corresponding to four states and two bits. As shown in FIG15A , by determining which of the four intervals the read current and charge are in, it can be determined whether the data stored in the storage branch 200 ′ is 0 or 1.

For example, when the charge amount is greater than a, the lower bit is 0. When the charge amount is less than a, the lower bit is 1.

When the charge is less than a and the current is greater than b, the high bit is 0. When the charge is less than a and the current is less than b, the high bit is 1.

When the charge is greater than a and the current is greater than c, the high bit is 0. When the charge is greater than a and the current is less than c, the high bit is 1.

That is, when the charge amount is greater than a and the current is greater than c, the data stored in the storage branch 200 ′ is <00>.

When the charge amount is greater than a and the current is less than c, the data stored in the storage branch 200 ′ is <10>.

When the charge amount is less than a and the current is greater than b, the data stored in the storage branch 200 ′ is <01>.

When the charge amount is less than a and the current is less than b, the data stored in the storage branch 200 ′ is <11>.

In other embodiments, when the storage array or storage circuit provided in the embodiments of the present application is applied to the memory provided in the embodiments of the present application, the charge detection circuit included in the memory is coupled to the transistor T for detecting the amount of charge output by the transistor T.

Based on this, there are four situations in the reading process, corresponding to four states and two bits. As shown in FIG15B , by determining which of the four intervals the charge obtained by reading is in, it can be determined whether the data stored in the storage branch 200 ′ is 0 or 1.

For example, when the charge amount is less than d, the data stored in the storage branch 200 ′ is <11>.

When the charge amount is greater than d and less than e, the data stored in the storage branch 200 ′ is <01>.

When the charge amount is greater than e and less than f, the data stored in the storage branch 200 ′ is <10>.

When the charge amount is greater than f and less than g, the data stored in the storage branch 200 ′ is <00>.

By properly selecting the integration time of the current output by the transistor T, it can be obtained that the corresponding charge amounts in the four states are significantly different, so as to clearly distinguish the four storage conditions.

Data retention phase:

Due to the non-volatility of ferroelectric materials, the cancellation of the external electric field will result in a residual polarization intensity +Pr or a residual polarization intensity -Pr. Therefore, during the non-data writing and non-data reading process, the reference ground voltage GND will be transmitted to the conductive gate G, the source doping region S and the drain doping region D, and the data stored in the storage branch 200' will be saved.

In the second case, the number of bits of the storage branch 200' may be _log23 bits.

The write phase is the same as in the first case above, the read phase is slightly different.

Reading phase:

A reference ground voltage GND is applied to the second input and output electrode (e.g., the source doping region S), a reference voltage Vref is applied to the control electrode (e.g., the conductive gate G), a read voltage Vread is applied to the first input and output electrode (e.g., the drain doping region D), and the signal of the first input and output electrode (e.g., the drain doping region D) is read.

In some embodiments, the reference voltage Vref is less than the coercive voltage Vc, and the absolute value of the read voltage Vread is greater than the coercive voltage Vc. A suitable reference voltage Vref is selected to determine whether the current flows through the drain doping region D to determine the state of the ferroelectric polarity of the first ferroelectric capacitor C1. At this time, in FIG. 15A, the current is small in both cases where the charge amount is less than a and the low bit is 1, and it is difficult to distinguish, and they are degenerated into one state.

In this way, the states stored in the storage branch 200' are reduced from four states to three states. Correspondingly, the number of bits of the storage branch 200' is also reduced from 2 bits to log ₂ 3 bits.

Using this data reading method, the three states can be distinguished more easily. Although the number of bits is sacrificed, the difficulty of designing peripheral circuits is reduced.

Based on this, when the storage array and storage circuit provided by the embodiment of the present application are applied to the memory provided by the embodiment of the present application, the number of bits of each storage unit 200 and storage branch 200' is greater than 1. Thus, the capacity of the memory can be increased without increasing the area of the memory. Moreover, during the read and write operation, the information of more than 1 bit stored in the storage unit 200 and the storage branch 200' can be completed by writing in batches and reading once, without multiple reads. Compared with splicing two storage units in the related art into a storage unit with a bit number greater than 1, and then reading and writing in two times, the read and write process of the storage unit 200 and the storage branch 200' in the embodiment of the present application is simple and occupies a small area.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (28)

1. A storage array, comprising:

   a plurality of memory cells, each memory cell of the plurality of memory cells comprising a transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor;

   The transistor comprises a conductive gate and a first doped region and a second doped region disposed adjacent to each other; the conductive gate is disposed above a gap between the first doped region and the second doped region;

   The first end of the first ferroelectric capacitor is coupled to the conductive gate, and the second end of the first ferroelectric capacitor is used to receive a signal from a word line; the first end of the second ferroelectric capacitor is coupled to the first doped region, and the second end of the second ferroelectric capacitor is used to communicate signals with a bit line.
2. The memory array according to claim 1, wherein the first ferroelectric capacitor and the second ferroelectric capacitor are located on a side of the conductive gate away from the first doped region and the second doped region.
3. The memory array according to claim 2, wherein the first ferroelectric capacitor and the second ferroelectric capacitor are formed synchronously.
4. The memory array according to any one of claims 1 to 3, characterized in that the second doped region is used to receive a signal of a plate line.
5. The memory array according to any one of claims 1 to 4, characterized in that the memory array further comprises a first wiring layer, and the first ferroelectric capacitor and the second ferroelectric capacitor are arranged on a side of the first wiring layer away from the transistor.
6. The memory array according to claim 5, characterized in that the memory array further comprises a second wiring layer;

   The first ferroelectric capacitor and the second ferroelectric capacitor are located between the second wiring layer and the first wiring layer, and the second wiring layer is disposed adjacent to the first wiring layer.
7. The storage array according to any one of claims 1 to 6, characterized in that the number of bits of the storage unit is 2 bits or log ₂ 3 bits.
8. A storage circuit, comprising:

   a plurality of storage branches, each storage branch of the plurality of storage branches comprising a transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor;

   The transistor includes a control electrode, a first input-output electrode, and a second input-output electrode; the first end of the first ferroelectric capacitor is coupled to the control electrode, and the second end of the first ferroelectric capacitor is used to receive a signal from a word line; the first end of the second ferroelectric capacitor is coupled to the first input-output electrode, and the second end of the second ferroelectric capacitor is used to communicate signals with a bit line.
9. The storage circuit according to claim 8, characterized in that the second input-output electrode is used to receive a signal from a plate line.
10. The storage circuit according to claim 8 or 9, characterized in that the first input-output electrode and the second input-output electrode include the first doped region and the second doped region disposed adjacently;

    The control electrode includes a conductive gate, and the conductive gate is located above the gap between the first doping region and the second doping region.
11. The storage circuit according to claim 10, characterized in that the first ferroelectric capacitor and the second ferroelectric capacitor are located on a side of the conductive gate away from the first doped region and the second doped region.
12. The storage circuit according to any one of claims 8 to 11, characterized in that the first ferroelectric capacitor and the second ferroelectric capacitor are formed synchronously.
13. The storage circuit according to any one of claims 8 to 12 is characterized in that the storage circuit also includes a first wiring layer, the first ferroelectric capacitor and the second ferroelectric capacitor are arranged on a side of the first wiring layer away from the transistor, the first ferroelectric capacitor is coupled to the control electrode via the first wiring layer, and the second ferroelectric capacitor is coupled to the first input-output electrode via the first wiring layer.
14. The memory circuit according to claim 13, wherein the memory array further comprises a second wiring layer;

    The first ferroelectric capacitor and the second ferroelectric capacitor are located between the second wiring layer and the first wiring layer, and the second wiring layer is disposed adjacent to the first wiring layer.
15. A memory, characterized in that it comprises: a controller and a storage array as described in any one of claims 1 to 7, or a storage circuit as described in any one of claims 8 to 14, coupled to the controller.
16. The memory according to claim 15, characterized in that the memory further comprises a charge detection circuit;

    The charge detection circuit is coupled to the storage unit of the storage array and is used to detect the amount of charge output by the storage unit;

    or,

    The charge detection circuit is coupled to the storage branch of the storage circuit and is used to detect the amount of charge output by the storage branch.
17. The memory according to claim 15 or 16, characterized in that the memory further comprises a current detection circuit;

    The current detection circuit is coupled to the storage unit of the storage array and is used to detect the current output by the storage unit;

    or,

    The current detection circuit is coupled to the storage branch of the storage circuit and is used to detect the current output by the storage branch.
18. An electronic device, characterized in that it comprises: a circuit board and a memory, wherein the circuit board and the memory are coupled; and the memory comprises the memory described in any one of claims 15-17.
19. A method for preparing a storage array, characterized in that the storage array comprises a plurality of storage units;

    The method for preparing the storage array comprises:

    forming a transistor and forming a first ferroelectric capacitor and a second ferroelectric capacitor to form the memory cell;

    Wherein, the transistor comprises a conductive gate and a first doping region and a second doping region disposed adjacent to each other; the conductive gate is located above a gap between the first doping region and the second doping region;

    The first end of the first ferroelectric capacitor is coupled to the conductive gate, and the second end of the first ferroelectric capacitor is used to receive a signal from a word line; the first end of the second ferroelectric capacitor is coupled to the first doped region, and the second end of the second ferroelectric capacitor is used to communicate signals with a bit line.
20. The method for preparing a memory array according to claim 19, wherein forming the first ferroelectric capacitor and the second ferroelectric capacitor comprises:

    The first ferroelectric capacitor and the second ferroelectric capacitor are formed on a side of the conductive gate away from the first doping region and the second doping region.
21. The method for preparing a memory array according to claim 19 or 20, wherein the first ferroelectric capacitor and the second ferroelectric capacitor are formed synchronously.
22. The method for preparing a memory array according to any one of claims 19 to 21, wherein the memory array further comprises a first wiring layer;

    The preparation method further comprises:

    Before forming the first ferroelectric capacitor and the second ferroelectric capacitor, the first wiring layer is formed on the transistor.
23. The method for preparing a memory array according to claim 22, wherein the memory array further comprises a second wiring layer;

    The preparation method further comprises:

    After forming the first ferroelectric capacitor and the second ferroelectric capacitor, the second wiring layer is formed; the second wiring layer is arranged adjacent to the first wiring layer.
24. A method for reading and writing a storage circuit, characterized in that the storage circuit comprises the storage circuit according to any one of claims 8 to 14;

    The reading and writing method comprises:

    When writing data to the first ferroelectric capacitor, a reference ground voltage is applied to the first input/output electrode and the second input/output electrode of the transistor; a first voltage is applied to the control electrode of the transistor to write the first data; a second voltage is applied to the control electrode to write the second data;

    When writing data to the second ferroelectric capacitor, the reference ground voltage is applied to the control electrode and the second input-output electrode; a third voltage is applied to the first input-output electrode to write the first data; a fourth voltage is applied to the first input-output electrode to write the second data;

    Applying the reference ground voltage to the second input-output electrode, applying a reference voltage to the control electrode, applying a read voltage to the first input-output electrode, and reading a signal of the first input-output electrode;

    A reference ground voltage is applied to the control electrode, the first input-output electrode, and the second input-output electrode to maintain the storage of the storage circuit.
25. The reading and writing method of the storage circuit according to claim 24 is characterized in that the absolute value of the first voltage, the third voltage, the second voltage and the absolute value of the fourth voltage are greater than the coercive voltage.
26. The reading and writing method of the storage circuit according to claim 24 or 25 is characterized in that the reference voltage is less than the coercive voltage, and the absolute value of the read voltage is greater than the coercive voltage.
27. The reading and writing method of the storage circuit according to any one of claims 24 to 26 is characterized in that the first voltage and the second voltage have opposite polarities; and the third voltage and the fourth voltage have opposite polarities.
28. A computer-readable storage medium, characterized in that the computer-readable storage medium includes computer instructions, and when the computer instructions are executed on a device, the device executes the reading and writing method as described in any one of claims 24-27.