WO2024014473A1

WO2024014473A1 - Semiconductor device

Info

Publication number: WO2024014473A1
Application number: PCT/JP2023/025696
Authority: WO
Inventors: 文悟田中
Original assignee: ローム株式会社
Priority date: 2022-07-15
Filing date: 2023-07-12
Publication date: 2024-01-18

Abstract

A semiconductor device according to the present invention is provided with an element insulating layer and a plurality of semiconductor resistive layers that are provided in the element insulating layer. The semiconductor resistive layers each comprise a resistive back surface, a resistive front surface that is on the reverse side from the resistive back surface, and a resistive lateral surface that connects the resistive back surface and the resistive front surface to each other. The element insulating layer comprises: a first insulating layer; a second insulating layer that is superposed on the first insulating layer and has a higher relative dielectric constant than the first insulating layer; and a third insulating layer that is superposed on the second insulating layer and has a lower relative dielectric constant than the second insulating layer. The semiconductor resistive layers are superposed on the second insulating layer and are provided within the third insulating layer in such a manner that the resistive back surfaces are in contact with the second insulating layer.

Description

semiconductor equipment

The present disclosure relates to a semiconductor device.

Conventionally, devices are known that detect high voltage using a resistive voltage divider circuit. For example, Patent Document 1 discloses a ladder resistance circuit including a plurality of series resistors connected in series with each other and a voltage dividing resistor connecting a voltage dividing point of the plurality of series resistors to a connection point of a high voltage battery; A power supply device is disclosed that detects the voltage of a battery unit using a voltage detection circuit including a /D converter.

Japanese Patent Application Publication No. 2010-8227

By the way, the development of a configuration in which a circuit including a plurality of resistors, such as a ladder resistance circuit of a power supply device, can be integrated into one chip is underway. In this case, electric field concentration may occur within the chip, and there is room for improvement in alleviating the electric field concentration.

A semiconductor device according to one aspect of the present disclosure includes an element insulating layer having a front surface and a back surface opposite to the front surface, and one or more semiconductor resistance layers provided in the element insulating layer, The semiconductor resistance layer includes a resistor back surface facing the back surface in the thickness direction of the element insulating layer, a resistor surface opposite to the resistor back surface, and a resistor side surface connecting the resistor back surface and the resistor surface. , the element insulating layer includes a first insulating layer, a second insulating layer laminated on the first insulating layer and having a higher dielectric constant than the first insulating layer, and a second insulating layer laminated on the second insulating layer. , a third insulating layer having a lower dielectric constant than the second insulating layer, the semiconductor resistance layer is laminated on the second insulating layer, and the resistor back surface is on the second insulating layer. The third insulating layer is provided in contact with the third insulating layer.

A semiconductor device according to one aspect of the present disclosure includes an element insulating layer, one or more semiconductor resistance layers provided in the element insulating layer, and electrically connected to the semiconductor resistance layer in the element insulating layer, a wiring layer disposed opposite to the semiconductor resistance layer in the thickness direction of the element insulating layer, the wiring layer having a wiring surface facing the semiconductor resistance layer in the thickness direction of the element insulation layer; The element insulating layer includes a wiring back surface opposite to the wiring surface, and a wiring side surface connecting the wiring front surface and the wiring back surface, and the element insulating layer is laminated on a fourth insulating layer and the fourth insulating layer, a fifth insulating layer having a higher dielectric constant than the fourth insulating layer; and a low dielectric constant insulating layer laminated on the fifth insulating layer and having a lower dielectric constant than the fifth insulating layer, The wiring layer is laminated on the fifth insulating layer, and is provided in the low dielectric constant insulating layer with the back surface of the wiring in contact with the fifth insulating layer.

According to the semiconductor device of the present disclosure, electric field concentration can be alleviated.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view of a first chip and a second chip in the semiconductor device of FIG. 1. FIG. 3 is a schematic plan view of the semiconductor resistance layer in the first chip. FIG. 4 is a schematic cross-sectional view showing the semiconductor resistance layer and its surroundings in the first chip. FIG. 5 is an enlarged cross-sectional view of the semiconductor resistance layer and its surroundings in FIG. 4. FIG. 6 is a schematic cross-sectional view showing the wiring layer and its surroundings in the first chip. FIG. 7 is a schematic cross-sectional view of the first chip taken along line F7-F7 in FIG. FIG. 8 is a schematic cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. FIG. 9 is a schematic cross-sectional view showing the manufacturing process following FIG. 8. FIG. 10 is a schematic cross-sectional view showing the manufacturing process following FIG. 9. FIG. 11 is a schematic cross-sectional view showing the manufacturing process following FIG. 10. FIG. 12 is a schematic cross-sectional view showing the manufacturing process following FIG. 11. FIG. 13 is a schematic cross-sectional view showing the manufacturing process following FIG. 12. FIG. 14 is a schematic cross-sectional view showing the manufacturing process following FIG. 13. FIG. 15 is a schematic cross-sectional view showing the manufacturing process following FIG. 14. FIG. 16 is a schematic cross-sectional view showing the manufacturing process following FIG. 15. FIG. 17 is a schematic cross-sectional view showing the semiconductor resistance layer and its surroundings in the first chip in the semiconductor device of the second embodiment. FIG. 18 is a schematic cross-sectional view showing the wiring layer and its surroundings in the first chip. FIG. 19 is a schematic cross-sectional view showing a terminal, a semiconductor resistance layer, a wiring layer, and their surroundings in the first chip. FIG. 20 is a schematic cross-sectional view showing the semiconductor resistance layer and its surroundings in the first chip in the semiconductor device of the third embodiment. FIG. 21 is a schematic cross-sectional view showing the wiring layer and its surroundings in the first chip. FIG. 22 is a schematic cross-sectional view showing a terminal, a semiconductor resistance layer, a wiring layer, and their surroundings in the first chip. FIG. 23 is a schematic cross-sectional view showing a terminal, a semiconductor resistance layer, a wiring layer, and their surroundings in a first chip of a semiconductor device according to a modification. FIG. 24 is a schematic cross-sectional view showing a wiring layer, a semiconductor resistance layer, and their surroundings in a first chip of a semiconductor device according to a modification.

Hereinafter, some embodiments of an insulating chip and a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure.

The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.

<First embodiment>
The semiconductor device 10 of the first embodiment will be described with reference to FIGS. 1 to 16.
1 and 2 schematically show the overall configuration of the semiconductor device 10, FIG. 3 shows a planar structure of a part of the first chip, which will be described later, and FIGS. 4 to 7 show a cross-sectional structure of a part of the first chip. It shows. 8 to 16 show an example of the manufacturing process of the semiconductor device 10.

Note that the term "planar view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. Furthermore, regarding the semiconductor device 10 shown in FIG. 4, the +Z direction is defined as top, the -Z direction as bottom, the +X direction as right, and the -X direction as left. Unless otherwise specified, "planar view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[Overall configuration of semiconductor device]
FIG. 1 schematically shows the overall configuration of a semiconductor device 10 according to the first embodiment. FIG. 2 schematically shows the electrical configuration and electrical connection structure of each of the first chip 14 and the second chip 15, which will be described later, of the semiconductor device 10. In addition, in FIG. 1, in order to easily understand the drawing, components inside the sealing resin 16, which will be described later, are shown with solid lines. In FIG. 2, internal components of the first chip 14 and the second chip 15 are shown with solid lines in order to easily understand the drawing.

As shown in FIG. 1, the semiconductor device 10 includes a frame 11, a die pad 12, a plurality of (seven in the first embodiment) leads 13A to 13G, a first chip 14 mounted on the frame 11, and a die pad 12. 12, wires W1 to W11, and a sealing resin 16 for sealing these. Here, in the first embodiment, the first chip 14 corresponds to an "insulating chip".

The sealing resin 16 is formed into a flat plate shape. The shape of the sealing resin 16 in plan view is rectangular. The sealing resin 16 has first to fourth resin side surfaces 16A to 16D. The first resin side surface 16A and the second resin side surface 16B constitute both end surfaces of the sealing resin 16 in the X-axis direction. The first resin side surface 16A constitutes an end surface of the sealing resin 16 in the -X direction, and the second resin side surface 16B constitutes an end surface of the sealing resin 16 in the +X direction. The third resin side surface 16C and the fourth resin side surface 16D constitute both end surfaces of the sealing resin 16 in the Y-axis direction. The third resin side surface 16C constitutes an end surface of the sealing resin 16 in the -Y direction, and the fourth resin side surface 16D constitutes an end surface of the sealing resin 16 in the +Y direction.

The frame 11 and die pad 12 are arranged apart from each other in the X-axis direction. In other words, the X-axis direction is the direction in which the frame 11 and die pad 12 are arranged. The frame 11 is arranged closer to the first resin side surface 16A than the die pad 12. Frame 11, die pad 12, and leads 13A to 13G are each made of a metal material such as copper (Cu) or aluminum (Al).

The frame 11 includes a die pad portion 11A and a lead portion 11B. In the first embodiment, the die pad section 11A and the lead section 11B are integrally formed.
The die pad portion 11A is a portion on which the first chip 14 is mounted, and supports the first chip 14. The die pad portion 11A is spaced apart from the first resin side surface 16A toward the second resin side surface 16B. The die pad portion 11A has a rectangular shape in plan view, with the Y-axis direction being the longitudinal direction and the X-axis direction being the lateral direction. In other words, the die pad portion 11A is formed so that the dimension in the arrangement direction of the frame 11 and the die pad 12 is shortened.

The lead portion 11B includes an end portion of the die pad portion 11A in the Y-axis direction that is closer to the third resin side surface 16C, and an end portion of the die pad portion 11A in the X-axis direction that is closer to the first resin side surface 16A. It is connected to the corner part consisting of the end part of. The lead portion 11B extends along the X-axis direction toward the first resin side surface 16A with respect to the die pad portion 11A.

The die pad 12 is located closer to the second resin side surface 16B than the frame 11, and is spaced apart from the second resin side surface 16B toward the first resin side surface 16A. The die pad 12 is a portion on which the second chip 15 is mounted, and supports the second chip 15. The die pad 12 has a rectangular shape in plan view, with the Y-axis direction being the longitudinal direction and the X-axis direction being the lateral direction. That is, the die pad 12 is formed so that the dimension in the arrangement direction of the frame 11 and the die pad 12 is shortened.

The leads 13A to 13G are distributed and arranged at both ends of the sealing resin 16 in the X-axis direction. More specifically, the lead 13A is arranged at the end of the sealing resin 16 on the first resin side surface 16A side. Each of the leads 13B to 13G is arranged at the end of the sealing resin 16 on the second resin side surface 16B side.

The leads 13A are arranged closer to the first resin side surface 16A than the die pad portion 11A. The lead 13A is spaced apart from the die pad portion 11A in the X-axis direction. Further, the lead 13A is arranged apart from the lead portion 11B in the Y-axis direction. In the first embodiment, the lead 13A is arranged at a position that overlaps with the end on the fourth resin side surface 16D side of both ends in the Y-axis direction of the die pad portion 11A when viewed from the X-axis direction.

Each of the leads 13B to 13G is arranged closer to the second resin side surface 16B than the die pad 12. Each of the leads 13B to 13G is arranged apart from the die pad 12 in the X-axis direction. The leads 13B to 13G are arranged spaced apart from each other in the Y-axis direction. The leads 13B to 13G are arranged in the order of lead 13B, lead 13C, lead 13D, lead 13E, lead 13F, and lead 13G from the fourth resin side surface 16D to the third resin side surface 16C. As can be seen from FIG. 1, the distance between the lead 13A and the lead portion 11B in the Y-axis direction is greater than the distance between adjacent leads in the Y-axis direction among the leads 13B to 13G.

The first chip 14 mounted on the die pad portion 11A of the frame 11 is formed into a flat plate shape. The shape of the first chip 14 in a plan view is a rectangular shape whose longitudinal direction is in the Y-axis direction and whose transverse direction is in the X-axis direction. That is, the first chip 14 is formed so that the dimensions in the arrangement direction of the frame 11 and die pad 12 are shortened.

The first chip 14 includes a plurality of terminals P1 to P5. The terminals P1 and P2 are provided at the end of the first chip 14 in the X-axis direction that is closer to the first resin side surface 16A. The terminal P1 is provided in the first chip 14 near the lead 13A. The terminal P2 is provided in the first chip 14 near the lead portion 11B. The terminals P3 to P5 are provided at the end closer to the second chip 15 of both ends of the first chip 14 in the X-axis direction. The terminals P3 to P5 are arranged apart from each other in the Y-axis direction.

The second chip 15 mounted on the die pad 12 is formed into a flat plate shape. The shape of the second chip 15 in plan view is a rectangular shape in which the Y-axis direction is the longitudinal direction and the X-axis direction is the lateral direction. In other words, the second chip 15 is formed so that the dimensions in the arrangement direction of the frame 11 and the die pad 12 are shortened.

The second chip 15 includes a plurality of terminals Q1 to Q9. The terminals Q1 to Q3 are provided at the end closer to the first chip 14 of both ends of the second chip 15 in the X-axis direction. The terminals Q1 to Q3 are arranged spaced apart from each other in the Y-axis direction. The terminals Q4 to Q9 are provided at the end closer to the second resin side surface 16B of both ends of the second chip 15 in the X-axis direction. The terminals Q4 to Q9 are arranged spaced apart from each other in the Y-axis direction.

The terminal P1 of the first chip 14 is electrically connected to the lead 13A by a wire W1. Terminal P2 is electrically connected to lead portion 11B by wire W2. In other words, it can be said that the terminal P2 is electrically connected to the frame 11. A high voltage generating section VT is electrically connected to the lead 13A and the lead section 11B. The high voltage generator VT is, for example, a DC power supply. The positive electrode of the high voltage generating section VT is electrically connected to the lead 13A, and the negative electrode of the high voltage generating section VT is electrically connected to the lead section 11B.

Terminals P3 to P5 of the first chip 14 and terminals Q1 to Q3 of the second chip 15 are individually electrically connected by wires W3 to W5. Terminals Q4 to Q9 are individually electrically connected to leads 13B to 13G by wires W6 to W11.

Here, in the first embodiment, among the terminals P1 to P5, the terminals P1 and P2 constitute high voltage side terminals, and the terminals P3 to P5 constitute low voltage side terminals. That is, the terminal electrically connected to the lead 13A and the lead portion 11B constitutes a high voltage side terminal, and the terminal electrically connected to the second chip 15 constitutes a low voltage side terminal.

In this way, the die pad section 11A of the frame 11 electrically connected to the high voltage generating section VT constitutes a high voltage side die pad, and the die pad 12 constitutes a low voltage side die pad. Therefore, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 is higher than that between the terminals P1, P2 and the substrate 30. In one example, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 is about 3850V in DC voltage, and the dielectric strength voltage between the terminals P1, P2 and the substrate 30 is about 1400V in DC power supply.

Next, the circuit configurations within the first chip 14 and the second chip 15 will be explained.
As shown in FIG. 2, the first chip 14 includes first to fourth resistance circuits 14A to 14D for stepping down the high voltage of the high voltage generating section VT (see FIG. 1). The first resistance circuit 14A includes a resistance value RA, the second resistance circuit 14B includes a resistance value RB, the third resistance circuit 14C includes a resistance value RC, and the fourth resistance circuit 14D includes a resistance value RD.

The resistance value RB is smaller than the resistance value RA. The ratio of the resistance value RB to the resistance value RA (RB/RA) is set in advance. Resistance value RC is smaller than resistance value RD. The ratio of the resistance value RC to the resistance value RD (RC/RD) is set in advance. The ratio (RB/RA) and the ratio (RC/RD) are set to the same predetermined value (for example, 1/999).

The first to fourth resistance circuits 14A to 14D are connected in series. Each of the first to fourth resistance circuits 14A to 14D has a first end and a second end. The first end of the first resistance circuit 14A is electrically connected to the terminal P1, and the second end of the first resistance circuit 14A is electrically connected to the first end of the second resistance circuit 14B. There is. A connection point between the first resistance circuit 14A and the second resistance circuit 14B is electrically connected to the terminal P3. The second end of the second resistance circuit 14B is electrically connected to the first end of the third resistance circuit 14C. A connection point between the second resistance circuit 14B and the third resistance circuit 14C is electrically connected to the terminal P4. The second end of the third resistance circuit 14C is electrically connected to the first end of the fourth resistance circuit 14D. A connection point between the third resistance circuit 14C and the fourth resistance circuit 14D is electrically connected to the terminal P5. The second end of the fourth resistance circuit 14D is electrically connected to the terminal P2.

The second chip 15 includes a voltage detection circuit 15A. Voltage detection circuit 15A includes an operational amplifier. Voltage detection circuit 15A is electrically connected to terminals Q1 to Q3. The terminal Q1 is electrically connected to the terminal P3 of the first chip 14 by a wire W3, the terminal Q2 is electrically connected to the terminal P4 of the first chip 14 by a wire W4, and the terminal Q3 is electrically connected to the terminal P3 of the first chip 14 by a wire W5. It is electrically connected to terminal P5 of. Therefore, the voltage detection circuit 15A connects the connection point between the first resistance circuit 14A and the second resistance circuit 14B, the connection point between the second resistance circuit 14B and the third resistance circuit 14C, and the connection point between the third resistance circuit 14C and the third resistance circuit 14C. The voltage between the connection point and the four-resistance circuit 14D is detected. The terminals Q4 to Q9 (leads 13B to 13G (see FIG. 1)) are used to supply power supply voltage to the operational amplifier in the second chip 15 and to output the output signal of the voltage detection circuit 15A.

[Schematic planar structure of the first chip]
FIG. 3 shows a schematic planar structure of the first chip 14 including the first to fourth resistance circuits 14A to 14D (see FIG. 2) of the first chip 14 described above.

As shown in FIG. 3, the first chip 14 includes a plurality of unit semiconductor resistance layers (hereinafter referred to as "semiconductor resistance layers 20"). Each semiconductor resistance layer 20 extends along the X-axis direction. In other words, each semiconductor resistance layer 20 extends in the lateral direction of the first chip 14. The plurality of semiconductor resistance layers 20 are arranged to be aligned with each other in the X-axis direction and spaced apart from each other in the Y-axis direction. In other words, the plurality of semiconductor resistance layers 20 are spaced apart from each other in the longitudinal direction of the first chip 14 .

The plurality of semiconductor resistance layers 20 are used as constituent elements of the first to fourth resistance circuits 14A to 14D. The plurality of semiconductor resistance layers 20 can be divided into first to fourth resistance regions R1 to R4 as a plurality of resistance regions. The first to fourth resistance regions R1 to R4 are arranged in the order of resistance regions R1, R2, R3, and R4 from the +Y direction to the -Y direction. The first resistance region R1 is a region forming the first resistance circuit 14A, the second resistance region R2 is a region forming the second resistance circuit 14B, and the third resistance region R3 is a region forming the third resistance circuit 14C. The fourth resistance region R4 is a region constituting the fourth resistance circuit 14D.

The number of semiconductor resistance layers 20 in each of the first to fourth resistance regions R1 to R4 is individually set. In the first embodiment, the number of semiconductor resistance layers 20 in the first resistance region R1 and the fourth resistance region R4 is the same. The number of semiconductor resistance layers 20 in the second resistance region R2 and the third resistance region R3 is the same. The number of semiconductor resistance layers 20 in the first and fourth resistance regions R1 and R4 is greater than the number of semiconductor resistance layers 20 in the second and third resistance regions R2 and R3. Note that the number of semiconductor resistance layers 20 in each of the first to fourth resistance regions R1 to R4 is not limited to that in the first embodiment, and can be changed arbitrarily.

More specifically, in the first to fourth resistance regions R1 to R4, each end of the semiconductor resistance layer 20 in the odd-numbered row from the end in the +Y direction in the -X direction is connected to the semiconductor resistance layer 20 in the -Y direction. It is electrically connected to the ends in the −X direction of even-numbered rows of semiconductor resistance layers 20 adjacent to each other in the direction. Furthermore, each of the +X direction ends of the even-numbered semiconductor resistance layers 20 from the +Y-direction end corresponds to the +X-direction ends of the odd-numbered semiconductor resistance layers 20 adjacent to the semiconductor resistance layer 20 in the −Y direction. electrically connected to the As a result, all the semiconductor resistance layers 20 in the first to fourth resistance regions R1 to R4 are connected in series.

The semiconductor resistance layer 20 in the first row from the end in the +Y direction of the first resistance region R1 and the terminal P1 are connected by a wiring 21. The wiring 21 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the first resistance region R1.

The semiconductor resistance layer 20 in the first row from the end in the +Y direction of the second resistance region R2 and the terminal P3 are connected by a wiring 22. The wiring 22 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the second resistance region R2.

The semiconductor resistance layer 20 in the first row from the end in the -Y direction of the second resistance region R2, the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the third resistance region R3, and the terminal P4 are connected by wiring 23. It is connected. The wiring 23 is located at the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end in the −Y direction of the second resistance region R2 and in the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the third resistance region R3. It is connected to the.

The semiconductor resistance layer 20 in the first row from the end in the -Y direction of the third resistance region R3 and the terminal P5 are connected by a wiring 24. The wiring 24 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end in the −Y direction of the third resistance region R3.

The semiconductor resistance layer 20 in the first row from the end in the -Y direction of the fourth resistance region R4 and the terminal P2 are connected by a wiring 25. The wiring 25 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end in the −Y direction of the fourth resistance region R4.

[Cross-sectional structure of the first chip]
An example of the internal configuration of the first chip 14 will be described with reference to FIGS. 4 to 7. Each of FIGS. 4 to 7 shows a cross-sectional structure of the first chip 14. As shown in FIG. FIG. 4 shows a cross-sectional structure of a region including four semiconductor resistance layers 20 adjacent to each other in the Y-axis direction in the first resistance region R1, taken along the YZ plane. FIG. 5 shows an enlarged structure of the four semiconductor resistance layers 20 of FIG. 4 and their surroundings. FIG. 6 shows a cross-sectional structure obtained by cutting an end in the +X direction along the YZ plane in a region including four semiconductor resistance layers 20 adjacent to each other in the Y-axis direction in the first resistance region R1. FIG. 7 shows a cross-sectional structure of the first chip 14 taken along line F7-F7 in FIG.

As shown in FIG. 4, the first chip 14 includes a substrate 30 and an element insulating layer 40 formed on the substrate 30.
The substrate 30 is formed of, for example, a semiconductor substrate. The thickness of the substrate 30 is, for example, about 300 μm. In the first embodiment, the substrate 30 is a semiconductor substrate made of a material containing Si. Note that the substrate 30 may be a semiconductor substrate made of a wide bandgap semiconductor or a compound semiconductor. Further, instead of the semiconductor substrate, the substrate 30 may be an insulating substrate formed of a material containing glass or an insulating substrate formed of a material containing ceramics such as alumina.

A wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

The element insulating layer 40 has an element front surface 41 and an element back surface 42 facing oppositely to each other in the Z-axis direction. Here, in the first embodiment, the Z-axis direction corresponds to the "thickness direction of the element insulating layer". The back surface 42 of the element is in contact with the substrate 30. The element surface 41 is a surface opposite to the substrate 30 in the Z-axis direction.

Terminals P1 to P5 (see FIG. 3) and a passivation film 43 are formed on the element insulating layer 40.
Terminals P1 to P5 are formed on the element surface 41 of the element insulating layer 40. Terminals P1 to P5 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), Ni ( One or more of nickel), Pd (palladium), and W (tungsten) is selected as appropriate. In the first embodiment, the terminals P1 to P5 are formed of a material containing Al. As an example, FIG. 7 shows a structure in which a terminal P1 is formed on the element surface 41.

As shown in FIG. 7, the terminal P1 is covered with a passivation film 43. On the other hand, the passivation film 43 has an opening 43X that exposes the terminal P1. Although not shown, the passivation film 43 has an opening 43X that exposes the terminals P2 to P5 shown in FIGS. 1 to 3. Terminals P1-P5 therefore include exposed surfaces for connecting wires W1-W5 (see FIG. 1). In this way, the terminals P1 to P5 constitute electrode pads.

As shown in FIG. 4, the passivation film 43 is formed on the element surface 41 of the element insulating layer 40. The passivation film 43 is a surface protection film of the first chip 14, and is formed of a material containing SiN, for example. Note that the material constituting the passivation film 43 can be changed arbitrarily, and may be formed of a material containing SiO ₂ , for example. Further, the passivation film 43 may have a laminated structure of a plurality of films, for example, a laminated structure of a film formed of a material containing SiN and a film formed of a material containing _SiO2 .

The element insulating layer 40 includes a substrate-side insulating layer 50 provided on the substrate 30, a wiring-side insulating layer 60 laminated on the substrate-side insulating layer 50, and a resistance-side insulating layer laminated on the wiring-side insulating layer 60. layer 70.

The substrate-side insulating layer 50 includes a plurality of first substrate-side insulating layers 51 and a second substrate-side insulating layer 52 formed on the plurality of first substrate-side insulating layers 51. The plurality of first substrate side insulating layers 51 and the plurality of second substrate side insulating layers 52 are alternately stacked one by one in the Z-axis direction.

The first substrate side insulating layer 51 is formed of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. The first substrate-side insulating layer 51 may be a SiN-based insulating film. In the first embodiment, the first substrate side insulating layer 51 is formed of a material containing SiN. Further, the first substrate-side insulating layer 51 is, for example, an insulating layer having a different composition from the second substrate-side insulating layer 52, and is a film having stress opposite to that of the second substrate-side insulating layer 52. The first substrate side insulating layer 51 may be, for example, a nitride film having tensile stress.

The second substrate side insulating layer 52 is an oxide film formed of a material containing SiO ₂ (silicon oxide). The film thickness of the second substrate side insulating layer 52 is thicker than the film thickness of the first substrate side insulating layer 51. The first substrate side insulating layer 51 has a thickness of 50 nm or more and less than 1000 nm. The second substrate side insulating layer 52 has a thickness of 500 nm or more and 5000 nm or less. In the first embodiment, the first substrate side insulating layer 51 has a thickness of about 300 nm, and the second substrate side insulating layer 52 has a thickness of about 2000 nm.

The reason why the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are laminated alternately is to prevent the warpage of the substrate 30 caused by the film formation of the second substrate-side insulating layer 52 from the first substrate-side insulating layer 51. This is because the substrate-side insulating layer 50 can be formed thickly by controlling the film formation. In the first embodiment, the substrate-side insulating layer 50 has a thickness of about 13.5 μm.

Note that from the viewpoint of ease of viewing the drawings, the ratio of the film thickness of the first substrate side insulating layer 51 to the film thickness of the second substrate side insulating layer 52 in the drawings is the actual film thickness of the first substrate side insulating layer 51. and the film thickness of the second substrate side insulating layer 52 are different. In addition, in FIG. 4, in order to clearly show the configurations of the first substrate side insulating layer 51 and the second substrate side insulating layer 52, the thicknesses of both the first substrate side insulating layer 51 and the second substrate side insulating layer 52 are thickened. are doing. Therefore, the number of laminated layers of the first substrate side insulating layer 51 and the second substrate side insulating layer 52 shown in FIG. 4 indicates the actual number of laminated layers of the first substrate side insulating layer 51 and the second substrate side insulating layer 52. It's not a thing.

The resistance side insulating layer 70 is an insulating layer in which the semiconductor resistance layer 20 is embedded. The resistance side insulating layer 70 includes a first insulating layer 71, a second insulating layer 72 laminated on the first insulating layer 71, and a third insulating layer 73 laminated on the second insulating layer 72. . The semiconductor resistance layer 20 is stacked on the second insulating layer 72 and covered with the third insulating layer 73. Therefore, as shown in FIG. 4, the plurality of semiconductor resistance layers 20 are arranged at the same position in the Z-axis direction.

The semiconductor resistance layer 20 is formed into a flat plate shape with the thickness direction in the Z-axis direction. The thickness of the semiconductor resistance layer 20 is thinner than the width (length in the X-axis direction) of the semiconductor resistance layer 20. Further, the semiconductor resistance layer 20 has a thickness smaller than each of the first to third insulating layers 71 to 73. The thickness of the semiconductor resistance layer 20 is, for example, 1 nm or more and 100 nm or less. In the first embodiment, the thickness of the semiconductor resistance layer 20 is approximately 2.5 nm. The semiconductor resistance layer 20 is formed of a material containing, for example, CrSi (chromium silicon).

As shown in FIG. 5, the semiconductor resistance layer 20 includes a resistor back surface 27 facing the element back surface 42 of the element insulating layer 40 in the Z-axis direction, a resistor surface 28 on the opposite side to the resistor back surface 27, and a resistor back surface 27 and the resistor back surface 28. and a resistive side surface 29 connected to the surface 28. In the first embodiment, both the resistance back surface 27 and the resistance surface 28 are surfaces along the XY plane. The resistance side surface 29 is a surface that intersects both the resistance back surface 27 and the resistance surface 28. In the first embodiment, the resistance side surface 29 is a surface perpendicular to both the resistance back surface 27 and the resistance surface 28.

The semiconductor resistance layer 20 is provided within the third insulating layer 73 with the resistor back surface 27 in contact with the second insulating layer 72 . That is, the semiconductor resistance layer 20 is sandwiched between the second insulating layer 72 and the third insulating layer 73. Both resistive surface 28 and resistive side 29 are in contact with third insulating layer 73 .

As shown in FIG. 6, the wiring-side insulating layer 60 is an insulating layer in which a plurality of wiring layers 80 are embedded. The wiring side insulating layer 60 includes a fourth insulating layer 61, a fifth insulating layer 62 laminated on the fourth insulating layer 61, and a sixth insulating layer 63 laminated on the fifth insulating layer 62. . The plurality of wiring layers 80 are stacked on the fifth insulating layer 62 and covered with the sixth insulating layer 63. In the illustrated example, the plurality of wiring layers 80 are arranged at the same position in the Z direction.

The wiring layer 80 includes, for example, the wirings 21 to 25 shown in FIG. Since the wiring layer 80 is embedded in the wiring side insulating layer 60, it is arranged closer to the substrate 30 (see FIG. 4) than the semiconductor resistance layer 20 embedded in the resistance side insulating layer 70 in the Z-axis direction.

The wiring layer 80 is formed in a flat plate shape with the thickness direction in the Z-axis direction. The thickness of the wiring layer 80 is thinner than the width of the wiring layer 80 (the length in the direction perpendicular to the direction in which the wiring layer 80 extends in plan view). The thickness of the wiring layer 80 is thicker than the thickness of the semiconductor resistance layer 20. In the example shown in FIG. 6, the thickness of the wiring layer 80 is thicker than the thickness of each of the fifth insulating layer 62 and the sixth insulating layer 63. On the other hand, the thickness of the wiring layer 80 is thinner than the thickness of the fourth insulating layer 61. For the wiring layer 80, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected. In the first embodiment, the wiring layer 80 is formed of a material containing Al.

In the example shown in FIG. 6, the wiring layer 80 electrically connects two semiconductor resistance layers 20 adjacent in the Y-axis direction. More specifically, the wiring layer 80 is formed to overlap both of the two semiconductor resistance layers 20. Each semiconductor resistance layer 20 and wiring layer 80 are connected by two vias 90. The via 90 extends in the Z-axis direction, which is the thickness direction of the element insulating layer 40. More specifically, the via 90 is in contact with both the semiconductor resistance layer 20 and the wiring layer 80 by penetrating the first insulating layer 71, the second insulating layer 72, and the sixth insulating layer 63 in the Z-axis direction. ing. For the via 90, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected. In the first embodiment, the via 90 is formed of a material containing W. Note that the number of vias 90 can be changed arbitrarily.

The wiring layer 80 includes a wiring back surface 81 facing the element back surface 42 (see FIG. 4) of the element insulating layer 40 in the Z-axis direction, a wiring surface 82 opposite to the wiring back surface 81, and the wiring back surface 81 and the wiring surface 82. and a wiring side surface 83 that connects. In the illustrated example, it can be said that the wiring back surface 81 faces the opposite side from the semiconductor resistance layer 20 in the Z-axis direction. In the first embodiment, both the wiring back surface 81 and the wiring front surface 82 are surfaces along the XY plane. The wiring side surface 83 is a surface that intersects both the wiring back surface 81 and the wiring front surface 82. In the first embodiment, the wiring side surface 83 is a surface perpendicular to both the wiring back surface 81 and the wiring front surface 82.

The wiring layer 80 is provided in the sixth insulating layer 63 with the wiring back surface 81 in contact with the fifth insulating layer 62. That is, the wiring layer 80 is sandwiched between the fifth insulating layer 62 and the sixth insulating layer 63. Both the wiring surface 82 and the wiring side surface 83 are in contact with the sixth insulating layer 63.

(Electric field relaxation structure of semiconductor resistance layer)
As shown in FIG. 5, the element insulating layer 40 including the resistance-side insulating layer 70 and the wiring-side insulating layer 60 includes a structure that alleviates electric field concentration generated in the semiconductor resistance layer 20. In one example, the element insulating layer 40 includes a first insulating layer 71, a second insulating layer 72, and a sixth insulating layer 63 as a structure that alleviates electric field concentration in the semiconductor resistance layer 20.

Both the first insulating layer 71 and the second insulating layer 72 are arranged between the semiconductor resistance layer 20 and the wiring layer 80 in the Z-axis direction. The sixth insulating layer 63 is arranged closer to the substrate 30 than both the first insulating layer 71 and the second insulating layer 72. The first insulating layer 71 is stacked on the sixth insulating layer 63. The first insulating layer 71 is in contact with the sixth insulating layer 63.

The second insulating layer 72 in contact with the semiconductor resistance layer 20 is formed of a material containing, for example, SiN. Therefore, the dielectric constant of the second insulating layer 72 is about 7. In the illustrated example, the thickness of the second insulating layer 72 is thinner than both the thickness of the first insulating layer 71 and the thickness of the sixth insulating layer 63.

The first insulating layer 71 is spaced apart from the semiconductor resistance layer 20 in the Z-axis direction with the second insulating layer 72 interposed therebetween. The first insulating layer 71 is spaced apart from the wiring layer 80 in the Z-axis direction with the sixth insulating layer 63 interposed therebetween. The first insulating layer 71 has a lower dielectric constant than the second insulating layer 72. The dielectric constant of the first insulating layer 71 is greater than 3.8 and less than 7. In one example, the dielectric constant of the first insulating layer 71 may be greater than 4 and less than 7. In the first embodiment, the first insulating layer 71 is made of a material containing SiON. Therefore, the dielectric constant of the first insulating layer 71 is adjusted according to the concentration of N (nitrogen) in SiON. The first insulating layer 71 has a thinner thickness than the sixth insulating layer 63.

The sixth insulating layer 63 is spaced apart from the semiconductor resistance layer 20 in the Z-axis direction. The sixth insulating layer 63 has a lower dielectric constant than the first insulating layer 71. In the first embodiment, the sixth insulating layer 63 is made of a material containing SiO ₂ . Therefore, the dielectric constant of the sixth insulating layer 63 is about 3.8. In this way, the sixth insulating layer 63 is an insulating layer that relaxes the electric field of the semiconductor resistance layer 20 and covers the wiring layer 80. The thickness of the region of the sixth insulating layer 63 where the wiring layer 80 is not arranged is thicker than the thickness of each of the first insulating layer 71 and the second insulating layer 72. Here, in the first embodiment, the sixth insulating layer 63 corresponds to a "low dielectric constant insulating layer".

In this structure, the second insulating layer 72 , the first insulating layer 71 , and the sixth insulating layer 63 are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30 in the structure that alleviates the electric field concentration on the semiconductor resistance layer 20 . ing. In other words, the structure is such that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30 as a structure for alleviating electric field concentration on the semiconductor resistance layer 20 .

Further, the third insulating layer 73 covering the semiconductor resistance layer 20 has a lower dielectric constant than the second insulating layer 72. The third insulating layer 73 may have a lower dielectric constant than the first insulating layer 71. The third insulating layer 73 is formed of a material containing any one of SiON, SiC, and _SiO2 . In the first embodiment, the third insulating layer 73 has a lower dielectric constant than the first insulating layer 71 and is therefore formed of a material containing SiO ₂ . This improves the insulation between the semiconductor resistance layers 20 adjacent to each other in the Y-axis direction.

In the illustrated example, the third insulating layer 73 is thicker than each of the first insulating layer 71 , the second insulating layer 72 , and the sixth insulating layer 63 .
Note that the thickness of each of the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, and the sixth insulating layer 63 can be changed arbitrarily. In one example, the thickness of the first insulating layer 71, the thickness of the second insulating layer 72, and the thickness of the sixth insulating layer 63 may be equal to each other. Further, in one example, the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72 may be equal to each other and thinner than the thickness of the sixth insulating layer 63. Further, in one example, the thickness of the first insulating layer 71 may be thicker than the thickness of the second insulating layer 72. Further, in one example, the thickness of the third insulating layer 73 may be equal to the thickness of the sixth insulating layer 63. Further, in one example, the thickness of the third insulating layer 73 may be thinner than the thickness of the sixth insulating layer 63.

(Electric field relaxation structure of wiring layer)
As shown in FIG. 6, the element insulating layer 40 including the wiring-side insulating layer 60 and the substrate-side insulating layer 50 includes a structure that alleviates electric field concentration generated in the wiring layer 80. In one example, the element insulating layer 40 includes a fourth insulating layer 61 , a fifth insulating layer 62 , and a second substrate-side insulating layer that is the uppermost layer of the substrate-side insulating layer 50 as a structure that alleviates electric field concentration in the wiring layer 80 . Contains 52. In the following description, the second substrate-side insulating layer 52, which is the uppermost layer of the substrate-side insulating layer 50, will be referred to as a "seventh insulating layer 52A."

Each of the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A is arranged closer to the substrate 30 (see FIG. 4) than the wiring layer 80. It can also be said that each of the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A is arranged on the opposite side of the semiconductor resistance layer 20 with respect to the wiring layer 80 in the Z-axis direction. The fourth insulating layer 61 is laminated on the seventh insulating layer 52A. The fourth insulating layer 61 is in contact with the seventh insulating layer 52A.

The fifth insulating layer 62 in contact with the wiring layer 80 is formed of a material containing SiN, for example. Therefore, the dielectric constant of the fifth insulating layer 62 is about 7. In the illustrated example, the thickness of the fifth insulating layer 62 is equal to the thickness of the fourth insulating layer 61. Here, if the difference between the thickness of the fifth insulating layer 62 and the thickness of the fourth insulating layer 61 is, for example, within 20% of the thickness of the fifth insulating layer 62, the thickness of the fifth insulating layer 62 is the fourth insulating layer 62. It can be said that the thickness is equal to the thickness of the insulating layer 61. Further, the thickness of the fifth insulating layer 62 is thinner than the thickness of the seventh insulating layer 52A.

In the illustrated example, both the thickness of the fifth insulating layer 62 and the thickness of the fourth insulating layer 61 are thinner than the thickness of the first insulating layer 71. Further, both the thickness of the fifth insulating layer 62 and the thickness of the fourth insulating layer 61 are thinner than the thickness of the second insulating layer 72.

The fourth insulating layer 61 is spaced apart from the wiring layer 80 in the Z-axis direction with the fifth insulating layer 62 interposed therebetween. The fourth insulating layer 61 has a lower dielectric constant than the fifth insulating layer 62. The relative permittivity of the fourth insulating layer 61 is greater than 3.8 and less than 7. In one example, the dielectric constant of the fourth insulating layer 61 may be greater than 4 and less than 7. In the first embodiment, the fourth insulating layer 61 is made of a material containing SiON. Therefore, the dielectric constant of the fourth insulating layer 61 is adjusted according to the concentration of N (nitrogen) in SiON. The fourth insulating layer 61 has a thinner thickness than the seventh insulating layer 52A.

The seventh insulating layer 52A is spaced apart from the wiring layer 80 in the Z-axis direction. The seventh insulating layer 52A has a lower dielectric constant than the fourth insulating layer 61. In the first embodiment, the seventh insulating layer 52A is made of a material containing SiO ₂ . Therefore, the dielectric constant of the seventh insulating layer 52A is about 3.8. The thickness of the seventh insulating layer 52A is thicker than both the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72. Further, the thickness of the seventh insulating layer 52A is thicker than the thickness of the sixth insulating layer 63.

In this structure, the fifth insulating layer 62, the fourth insulating layer 61, and the seventh insulating layer 52A are arranged in this order from the wiring layer 80 toward the substrate 30 in the structure that alleviates electric field concentration on the wiring layer 80. . In other words, the structure is such that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30 as a structure for alleviating electric field concentration on the wiring layer 80 .

Further, the sixth insulating layer 63 covering the wiring layer 80 has a lower dielectric constant than the fifth insulating layer 62. The sixth insulating layer 63 may have a lower dielectric constant than the fourth insulating layer 61. The sixth insulating layer 63 is formed of a material containing any one of SiON, SiC, and _SiO2 . In the first embodiment, the sixth insulating layer 63 has a lower dielectric constant than the fourth insulating layer 61 and is therefore formed of a material containing SiO ₂ . This increases the insulation between the wiring layers 80 adjacent in the Y-axis direction.

Note that the thickness of each of the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A can be changed arbitrarily. In one example, the thickness of the fourth insulating layer 61 may be thinner than the thickness of the fifth insulating layer 62. Further, in one example, the thickness of the fourth insulating layer 61 may be thicker than the thickness of the fifth insulating layer 62. Further, in one example, the thickness of the fourth insulating layer 61, the thickness of the fifth insulating layer 62, and the thickness of the seventh insulating layer 52A may be equal to each other. Further, in one example, the thickness of the fourth insulating layer 61 and the thickness of the fifth insulating layer 62 may be equal to each other and thinner than the thickness of the seventh insulating layer 52A. Further, in one example, the thickness of the seventh insulating layer 52A may be equal to the thickness of the sixth insulating layer 63. Further, in one example, the thickness of the seventh insulating layer 52A may be thinner than the thickness of the sixth insulating layer 63.

(Electric field relaxation structure of terminal)
As shown in FIG. 7, the element insulating layer 40 includes a structure that alleviates the concentration of the electric field generated at the terminal P1. In one example, the element insulating layer 40 includes a third insulating layer 73, an eighth insulating layer 91, and a ninth insulating layer 92 as a structure that alleviates electric field concentration at the terminal P1. The first chip 14 of the first embodiment includes terminals P1 to P5 shown in FIG. The terminals P2 to P5 are also formed in the same manner as the terminal P1. In FIG. 7, a structure for alleviating electric field concentration using the terminal P1 will be described.

The eighth insulating layer 91 is laminated on the third insulating layer 73. The ninth insulating layer 92 is laminated on the eighth insulating layer 91. A terminal P1 is arranged on the ninth insulating layer 92. Both the eighth insulating layer 91 and the ninth insulating layer 92 are spaced apart from the semiconductor resistance layer 20 in the Z-axis direction.

The ninth insulating layer 92 in contact with the terminal P1 is formed of a material containing, for example, SiN. Therefore, the relative dielectric constant of the ninth insulating layer 92 is about 7. In the illustrated example, the thickness of the ninth insulating layer 92 is thinner than the thickness of the eighth insulating layer 91. Further, the thickness of the ninth insulating layer 92 is thinner than the thickness of the third insulating layer 73.

In the illustrated example, the thickness of the ninth insulating layer 92 is equal to the thickness of the second insulating layer 72. Here, if the difference between the thickness of the ninth insulating layer 92 and the thickness of the second insulating layer 72 is within 20% of the thickness of the second insulating layer 72, the thickness of the ninth insulating layer 92 is It can be said that the thickness is equal to the thickness of the insulating layer 72. The thickness of the ninth insulating layer 92 is thinner than the thickness of the first insulating layer 71. The thickness of the ninth insulating layer 92 is thicker than both the thickness of the fourth insulating layer 61 and the thickness of the fifth insulating layer 62. The thickness of the ninth insulating layer 92 is thinner than the thickness of the sixth insulating layer 63.

The eighth insulating layer 91 is spaced apart from the terminal P1 in the Z-axis direction via the ninth insulating layer 92. The eighth insulating layer 91 has a lower dielectric constant than the ninth insulating layer 92. The relative permittivity of the eighth insulating layer 91 is greater than 3.8 and less than 7. In one example, the relative dielectric constant of the eighth insulating layer 91 may be greater than 4 and less than 7. In the first embodiment, the eighth insulating layer 91 is made of a material containing SiON. Therefore, the dielectric constant of the eighth insulating layer 91 is adjusted according to the concentration of N (nitrogen) in SiON. In the illustrated example, the eighth insulating layer 91 has a smaller thickness than the third insulating layer 73. The thickness of the eighth insulating layer 91 is equal to the thickness of the first insulating layer 71. Here, if the difference between the thickness of the eighth insulating layer 91 and the thickness of the first insulating layer 71 is within 20% of the thickness of the first insulating layer 71, the thickness of the eighth insulating layer 91 is It can be said that the thickness is equal to the thickness of the insulating layer 71.

The third insulating layer 73 is spaced apart from the terminal P1 in the Z-axis direction. Since the third insulating layer 73 is formed of a material containing SiO ₂ as described above, it has a lower dielectric constant than the eighth insulating layer 91.

In this structure, the ninth insulating layer 92, the eighth insulating layer 91, and the third insulating layer 73 are arranged in this order from the terminals P1 to P5 toward the substrate 30 in the structure that alleviates the electric field concentration on the terminals P1 to P5. ing. In other words, the structure is such that the dielectric constant decreases from the terminals P1 to P5 toward the substrate 30, as a structure to alleviate electric field concentration on the terminals P1 to P5.

Note that the thickness of each of the eighth insulating layer 91, the ninth insulating layer 92, and the third insulating layer 73 can be changed arbitrarily. In one example, the thickness of the eighth insulating layer 91 and the thickness of the ninth insulating layer 92 may be equal to each other. Further, in one example, the thickness of the eighth insulating layer 91 may be thicker than the thickness of the ninth insulating layer 92. Further, in one example, the thickness of the eighth insulating layer 91, the thickness of the ninth insulating layer 92, and the thickness of the third insulating layer 73 may be equal to each other.

Each of the terminals P1 to P5 and the wiring layer 80 are electrically connected by vias 93. The via 93 extends in the Z-axis direction, which is the thickness direction of the element insulating layer 40. More specifically, as shown in FIG. By penetrating the layer 63 in the Z-axis direction, it is in contact with both the terminal P1 and the wiring layer 80. Although not shown, the connection structure between each of the terminals P2 to P5 and the wiring layer 80 by the via 93 is also similar. Via 93 is formed of the same material as via 90, for example.

[Method for manufacturing semiconductor device]
An example of a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 8 to 16. For convenience, in the following description, components common to the semiconductor device 10 will be given the same reference numerals even in the manufacturing process of the semiconductor device 10.

As shown in FIG. 8, the method for manufacturing the semiconductor device 10 includes the steps of preparing a substrate 30 and forming a substrate-side insulating layer 50 on the substrate 30.
First, the substrate 30 is prepared. The substrate 30 is, for example, a Si substrate. Subsequently, a step of forming a substrate-side insulating layer 50 on the substrate 30 is performed. In one example, in this step, after the second substrate-side insulating layer 52 is formed on the substrate 30, the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are alternately laminated. The first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are formed, for example, by chemical vapor deposition (CVD). In the first embodiment, the first substrate-side insulating layer 51 is a SiN film, and the second substrate-side insulating layer 52 is an SiO ₂ film. Further, the second substrate-side insulating layer 52, which is the uppermost layer of the substrate-side insulating layer 50, constitutes a seventh insulating layer 52A.

As shown in FIG. 9, the method for manufacturing the semiconductor device 10 includes a step of forming a part of the wiring side insulating layer 60. More specifically, the method for manufacturing the semiconductor device 10 includes a step of forming a fourth insulating layer 61 and a step of forming a fifth insulating layer 62.

In the step of forming the fourth insulating layer 61, the fourth insulating layer 61 is formed by, for example, CVD so as to be deposited on the second substrate side insulating layer 52, which becomes the seventh insulating layer 52A. Subsequently, in the step of forming the fifth insulating layer 62, the fifth insulating layer 62 is deposited on the fourth insulating layer 61 by, for example, CVD. In the first embodiment, the fourth insulating layer 61 is a SiON film, and the fifth insulating layer 62 is a SiN film.

As shown in FIG. 10, the method for manufacturing the semiconductor device 10 includes a step of forming a wiring layer 80. More specifically, in this step, a metal film (not shown), which is a material film of the wiring layer 80, is formed on the fifth insulating layer 62 over the entire surface of the fifth insulating layer 62 by, for example, sputtering. For example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected for the metal film. Subsequently, a wiring layer 80 is formed by patterning the metal film by, for example, lithography and etching.

As shown in FIG. 11, the method for manufacturing the semiconductor device 10 includes a step of forming the remainder of the wiring-side insulating layer 60 and a step of forming a part of the resistance-side insulating layer 70.
The step of forming the remainder of the wiring-side insulating layer 60 includes the step of forming a sixth insulating layer 63. In this step, the sixth insulating layer 63 is formed by depositing on the fifth insulating layer 62 and the wiring layer 80, for example, by CVD. Thereby, the wiring layer 80 is covered with the fifth insulating layer 62 and the sixth insulating layer 63. In the first embodiment, the sixth insulating layer 63 is a SiO ₂ film.

The step of forming a part of the resistance side insulating layer 70 includes a step of forming a first insulating layer 71 and a step of forming a second insulating layer 72. More specifically, in the step of forming the first insulating layer 71, the first insulating layer 71 is deposited on the sixth insulating layer 63 by, for example, CVD. In the step of forming the second insulating layer 72, the second insulating layer 72 is deposited on the first insulating layer 71 by, for example, CVD. In the first embodiment, the first insulating layer 71 is a SiON film, and the second insulating layer 72 is a SiN film.

As shown in FIG. 12, the method for manufacturing the semiconductor device 10 includes a step of forming a via 90. More specifically, in this step, via openings 801 are first formed by etching, for example. The via opening 801 is formed to penetrate both the first insulating layer 71 and the second insulating layer 72 in the Z-axis direction, and to expose a part of the wiring layer 80 to the sixth insulating layer 63. . Subsequently, via opening 801 is filled with a metal material, for example, by sputtering. As the metal material, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected, for example. As a result, vias 90 are formed.

As shown in FIG. 13, the method for manufacturing the semiconductor device 10 includes a step of forming a semiconductor resistance layer 20. More specifically, in this step, a resistive material film, which is a material film of the semiconductor resistive layer 20, is first formed on the second insulating layer 72. The resistive material film is formed over the entire surface of the second insulating layer 72. The resistive material film is made of CrSi, for example. Subsequently, the semiconductor resistance layer 20 is formed by patterning the resistance material film by, for example, lithography and etching. Thereby, the upper end of the via 90 is connected to the semiconductor resistance layer 20.

As shown in FIG. 14, the method for manufacturing the semiconductor device 10 includes a step of forming the remainder of the resistance-side insulating layer 70, a step of forming an eighth insulating layer 91, a step of forming a ninth insulating layer 92, including. The step of forming the remainder of the resistance-side insulating layer 70 includes the step of forming a third insulating layer 73.

In the step of forming the third insulating layer 73, the third insulating layer 73 is formed by depositing on the second insulating layer 72 and the semiconductor resistance layer 20, for example, by CVD. In the step of forming the eighth insulating layer 91, the eighth insulating layer 91 is formed by depositing on the third insulating layer 73, for example, by CVD. In the step of forming the ninth insulating layer 92, the ninth insulating layer 92 is deposited on the eighth insulating layer 91 by, for example, CVD. In the first embodiment, the third insulating layer 73 is an SiO ₂ film, the eighth insulating layer 91 is an SiON film, and the ninth insulating layer 92 is an SiN film.

As shown in FIG. 15, the method for manufacturing the semiconductor device 10 includes a step of forming a via 93. More specifically, in this step, via openings 802 are first formed, for example, by etching. The via opening 802 penetrates the ninth insulating layer 92 , the eighth insulating layer 91 , the third insulating layer 73 , the second insulating layer 72 , and the first insulating layer 71 in the Z-axis direction, and also extends through the sixth insulating layer 63 . The wiring layer 80 is formed so as to be partially exposed. Subsequently, via opening 802 is filled with a metal material, for example, by sputtering. As the metal material, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected, for example. As a result, vias 93 are formed.

As shown in FIG. 16, the method for manufacturing the semiconductor device 10 includes a step of forming terminals P1 to P5. More specifically, in this step, a metal film (not shown), which is a material film for the terminals P1 to P5, is formed over the entire surface of the ninth insulating layer 92 on the ninth insulating layer 92 by, for example, sputtering. For example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, Ni, Pd, and W is appropriately selected for the metal film. Subsequently, terminals P1 to P5 are formed by patterning the metal film by, for example, lithography and etching. Note that in FIG. 16, for convenience, only the terminal P1 among the terminals P1 to P5 is shown.

Although not shown, the method for manufacturing the semiconductor device 10 includes a step of forming a passivation film 43. More specifically, in this step, a passivation material film, which is the material film of the passivation film 43, is first formed on the ninth insulating layer 92 and on the terminals P1 to P5 by, for example, CVD. Subsequently, a portion of the passivation material film covering the terminals P1 to P5 is removed, for example, by etching. In other words, some of the terminals P1 to P5 are exposed from the passivation material film. The passivation material film is, for example, a SiN film. As a result, a passivation film 43 is formed. The first chip 14 is formed through the above steps.

Although not shown, the method for manufacturing the semiconductor device 10 includes the steps of preparing the first chip 14 and the second chip 15, preparing a lead frame, and leading the first chip 14 and the second chip 15. It includes a step of mounting on a frame, a step of forming wires W1 to W11, a step of forming sealing resin 16, and a step of dividing into pieces.

In the step of preparing a lead frame, a lead frame including a frame 11, a die pad 12, and leads 13A to 13G (see FIG. 1) is prepared.
In the step of mounting the first chip 14 and the second chip 15 on the lead frame, the first chip 14 is die-bonded to the die pad portion 11A (see FIG. 1) of the frame 11, and the second chip 15 is die-bonded to the die pad 12. Ru.

In the step of forming wires W1 to W11, W1 to W11 are formed by a wire bonding device. That is, W1 to W11 are bonding wires.
In the step of forming the sealing resin 16, the resin layer sealing the frame 11, the die pad 12, the leads 13A to 13G, the first chip 14, the second chip 15, and the wires W1 to W11 is formed by, for example, transfer molding. Ru. For example, black epoxy resin is used for the resin layer. Note that the resin layer may be formed by compression molding, for example.

In the step of singulating, the lead frame and the resin layer are cut, for example, by dicing. As a result, frame 11 and leads 13A to 13G are formed. Through the above steps, the semiconductor device 10 is manufactured.

[effect]
According to the semiconductor device 10 of the first embodiment, the following effects can be obtained.
(1-1) The semiconductor device 10 includes an element insulating layer 40 having an element front surface 41 and an element back surface 42 opposite to the element front surface 41, and a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40. , is provided. Each semiconductor resistance layer 20 includes a resistance back surface 27 facing the element back surface 42 in the thickness direction (Z-axis direction) of the element insulating layer 40, a resistance surface 28 on the opposite side to the resistance back surface 27, and a resistance surface 27 and a resistance surface. 28. The element insulating layer 40 includes a first insulating layer 71 , a second insulating layer 72 laminated on the first insulating layer 71 , a second insulating layer 72 having a higher dielectric constant than the first insulating layer 71 , and a second insulating layer 72 laminated on the second insulating layer 72 . and a third insulating layer 73 having a lower dielectric constant than the second insulating layer 72. Each semiconductor resistance layer 20 is stacked on the second insulating layer 72 . Each semiconductor resistance layer 20 is provided within the third insulating layer 73 with the resistor back surface 27 in contact with the second insulating layer 72 .

According to this configuration, since the resistor back surface 27 of the semiconductor resistance layer 20 is in contact with the second insulating layer 72 having a higher dielectric constant than the third insulating layer 73, the resistor back surface 27 of the element insulating layer 40 is connected to the element back surface 40 of the element insulating layer 40. It is possible to reduce the electric field strength directed toward . Therefore, electric field concentration in the semiconductor resistance layer 20 can be alleviated.

In addition, the dielectric constant decreases in the order of the semiconductor resistance layer 20, the second insulating layer 72, and the first insulating layer 71. That is, in the direction from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases as the distance from the semiconductor resistance layer 20 increases. Thereby, the electric field strength directed from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration in the semiconductor resistance layer 20 can be further alleviated.

(1-2) The plurality of semiconductor resistance layers 20 are aligned in the thickness direction (Z-axis direction) of the element insulating layer 40 and in a direction perpendicular to the thickness direction (Y-axis direction in the first embodiment). are arranged separately.

According to this configuration, the first insulating layer 71 and the second insulating layer 72 that are common to the plurality of semiconductor resistance layers 20 can realize a structure that alleviates electric field concentration in each semiconductor resistance layer 20. Therefore, compared to a structure in which a plurality of semiconductor resistance layers 20 are provided at different positions in the Z-axis direction, a structure that alleviates electric field concentration in each semiconductor resistance layer 20 can be easily realized.

(1-3) The semiconductor device 10 includes a wiring layer 80 provided on the element back surface 42 side of the element insulating layer 40 with respect to the semiconductor resistance layer 20 and electrically connected to the semiconductor resistance layer 20. The wiring layer 80 includes a wiring surface 82 facing the semiconductor resistance layer 20 in the thickness direction (Z-axis direction) of the element insulating layer 40, a wiring back surface 81 opposite to the wiring surface 82, and a wiring surface 82 and a wiring back surface 81. and a wiring side surface 83 that connects the wiring. The element insulating layer 40 includes a fourth insulating layer 61 and a fifth insulating layer 62 stacked on the fourth insulating layer 61 and having a higher dielectric constant than the fourth insulating layer 61. The wiring layer 80 is laminated on the fifth insulating layer 62 , and the wiring back surface 81 is in contact with the fifth insulating layer 62 .

According to this configuration, since the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62 having a higher dielectric constant than the fourth insulating layer 61, the wiring back surface 81 is in contact with the element back surface 42 of the element insulating layer 40. It is possible to reduce the electric field strength toward the Therefore, electric field concentration in the wiring layer 80 can be alleviated.

In addition, the relative dielectric constant decreases in the order of the wiring layer 80, the fifth insulating layer 62, and the fourth insulating layer 61. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the relative permittivity gradually decreases as the distance from the wiring layer 80 increases. Thereby, the electric field strength directed from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration in the wiring layer 80 can be further alleviated.

(1-4) The element insulating layer 40 is provided between the fifth insulating layer 62 and the first insulating layer 71 and includes a sixth insulating layer 63 having a lower dielectric constant than the fifth insulating layer 62. The first insulating layer 71 is stacked on the sixth insulating layer 63. The sixth insulating layer 63 has a lower dielectric constant than the first insulating layer 71.

According to this configuration, the dielectric constant decreases in the order of the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the sixth insulating layer 63. That is, in the direction from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases as the distance from the semiconductor resistance layer 20 increases. Thereby, the electric field strength directed from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration in the semiconductor resistance layer 20 can be further alleviated.

(1-5) The element insulating layer 40 includes a seventh insulating layer 52A having a lower dielectric constant than the fourth insulating layer 61. The fourth insulating layer 61 is laminated on the seventh insulating layer 52A.
According to this configuration, the dielectric constant decreases in the order of the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the seventh insulating layer 52A. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the relative permittivity gradually decreases as the distance from the wiring layer 80 increases. Thereby, the electric field strength directed from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration in the wiring layer 80 can be further alleviated.

(1-6) The element insulating layer 40 is laminated on the third insulating layer 73, and an eighth insulating layer 91 having a higher dielectric constant than the third insulating layer 73, and the eighth insulating layer 91 is laminated, a ninth insulating layer 92 having a higher dielectric constant than the eighth insulating layer 91; The semiconductor device 10 further includes terminals P1 to P5 as electrode pads formed on the ninth insulating layer 92.

According to this configuration, since the terminals P1 to P5 are in contact with the ninth insulating layer 92 having a higher dielectric constant than the third insulating layer 73 and the eighth insulating layer 91, the terminals P1 to P5 are connected to the element insulating layer 40. The electric field intensity directed toward the back surface 42 of the element can be reduced. Therefore, electric field concentration at the terminals P1 to P5 can be alleviated.

In addition, the relative dielectric constant decreases in the order of the ninth insulating layer 92, the eighth insulating layer 91, and the third insulating layer 73 from the terminals P1 to P5. That is, in the direction from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40, the relative dielectric constant gradually decreases as the distance from the wiring layer 80 increases. Thereby, the electric field intensity directed from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration at the terminals P1 to P5 can be further alleviated.

(1-7) The semiconductor device 10 includes an element insulating layer 40, a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40, and electrically connected to the semiconductor resistance layer 20 in the element insulating layer 40, A wiring layer 80 is provided facing the semiconductor resistance layer 20 in the thickness direction (Z-axis direction) of the element insulating layer 40. The wiring layer 80 includes a wiring surface 82 facing the semiconductor resistance layer 20 in the thickness direction of the element insulating layer 40, a wiring back surface 81 opposite to the wiring surface 82, and a wiring side surface connecting the wiring surface 82 and the wiring back surface 81. 83. The element insulating layer 40 includes a fourth insulating layer 61 and a fifth insulating layer 62 that is laminated on the fourth insulating layer 61 and has a dielectric constant higher than that of the fourth insulating layer 61, and a fifth insulating layer 62 that is laminated on the fifth insulating layer 62. and a sixth insulating layer 63 having a lower dielectric constant than the fifth insulating layer 62. The wiring layer 80 is laminated on the fifth insulating layer 62 , and is provided in the sixth insulating layer 63 with the wiring back surface 81 in contact with the fifth insulating layer 62 .

According to this configuration, since the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62 having a higher dielectric constant than the sixth insulating layer 63, the wiring back surface 81 is in contact with the element back surface 42 of the element insulating layer 40. It is possible to reduce the electric field strength toward the Therefore, electric field concentration in the wiring layer 80 can be alleviated.

<Second embodiment>
The semiconductor device 10 of the second embodiment will be described with reference to FIGS. 17 to 19. The semiconductor device 10 of the second embodiment has a different electric field relaxation structure compared to the semiconductor device 10 of the first embodiment. In the following, points different from the first embodiment will be explained in detail, and the same reference numerals will be given to the same components as in the first embodiment, and the explanation thereof will be omitted.

As shown in FIG. 17, in the semiconductor device 10 of the second embodiment, the element insulating layer 40 includes a surface-side insulating layer 100 instead of the wiring-side insulating layer 60 and the resistance-side insulating layer 70 (both shown in FIG. 5). include. More specifically, the element insulating layer 40 has a single-layer structure of the first insulating layer 71 instead of the laminated structure of the sixth insulating layer 63 and the first insulating layer 71 in the first embodiment (see FIG. 5). Be prepared. Further, the element insulating layer 40 has a single-layer structure of the third insulating layer 73 instead of the laminated structure of the third insulating layer 73 and the eighth insulating layer 91 (see FIG. 5) in the first embodiment. That is, the front side insulating layer 100 includes the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the fourth insulating layer 61, the fifth insulating layer 62, the seventh insulating layer 52A, and the ninth insulating layer Contains 92. It can also be said that the front side insulating layer 100 includes the resistance side insulating layer 70. Here, in the second embodiment, the first insulating layer 71 corresponds to a "low dielectric constant insulating layer".

The electric field relaxation structure of the semiconductor resistance layer 20 of the second embodiment includes the first insulating layer 71 and the second insulating layer 72 and does not include the sixth insulating layer 63. Therefore, in the second embodiment, the first insulating layer 71 is laminated on the fifth insulating layer 62. The first insulating layer 71 is in contact with the fifth insulating layer 62.

The thickness of the first insulating layer 71 is thicker than the thickness of the first insulating layer 71 of the first embodiment. The thickness of the first insulating layer 71 is thicker than the thickness of the second substrate side insulating layer 52 (seventh insulating layer 52A). The first insulating layer 71 has a lower dielectric constant than the second insulating layer 72. The dielectric constant of the first insulating layer 71 is greater than 3.8 and less than 7. In one example, the dielectric constant of the first insulating layer 71 may be greater than 4 and less than 7. The first insulating layer 71 is made of a material containing SiON, similarly to the first embodiment. Therefore, the dielectric constant of the first insulating layer 71 is adjusted according to the concentration of N (nitrogen) in SiON.

The second insulating layer 72 is an insulating layer in contact with the resistor back surface 27 of the semiconductor resistance layer 20, and is formed of a material containing SiN, as in the first embodiment. The thickness of the second insulating layer 72 is the same as in the first embodiment.

In this way, in the structure that alleviates the electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72 and the first insulating layer 71 are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure is such that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30 as a structure for alleviating electric field concentration on the semiconductor resistance layer 20 .

Further, the third insulating layer 73 covering the semiconductor resistance layer 20 has a lower dielectric constant than the second insulating layer 72. In the second embodiment, the third insulating layer 73 is formed of a material containing SiON or SiC, unlike the first embodiment. In the second embodiment, the third insulating layer 73 is made of a material containing SiON, like the first insulating layer 71. That is, the relative permittivity of the third insulating layer 73 and the relative permittivity of the first insulating layer 71 are equal to each other.

In the illustrated example, the thickness of the third insulating layer 73 is thicker than the thickness of the third insulating layer 73 of the first embodiment. The thickness of the third insulating layer 73 is thicker than both the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72.

Note that the thickness of each of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 can be changed arbitrarily. In one example, the thickness of the first insulating layer 71, the thickness of the second insulating layer 72, and the thickness of the third insulating layer 73 may be equal to each other. Further, in one example, the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72 may be equal to each other and thinner than the thickness of the third insulating layer 73. Further, in one example, the thickness of the second insulating layer 72 may be thicker than the thickness of the first insulating layer 71.

As shown in FIG. 18, the electric field relaxation structure of the wiring layer 80 of the second embodiment is the same as the electric field relaxation structure of the wiring layer 80 of the first embodiment. That is, the electric field relaxation structure of the wiring layer 80 includes the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A.

As shown in FIG. 19, the semiconductor device 10 of the second embodiment has a third insulating layer 73 instead of the laminated structure of the third insulating layer 73 and the eighth insulating layer 91 of the first embodiment (see FIG. 5). It has a single layer structure. Therefore, the electric field relaxation structure of the terminals P1 to P5 of the second embodiment includes the third insulating layer 73 and the ninth insulating layer 92.

The ninth insulating layer 92 is laminated on the third insulating layer 73. The ninth insulating layer 92 is in contact with the third insulating layer 73. The ninth insulating layer 92 is made of a material containing SiN, similarly to the first embodiment. The third insulating layer 73 is formed of a material containing SiON, similarly to the second embodiment. That is, the relative dielectric constant of the third insulating layer 73 is lower than that of the ninth insulating layer 92.

In this way, in the structure that alleviates the electric field concentration on the terminals P1 to P5, the ninth insulating layer 92 and the third insulating layer 73 are arranged in this order from the terminals P1 to P5 toward the substrate 30. In other words, the structure is such that the dielectric constant decreases from the terminals P1 to P5 toward the substrate 30, as a structure to alleviate electric field concentration on the terminals P1 to P5.

[effect]
According to the semiconductor device 10 of the second embodiment, in addition to the effects (1-1) to (1-3), (1-5), and (1-8) of the first embodiment, the following effects are achieved. can get.

(2-1) The semiconductor device 10 includes an element insulating layer 40, a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40, and electrically connected to the semiconductor resistance layer 20 in the element insulating layer 40, A wiring layer 80 is provided facing the semiconductor resistance layer 20 in the thickness direction (Z-axis direction) of the element insulating layer 40. The wiring layer 80 includes a wiring surface 82 facing the semiconductor resistance layer 20 in the thickness direction of the element insulating layer 40, a wiring back surface 81 opposite to the wiring surface 82, and a wiring side surface connecting the wiring surface 82 and the wiring back surface 81. 83. The element insulating layer 40 includes a fourth insulating layer 61 and a fifth insulating layer 62 that is laminated on the fourth insulating layer 61 and has a dielectric constant higher than that of the fourth insulating layer 61, and a fifth insulating layer 62 that is laminated on the fifth insulating layer 62. and a first insulating layer 71 having a lower dielectric constant than the fifth insulating layer 62. The wiring layer 80 is laminated on the fifth insulating layer 62 , and is provided in the first insulating layer 71 with the wiring back surface 81 in contact with the fifth insulating layer 62 .

According to this configuration, since the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62 having a higher dielectric constant than the first insulating layer 71, the wiring back surface 81 is in contact with the element back surface 42 of the element insulating layer 40. It is possible to reduce the electric field strength toward the Therefore, electric field concentration in the wiring layer 80 can be alleviated.

(2-2) The element insulating layer 40 is laminated on the third insulating layer 73 and includes the ninth insulating layer 92 as a high dielectric constant insulating layer having a higher dielectric constant than the third insulating layer 73. The semiconductor device 10 further includes terminals P1 to P5 as electrode pads formed on the ninth insulating layer 92.

According to this configuration, since the terminals P1 to P5 are in contact with the ninth insulating layer 92 having a higher dielectric constant than the third insulating layer 73, an electric field directed from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40 Strength can be reduced. Therefore, electric field concentration at the terminals P1 to P5 can be alleviated.

In addition, the relative permittivity decreases in the order of terminals P1 to P5 to ninth insulating layer 92 and third insulating layer 73. That is, in the direction from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40, the relative dielectric constant gradually decreases as the distance from the wiring layer 80 increases. Thereby, the electric field intensity directed from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40 can be further reduced. Therefore, electric field concentration at the terminals P1 to P5 can be further alleviated.

<Third embodiment>
The semiconductor device 10 of the third embodiment will be described with reference to FIGS. 20 to 22. The semiconductor device 10 of the third embodiment has a different electric field relaxation structure compared to the semiconductor device 10 of the first embodiment. In the following, points different from the first embodiment will be explained in detail, and components common to the first embodiment will be denoted by the same reference numerals, and their explanation will be omitted.

As shown in FIG. 20, in the semiconductor device 10 of the third embodiment, the element insulating layer 40 is similar to the wiring-side insulating layer 60 and the resistance-side insulating layer 70 (both shown in FIG. 5) of the semiconductor device 10 of the first embodiment. Instead, a front side insulating layer 100 is provided. More specifically, the element insulating layer 40 has a single-layer structure of the first insulating layer 71 instead of the laminated structure of the sixth insulating layer 63 and the first insulating layer 71 in the first embodiment (see FIG. 5). Be prepared. Further, the element insulating layer 40 has a single layer structure of the third insulating layer 73 instead of the laminated structure of the third insulating layer 73, the eighth insulating layer 91, and the ninth insulating layer 92 (see FIG. 5) in the first embodiment. It has a layered structure. That is, the front side insulating layer 100 includes the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A. It can also be said that the front side insulating layer 100 includes the resistance side insulating layer 70. Here, in the third embodiment, the first insulating layer 71 corresponds to a "low dielectric constant insulating layer".

As shown in FIG. 20, in the third embodiment, the electric field relaxation structure of the semiconductor resistance layer 20 is the same as the electric field relaxation structure of the semiconductor resistance layer 20 of the second embodiment.
As shown in FIG. 21, in the third embodiment, the electric field relaxation structure of the wiring layer 80 is the same as the electric field relaxation structure of the wiring layer 80 of the first and second embodiments.

As shown in FIG. 22, in the third embodiment, the electric field relaxation structure of the terminals P1 to P5 is omitted. That is, the semiconductor device 10 of the third embodiment does not include both the eighth insulating layer 91 and the ninth insulating layer 92 (see FIG. 7).

Terminals P1 to P5 are formed on the third insulating layer 73. The terminals P1 to P5 are in contact with the third insulating layer 73. The third insulating layer 73 is made of a material containing SiO ₂ similarly to the first embodiment. Terminals P1 to P5 are covered with a passivation film 43, similar to the first embodiment. According to the third embodiment, effects (1-1) to (1-3), (1-5), and (1-8) of the first embodiment and (2-1) of the second embodiment are obtained. You can obtain the following effects.

<Example of change>
Each of the above embodiments can be modified and implemented as follows. Further, each of the above embodiments and the following modified examples can be implemented in combination with each other within a technically consistent range.

- In each of the above embodiments, the positional relationship between the semiconductor resistance layer 20 and the wiring layer 80 in the Z-axis direction can be changed arbitrarily.
In one example, as shown in FIG. 23, the wiring layer 80 may be arranged closer to the element surface 41 of the element insulating layer 40 than the semiconductor resistance layer 20 is. In other words, the wiring layer 80 may be arranged between the semiconductor resistance layer 20 and the terminals P1 to P5 in the Z-axis direction.

As the position of the wiring layer 80 in the Z-axis direction is changed, the positions of the fourth insulating layer 61, the fifth insulating layer 62, and the sixth insulating layer 63 in the Z-axis direction are changed. As the positions of the fourth insulating layer 61, the fifth insulating layer 62, and the sixth insulating layer 63 are changed in the Z-axis direction, the Z-axis of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 are changed. The position of the direction is changed. That is, in the illustrated example, it can be said that the position of the wiring-side insulating layer 60 in the Z-axis direction and the position of the resistance-side insulating layer 70 in the Z-axis direction are interchanged.

More specifically, the fourth insulating layer 61 is laminated on the third insulating layer 73. The fifth insulating layer 62 is laminated on the fourth insulating layer 61. The wiring layer 80 is formed on the fifth insulating layer 62. The sixth insulating layer 63 is laminated on the fifth insulating layer 62 and covers the wiring layer 80. Here, similarly to the first embodiment, the fourth insulating layer 61 is made of a material containing SiON, the fifth insulating layer 62 is made of a material containing SiN, and the sixth insulating layer 63 is made of a material containing SiO2. It is made of a material containing ₂ .

The first insulating layer 71 is laminated on the seventh insulating layer 52A. The second insulating layer 72 is laminated on the first insulating layer 71. The semiconductor resistance layer 20 is formed on the second insulating layer 72. The third insulating layer 73 is stacked on the second insulating layer 72 and covers the semiconductor resistance layer 20 . Here, similarly to the first embodiment, the first insulating layer 71 is made of a material containing SiON, the second insulating layer 72 is made of a material containing SiN, and the third insulating layer 73 is made of a material containing SiO2. It is made of a material containing ₂ . Furthermore, the seventh insulating layer 52A is formed of a material containing SiO ₂ .

The via 90 penetrates the fourth insulating layer 61, the fifth insulating layer 62, and the third insulating layer 73 to connect the semiconductor resistance layer 20 and the wiring layer 80. The via 93 penetrates the ninth insulating layer 92, the eighth insulating layer 91, and the sixth insulating layer 63 to connect the wiring layer 80 and the terminals P1 to P5. The materials forming the

vias

90 and 93 are, for example, the same as those in the first embodiment.

The structure that alleviates electric field concentration on the wiring layer 80 includes a fifth insulating layer 62, a fourth insulating layer 61, and a third insulating layer 73. In the structure that alleviates electric field concentration on the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 are arranged in this order from the wiring layer 80 toward the substrate 30. In other words, the structure is such that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30 as a structure for alleviating electric field concentration on the wiring layer 80 .

The structure that alleviates electric field concentration on the semiconductor resistance layer 20 includes the second insulating layer 72, the first insulating layer 71, and the seventh insulating layer 52A. In the structure that alleviates electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the seventh insulating layer 52A are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure is such that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30 as a structure for alleviating electric field concentration on the semiconductor resistance layer 20 .

The eighth insulating layer 91 is laminated on the sixth insulating layer 63. The ninth insulating layer 92 is laminated on the eighth insulating layer 91. Terminals P1 to P5 are formed on the ninth insulating layer 92. Here, similarly to the first embodiment, the eighth insulating layer 91 is made of a material containing SiON, and the ninth insulating layer 92 is made of a material containing SiN.

The structure that alleviates electric field concentration on terminals P1 to P5 includes a ninth insulating layer 92, an eighth insulating layer 91, and a sixth insulating layer 63. In the structure that alleviates electric field concentration on the terminals P1 to P5, the ninth insulating layer 92, the eighth insulating layer 91, and the sixth insulating layer 63 are arranged in this order from the terminals P1 to P5 toward the substrate 30. In other words, the structure is such that the dielectric constant decreases from the terminals P1 to P5 toward the substrate 30, as a structure to alleviate electric field concentration on the terminals P1 to P5.

According to this configuration, as in the first embodiment, the electric field strength of each of the semiconductor resistance layer 20, the wiring layer 80, and the terminals P1 to P5 can be reduced. Therefore, electric field concentration within the semiconductor device 10 (first chip 14) can be alleviated.

- In each of the above embodiments, the wiring layer 80 may be arranged above the semiconductor resistance layer 20, and the wiring layer 80 may constitute the terminals P1 to P5.
In one example, as shown in FIG. 24, the wiring layer 80 is formed on the element surface 41 of the element insulating layer 40. In other words, the insulating layer including the element surface 41 of the element insulating layer 40 is constituted by the fifth insulating layer 62. The fifth insulating layer 62 is laminated on the fourth insulating layer 61. The fourth insulating layer 61 is laminated on the third insulating layer 73. In this way, in the modification shown in FIG. 24, both the eighth insulating layer 91 and the ninth insulating layer 92 are omitted from the semiconductor device 10.

The passivation film 43 covers both the fifth insulating layer 62 and the wiring layer 80. On the other hand, the passivation film 43 includes an opening 43X that exposes a portion of the wiring layer 80 that constitutes the terminals P1 to P5. In other words, the portions of the wiring layer 80 exposed from the passivation film 43 constitute the terminals P1 to P5.

The via 90 connects the semiconductor resistance layer 20 and the wiring layer 80 by penetrating the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 in the Z-axis direction. The via 90 is formed of the same material as the via 90 of the first embodiment, for example. In the modification shown in FIG. 24, the via 93 is omitted from the semiconductor device 10.

The structure that alleviates electric field concentration on the wiring layer 80 includes a fifth insulating layer 62 , a fourth insulating layer 61 , and a third insulating layer 73 . In the structure that alleviates electric field concentration on the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 are arranged in this order from the wiring layer 80 toward the substrate 30. In other words, the structure is such that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30 as a structure for alleviating electric field concentration on the wiring layer 80 .

According to this configuration, the electric field strength of each of the semiconductor resistance layer 20 and the wiring layer 80 can be reduced, similarly to the first embodiment. Therefore, electric field concentration within the semiconductor device 10 (first chip 14) can be alleviated.

- In each embodiment, the arrangement of the plurality of semiconductor resistance layers 20 can be arbitrarily changed. In one example, the plurality of semiconductor resistance layers 20 may be arranged apart from each other in the X-axis direction. In other words, the plurality of semiconductor resistance layers 20 may be arranged apart from each other in the lateral direction of the first chip 14. Further, at least one of the plurality of semiconductor resistance layers 20 may be arranged at a different position with respect to other semiconductor resistance layers 20 in the thickness direction (Y-axis direction) of the element insulating layer 40.

- In each embodiment, the configuration of the plurality of semiconductor resistance layers 20 can be changed arbitrarily. Moreover, the number of semiconductor resistance layers 20 can be changed arbitrarily.
- In each embodiment, the structure of the substrate side insulating layer 50 can be changed arbitrarily. In one example, the first substrate-side insulating layer 51 may be omitted from the substrate-side insulating layer 50. In this case, for example, the substrate-side insulating layer 50 has a laminated structure of the second substrate-side insulating layer 52.

- In each embodiment, the shape of the first chip 14 in plan view can be arbitrarily changed. In one example, the first chip 14 may have a square shape in plan view.
As used in this disclosure, the term "on" includes the meanings of "on" and "above" unless the context clearly dictates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer.

The Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper" and "lower" in the Z-axis direction described herein are "upper" and "lower" in the vertical direction. Not limited to one thing. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

<Additional notes>
The technical ideas that can be understood from the above embodiment and each modification example will be described below. It should be noted that, for the purpose of assisting understanding rather than with the intention of limiting, the corresponding reference numerals in the embodiments for the configurations described in the supplementary notes are shown in parentheses. The symbols are shown as examples to aid understanding, and the components described with each symbol should not be limited to the components indicated by the symbols.

[Additional note 1]
an element insulating layer (40) having a front surface (41) and a back surface (42) opposite to the front surface (41);
one or more semiconductor resistance layers (20) provided in the element insulating layer (40),
The semiconductor resistance layer (20) is
a resistor back surface (27) facing the back surface (42) in the thickness direction (Z-axis direction) of the element insulating layer (40);
a resistor surface (28) opposite to the resistor back surface (27);
a resistor side surface (29) connecting the resistor back surface (27) and the resistor surface (28);
The element insulating layer (40) is
a first insulating layer (71);
a second insulating layer (72) laminated on the first insulating layer (71) and having a higher dielectric constant than the first insulating layer (71);
a third insulating layer (73) laminated on the second insulating layer (72) and having a lower dielectric constant than the second insulating layer (72);
The semiconductor resistance layer (20) is laminated on the second insulating layer (72), and the third insulating layer ( A semiconductor device (10) provided in 73).

[Additional note 2]
A plurality of the semiconductor resistance layers (20) are provided, and are aligned in the thickness direction (Z-axis direction) of the element insulating layer (40), and in a direction perpendicular to the thickness direction (Z-axis direction). The semiconductor device according to Supplementary Note 1, wherein the semiconductor device is arranged at a distance in the Y-axis direction.

[Additional note 3]
A wiring layer (80) provided on the back surface (42) side of the element insulating layer (40) with respect to the semiconductor resistance layer (20) and electrically connected to the semiconductor resistance layer (20). 3. The semiconductor device according to 1 or 2.

[Additional note 4]
The wiring layer (80) is
a wiring surface (82) facing the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40);
a wiring back surface (81) opposite to the wiring surface (82);
a wiring side surface (83) connecting the wiring surface (82) and the wiring back surface (81);
The element insulating layer (40) is
a fourth insulating layer (61);
a fifth insulating layer (62) laminated on the fourth insulating layer (61) and having a higher dielectric constant than the fourth insulating layer (61);
The semiconductor device according to appendix 3, wherein the wiring layer (80) is laminated on the fifth insulating layer (62), and the wiring back surface (81) is in contact with the fifth insulating layer (62).

[Additional note 5]
The element insulating layer (40) is provided between the fifth insulating layer (62) and the first insulating layer (71), and is a sixth insulating layer having a lower dielectric constant than the fifth insulating layer (62). including an insulating layer (63);
The semiconductor device according to appendix 4, wherein the wiring layer (80) is provided within the sixth insulating layer (63).

[Additional note 6]
The element insulating layer (40) is provided between the fifth insulating layer (62) and the first insulating layer (71), and is a sixth insulating layer having a lower dielectric constant than the fifth insulating layer (62). including an insulating layer (63);
The first insulating layer (71) is laminated on the sixth insulating layer (63),
The semiconductor device according to appendix 4 or 5, wherein the sixth insulating layer (63) has a lower dielectric constant than the first insulating layer (71).

[Additional note 7]
The semiconductor device according to appendix 6, wherein the first insulating layer (71) is spaced apart from the wiring layer (80) in the thickness direction (Z-axis direction) of the element insulating layer (40). .

[Additional note 8]
The first insulating layer (71) is laminated on the fifth insulating layer (62), and has a lower dielectric constant than the fifth insulating layer (62),
The semiconductor device according to any one of appendices 4 to 7, wherein the wiring layer (80) is provided within the first insulating layer (71).

[Additional note 9]
The element insulating layer (40) includes a seventh insulating layer (52A) having a lower dielectric constant than the fourth insulating layer (61),
The semiconductor device according to any one of appendices 4 to 8, wherein the fourth insulating layer (61) is laminated on the seventh insulating layer (52A).

[Additional note 10]
The element insulating layer (40) is
an eighth insulating layer (91) laminated on the third insulating layer (73) and having a higher dielectric constant than the third insulating layer (73);
a ninth insulating layer (92) laminated on the eighth insulating layer (91) and having a higher dielectric constant than the eighth insulating layer (91);
The semiconductor device according to any one of Supplementary Notes 1 to 9, further comprising electrode pads (P1 to P5) formed on the ninth insulating layer (92).

[Additional note 11]
The element insulating layer (40) includes a high dielectric constant insulating layer (92) laminated on the third insulating layer (73) and having a higher dielectric constant than the third insulating layer (37),
The semiconductor device according to any one of appendices 1 to 8, further comprising electrode pads (P1 to P5) formed on the high dielectric constant insulating layer (92).

[Additional note 12]
The device further includes a via (90) extending in the thickness direction (Z-axis direction) of the element insulating layer (40) and electrically connecting the semiconductor resistance layer (20) and the wiring layer (80). 9. The semiconductor device according to any one of 9.

[Additional note 13]
The semiconductor device according to any one of Supplementary Notes 3 to 9, wherein the semiconductor resistance layer (20) has a thickness thinner than the wiring layer (80).

[Additional note 14]
a wiring layer (80) provided on the surface (41) of the element insulating layer (40) and electrically connected to the semiconductor resistance layer (20);
A passivation film (43) provided on the surface (41) of the element insulating layer (40) and covering the wiring layer (80) so as to expose a part of the wiring layer (80). The semiconductor device according to any one of items 1 to 13.

[Additional note 15]
an element insulating layer (40);
one or more semiconductor resistance layers (20) provided within the element insulating layer (40);
electrically connected to the semiconductor resistance layer (20) within the element insulating layer (40), and disposed opposite to the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40); a wiring layer (80),
The wiring layer (80) is
a wiring surface (82) facing the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40);
a wiring back surface (81) opposite to the wiring surface (82);
a wiring side surface (83) connecting the wiring surface (82) and the wiring back surface (81);
The element insulating layer (40) is
a fourth insulating layer (61);
a fifth insulating layer (62) laminated on the fourth insulating layer (61) and having a higher dielectric constant than the fourth insulating layer (61);
a low dielectric constant insulating layer (63/71) laminated on the fifth insulating layer (62) and having a lower dielectric constant than the fifth insulating layer (62);
The wiring layer (80) is laminated on the fifth insulating layer (62), and the low dielectric constant insulating layer ( 63/71).

[Additional note 16]
The element insulating layer (40) further includes a sixth insulating layer (63) having a lower dielectric constant than the fifth insulating layer (62),
The semiconductor device according to appendix 15, wherein the sixth insulating layer (63) is the low dielectric constant insulating layer stacked on the fifth insulating layer (62).

[Additional note 17]
The element insulating layer (40) is
a first insulating layer (71) having a lower dielectric constant than the fifth insulating layer (62);
a second insulating layer (72) laminated on the first insulating layer (71) and having a higher dielectric constant than the first insulating layer (71);
The semiconductor resistance layer (20) is laminated on the second insulating layer (72),
The semiconductor device according to appendix 15, wherein the first insulating layer (71) is the low dielectric constant insulating layer stacked on the fifth insulating layer (62).

[Additional note 18]
The element insulating layer (40) includes a seventh insulating layer (52A) having a lower dielectric constant than the fourth insulating layer (61),
The semiconductor device according to any one of appendices 15 to 17, wherein the fourth insulating layer (61) is laminated on the seventh insulating layer (52A).

[Additional note 19]
an element insulating layer (40) having a front surface (41) and a back surface (42) opposite to the front surface (41);
one or more semiconductor resistance layers (20) provided within the element insulating layer (40);
electrode pads (P1 to P5) provided on the surface (41) of the element insulating layer (40);
a passivation film (43) provided on the surface (41) of the element insulating layer (40) and covering the electrode pads (P1 to P5);
The element insulating layer (40) is
an eighth insulating layer (91);
a ninth insulating layer (92) laminated on the eighth insulating layer (91) and having a higher dielectric constant than the eighth insulating layer (91);
The electrode pads (P1 to P5) are laminated on the ninth insulating layer (92), and are provided in the passivation film (43) in contact with the ninth insulating layer (92). Semiconductor device (10).

[Additional note 20]
one or more semiconductor resistance layers (20) provided within the element insulating layer (40);
electrically connected to the semiconductor resistance layer (20) within the element insulating layer (40), and disposed opposite to the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40); a wiring layer (80),
The semiconductor device according to attachment 19, wherein the electrode pads (P1 to P5) are electrically connected to the semiconductor resistance layer (20) via the wiring layer (80).

[Additional note 21]
The element insulating layer (40) includes a third insulating layer (73) having a lower dielectric constant than the eighth insulating layer (91),
The semiconductor device according to appendix 19 or 20, wherein the eighth insulating layer (91) is stacked on the third insulating layer (73).

[Additional note 22]
further comprising a substrate (30);
The element insulating layer (40) is
a substrate-side insulating layer (50) provided on the substrate (30);
a front-side insulating layer (100) laminated on the substrate-side insulating layer (50),
The front-side insulating layer (100) includes the first insulating layer (71), the second insulating layer (72), and the third insulating layer (73). semiconductor devices.

[Additional note 23]
further comprising a substrate (30);
The element insulating layer (40) is
a substrate-side insulating layer (50) provided on the substrate (30);
a front-side insulating layer (100) laminated on the substrate-side insulating layer (50),
The front side insulating layer (100) includes the first insulating layer (71), the second insulating layer (72), the third insulating layer (73), the fourth insulating layer (74), and the fifth insulating layer (72). The semiconductor device according to appendix 4, including an insulating layer (75).

[Additional note 24]
further comprising a substrate (30);
The element insulating layer (40) is
a substrate-side insulating layer (50) provided on the substrate (30);
a wiring side insulating layer (60) laminated on the substrate side insulating layer (50);
a resistance-side insulating layer (70) laminated on the wiring-side insulating layer (60),
The resistance side insulating layer (70) includes the first insulating layer (71), the second insulating layer (72), and the third insulating layer (73),
The wiring side insulating layer (60) includes the fourth insulating layer (61), the fifth insulating layer (62), and the sixth insulating layer (63). semiconductor devices.

[Additional note 25]
The substrate side insulating layer (50) is
a plurality of first substrate side insulating layers (51);
a plurality of second substrate side insulating layers (52);
The semiconductor according to any one of appendices 22 to 24, wherein the plurality of first substrate side insulating layers (51) and the plurality of second substrate side insulating layers (52) are alternately stacked one by one. Device.

[Additional note 26]
The first substrate side insulating layer (51) is formed of a material containing SiN,
The semiconductor device according to attachment 25, wherein the second substrate side insulating layer (52) is formed of a material containing SiO ₂ .

[Additional note 27]
further comprising a substrate (30);
The wiring layer (80) is arranged to be spaced apart from the substrate (30) in the thickness direction (Z-axis direction) of the element insulating layer (40). Semiconductor equipment.

[Additional note 28]
The first insulating layer (71) is formed of a material containing SiON,
The second insulating layer (72) is formed of a material containing SiN,
The semiconductor device according to any one of appendices 1 to 14, wherein the third insulating layer (73) is formed of a material containing SiO ₂ .

[Additional note 29]
The fourth insulating layer (61) is formed of a material containing SiON,
The semiconductor device according to appendix 4, wherein the fifth insulating layer (62) is formed of a material containing SiN.

[Additional note 30]
The fourth insulating layer (61) is formed of a material containing SiON,
The fifth insulating layer (62) is formed of a material containing SiN,
The semiconductor device according to any one of appendices 5 to 7, wherein the sixth insulating layer (63) is formed of a material containing SiO ₂ .

[Additional note 31]
The semiconductor device according to appendix 9, wherein the seventh insulating layer (52A) is formed of a material containing _SiO2 .

[Additional note 32]
The eighth insulating layer (91) is formed of a material containing SiON,
The semiconductor device according to appendix 10, wherein the ninth insulating layer (92) is formed of a material containing SiN.

[Additional note 33]
The semiconductor device according to any one of Supplementary Notes 1 to 32, wherein the semiconductor resistance layer (20) contains CrSi.

[Additional note 34]
The semiconductor device according to any one of appendices 1 to 14, wherein the first insulating layer (71) has a thickness thinner than the third insulating layer (73).

[Additional note 35]
The semiconductor device according to any one of appendices 1 to 14, wherein the second insulating layer (72) has a thickness thinner than the first insulating layer (71).

[Appendix 36]
The semiconductor device according to any one of appendices 4 to 8, wherein the fifth insulating layer (62) has a thickness thinner than the second insulating layer (72).

[Additional note 37]
The semiconductor device according to any one of appendices 4 to 8, wherein the fourth insulating layer (61) has a thickness thinner than the second insulating layer (72).

[Appendix 38]
The semiconductor device according to any one of appendices 3 to 9, wherein the second insulating layer (72) has a thickness that is less than or equal to the wiring layer (80).

[Additional note 39]
The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the second insulating layer (72) has a thickness greater than the semiconductor resistance layer (20).

[Additional note 40]
The semiconductor device according to appendix 6 or 7, wherein the sixth insulating layer (63) has a thickness greater than both the fourth insulating layer (61) and the fifth insulating layer (62).

[Additional note 41]
The semiconductor device according to appendix 6 or 7, wherein the sixth insulating layer (63) has a greater thickness than the first insulating layer (71).

10... Semiconductor device 11... Frame 11A... First die pad part 11B... First lead part 12... Die pad 13A-13G... Lead 14... First chip 14A-14D... First to fourth resistance circuit 15... Second chip 15A... Voltage detection circuit 16...Sealing resin 16A-16D...First to fourth resin side surfaces 20...Semiconductor resistance layer 21-25...Wiring 27...Resistor back surface 28...Resistor surface 29...Resistor side surface 30...Substrate 40...Element insulating layer 41 ...Element surface 42...Element back surface 43...Passivation film 43X...Opening 50...Substrate side insulating layer 51...First substrate side insulating layer 52...Second substrate side insulating layer 52A...Seventh insulating layer 60...Wiring side insulating layer 61 ... Fourth insulating layer 62... Fifth insulating layer 63... Sixth insulating layer 70... Resistance side insulating layer 71... First insulating layer 72... Second insulating layer 73... Third insulating layer 80... Wiring layer 81... Wiring back surface 82 ... Wiring surface 83... Wiring side surface 90... Via 91... Eighth insulating layer 92... Ninth insulating layer 93... Via 100... Front

side insulating layer

801, 802... Via opening W1 to W11... Wire P1 to P5... Terminal Q1 ~Q9...terminal

Claims

an element insulating layer having a front surface and a back surface opposite to the front surface;
one or more semiconductor resistance layers provided in the element insulating layer;
Equipped with
The semiconductor resistance layer is
a resistor back surface facing the back surface in the thickness direction of the element insulating layer;
a resistor surface opposite to the resistor back surface;
a resistor side surface connecting the resistor back surface and the resistor surface;
including;
The element insulating layer is
a first insulating layer;
a second insulating layer laminated on the first insulating layer and having a higher dielectric constant than the first insulating layer;
a third insulating layer laminated on the second insulating layer and having a lower dielectric constant than the second insulating layer;
including;
The semiconductor resistance layer is stacked on the second insulating layer, and is provided in the third insulating layer with the back surface of the resistor in contact with the second insulating layer.
The semiconductor device according to claim 1, wherein a plurality of the semiconductor resistance layers are provided, and the semiconductor resistance layers are aligned in the thickness direction of the element insulating layer and spaced apart in a direction perpendicular to the thickness direction. .
The semiconductor device according to claim 1 , further comprising a wiring layer provided on the back side of the element insulating layer with respect to the semiconductor resistance layer and electrically connected to the semiconductor resistance layer.
The wiring layer is
a wiring surface facing the semiconductor resistance layer in the thickness direction of the element insulating layer;
a back side of the wiring opposite to the wiring surface;
a wiring side surface connecting the wiring surface and the wiring back surface;
including;
The element insulating layer is
a fourth insulating layer;
a fifth insulating layer laminated on the fourth insulating layer and having a higher dielectric constant than the fourth insulating layer;
including;
The semiconductor device according to claim 3, wherein the wiring layer is stacked on the fifth insulating layer, and the back surface of the wiring is in contact with the fifth insulating layer.
The element insulating layer is provided between the fifth insulating layer and the first insulating layer, and includes a sixth insulating layer having a lower dielectric constant than the fifth insulating layer,
The semiconductor device according to claim 4, wherein the wiring layer is provided within the sixth insulating layer.
The element insulating layer is provided between the fifth insulating layer and the first insulating layer, and includes a sixth insulating layer having a lower dielectric constant than the fifth insulating layer,
The first insulating layer is laminated on the sixth insulating layer,
The semiconductor device according to claim 4 , wherein the sixth insulating layer has a lower dielectric constant than the first insulating layer.
The semiconductor device according to claim 6, wherein the first insulating layer is spaced apart from the wiring layer in the thickness direction of the element insulating layer.
The first insulating layer is laminated on the fifth insulating layer, and has a lower dielectric constant than the fifth insulating layer,
The semiconductor device according to claim 4, wherein the wiring layer is provided within the first insulating layer.
The element insulating layer includes a seventh insulating layer having a lower dielectric constant than the fourth insulating layer,
The semiconductor device according to claim 4, wherein the fourth insulating layer is stacked on the seventh insulating layer.
The element insulating layer is
an eighth insulating layer laminated on the third insulating layer and having a higher dielectric constant than the third insulating layer;
a ninth insulating layer laminated on the eighth insulating layer and having a higher dielectric constant than the eighth insulating layer;
including;
The semiconductor device according to claim 1, further comprising an electrode pad formed on the ninth insulating layer.
The element insulating layer includes a high dielectric constant insulating layer laminated on the third insulating layer and having a higher dielectric constant than the third insulating layer,
The semiconductor device according to claim 1, further comprising an electrode pad formed on the high dielectric constant insulating layer.
10. The semiconductor device according to claim 3, further comprising a via extending in the thickness direction of the element insulating layer and electrically connecting the semiconductor resistance layer and the wiring layer.
The semiconductor device according to claim 3, wherein the semiconductor resistance layer has a thickness thinner than the wiring layer.
a wiring layer provided on the surface of the element insulating layer and electrically connected to the semiconductor resistance layer;
a passivation film provided on the surface of the element insulating layer and covering the wiring layer so as to expose a part of the wiring layer;
The semiconductor device according to any one of claims 1 to 13, comprising:
an element insulating layer;
one or more semiconductor resistance layers provided in the element insulating layer;
a wiring layer electrically connected to the semiconductor resistance layer in the element insulating layer and facing the semiconductor resistance layer in the thickness direction of the element insulating layer;
Equipped with
The wiring layer is
a wiring surface facing the semiconductor resistance layer in the thickness direction of the element insulating layer;
a wiring back surface opposite to the wiring surface;
a wiring side surface connecting the wiring surface and the wiring back surface;
including;
The element insulating layer is
a fourth insulating layer;
a fifth insulating layer laminated on the fourth insulating layer and having a higher dielectric constant than the fourth insulating layer;
a low dielectric constant insulating layer laminated on the fifth insulating layer and having a lower dielectric constant than the fifth insulating layer;
including;
The wiring layer is laminated on the fifth insulating layer, and is provided in the low dielectric constant insulating layer with the back surface of the wiring in contact with the fifth insulating layer.
The element insulating layer further includes a sixth insulating layer having a lower dielectric constant than the fifth insulating layer,
The semiconductor device according to claim 15, wherein the sixth insulating layer is the low dielectric constant insulating layer stacked on the fifth insulating layer.
The element insulating layer is
a first insulating layer having a lower dielectric constant than the fifth insulating layer;
a second insulating layer laminated on the first insulating layer and having a higher dielectric constant than the first insulating layer;
including;
The semiconductor resistance layer is laminated on the second insulating layer,
The semiconductor device according to claim 15, wherein the first insulating layer is the low dielectric constant insulating layer stacked on the fifth insulating layer.