WO2023190400A1

WO2023190400A1 - Method for manufacturing semiconductor device

Info

Publication number: WO2023190400A1
Application number: PCT/JP2023/012313
Authority: WO
Inventors: 大子星野
Original assignee: ラピスセミコンダクタ株式会社
Priority date: 2022-03-29
Filing date: 2023-03-27
Publication date: 2023-10-05

Abstract

The present invention forms a reference mark 22 formed in a first process of a photolithography process of semiconductor device manufacturing and a reference mark 24 formed in a second process following the first process as concentric double square frames, and sets, as a detection position XoRi, a middle point of the width of a signal waveform S representing a change in contrast of image data acquired by an imaging device provided to an optical microscope of an alignment measurement device and including the reference mark 22 and the reference mark 24 in a portion of an intersection between the signal waveform S and a predetermined threshold value Th, and the detection position XoRi is used as a reference for positioning of a layer relating to a third process following the second process.

Description

Manufacturing method of semiconductor device

The present disclosure relates to a method of manufacturing a semiconductor device, and particularly to a method of overlapping resist patterns in a lithography process of semiconductor manufacturing.

The manufacturing process for semiconductor devices involves repeating a film formation process to form a film to be processed, a lithography process to form a resist pattern on a substrate using the semiconductor circuit as a mask, and an etching process to process the film to be processed based on the resist pattern. In this way, an element circuit is formed, but in the lithography process, it is necessary to accurately overlap the resist pattern with the processing pattern formed in the previous process.

For example, assume a processing flow from the first step, which is element isolation processing, to the second step, which is gate processing, and the third step, which is contact hole processing and formation. In this processing flow, as shown in FIG. 6, the reference mark 32 is an outer square frame processed and formed in a pre-process to be aligned, and an inner square frame formed in a post-process photolithography process. A certain photolithography mark 34 is configured as a pair of marks, and the amount of misalignment is determined by understanding the relative vertical and horizontal displacement of the registration mark 34 with respect to the reference mark 32.

Specifically, the detection position is the midpoint of the width of the signal waveform S at the intersection of the signal waveform S converted from the optical image recognized in the mark detection area 32A on the right side of the reference mark 32 and a predetermined threshold Th. Let it be XoRi. Similarly, the detection positions XoLe, YoUp, YoLo, XiRi, XiLe, YiUp, YiLo recognized in the reference mark 32 and other mark detection areas 32B, 32C, 32D, 34A, 34B, 34C, and 34D of the photolithography mark 34, respectively Therefore, the detection position Xo in the X direction and the detection position Yo in the Y direction of the reference mark 32 during alignment measurement, and the detection position Xi in the X direction and detection position Yi in the Y direction of the photolithography mark 34 during alignment measurement are Desired. Then, the difference between the detected position Xi and the detected position Xo is the misalignment amount ΔX in the X direction, and the difference between the detected position Yi and the detected position Yo is the misalignment amount ΔY in the Y direction, which are respectively derived as follows. .
ΔX = Xi - Xo
ΔY = Yi - Yo

7A shows an example of misalignment of the second process with respect to the first process, FIG. 7B shows an example of misalignment of the third process with respect to the first process, and FIG. 7C shows an example of misalignment of the third process with respect to the second process. , respectively.

FIG. 7A shows that when the position of the photolithography mark in the second process corresponding to the reference mark 32 in the first process, which is the previous process, is the actual value 38, whereas the normal value is 36, the true value is This shows a case where misalignment amounts ΔX21 and ΔY21, which are the differences between 36 and the actual value 38 in the X and Y directions, occur.

FIG. 7B shows that when the position of the photolithography mark in the third process corresponding to the reference mark 32 in the first process, which is the previous process, is the actual value 42, whereas the normal value is 40, the true value is This shows a case where misalignment amounts -ΔX31 and -ΔY31, which are the differences between 40 and the actual value 42 in the X and Y directions, occur.

FIG. 7C shows an example of misalignment in the third process relative to the second process when misalignment occurs in FIGS. 7A and 7B.

The misalignment amounts ΔX32 and ΔY32 in the third process relative to the second process are the differences in the X and Y directions between the true value 40 and the actual value 48 shown in FIG. 7C, but theoretically, as shown below, It is calculated based on the difference between the misalignment amounts -ΔX31, -ΔY31 of the third process with respect to the first process and the misalignment amounts ΔX21, ΔY21 of the second process with respect to the first process.
-ΔX32 = -ΔX31-ΔX21
-ΔY32 = -ΔY31-ΔY21

∴ΔX32 = ΔX31+ΔX21
ΔY32 = ΔY31+ΔY21

As a result, the amount of misalignment ΔX32, ΔY32 of the third process with respect to the second process is determined by the amount of misalignment ΔX31, ΔY31 of the third process with respect to the first process added to the amount of misalignment ΔX32, ΔY32 of the second process with respect to the first process. There may be cases where this is done.

FIG. 8A is a schematic diagram showing a state in which the gate pattern 14 is formed in the second step after the element isolation pattern 12 is formed in the first step on the semiconductor substrate 10. In FIG. 8A, the gate pattern 14 formed on the element isolation pattern 12 has a misalignment amount ΔX21 in the second process with respect to the first process.

FIG. 8B is a schematic diagram showing a case where the contact hole pattern 16 is formed in the third step after the gate pattern 14 is formed in the second step on the element isolation pattern 12. In FIG. 8B, the contact hole pattern 16 formed on the element isolation pattern 12 has a misalignment amount ΔX31 in the third process with respect to the first process.

As a result, the misalignment amount ΔX31 is added to the misalignment amount ΔX21, and the gate pattern 14 formed in the second step and the contact hole pattern 16 formed in the third step come into contact, causing leakage current. This results in a problem that occurs.

In the case shown in FIGS. 8A and 8B, the first process is used as the reference for the matching target process, but it is also possible to change the matching target process to the second process. However, even when the second process is used as the alignment target process, the contact hole pattern 16 is misaligned with respect to the element isolation pattern 12 formed in the first process, resulting in increased resistance due to poor grounding with the active region and Problems such as an increase in leakage current may occur.

Japanese Patent No. 5554906 discloses a technique for correcting the orthogonal component of shot shape distortion and the magnification difference in the in-plane direction in hybrid processing in which the lower layer process is performed using a scanner type exposure device and the upper layer process is performed using a batch type exposure device. discloses an invention of an alignment method for an exposure apparatus with high overlay accuracy.

Japanese Unexamined Patent Publication No. 7-142326 discloses that after measuring the error between the first layer and the second layer serving as a reference, and deriving the amount of deviation of each layer, the error is averaged for each layer. An invention of a mask overlay method is disclosed in which the third layer is positioned for exposure at an intermediate position.

However, in the invention disclosed in Japanese Patent No. 5,554,906, the misalignment amounts of each of the plurality of steps may be superimposed as described above.

In the invention disclosed in JP-A-7-142326, the amount of deviation is measured multiple times and the average value of the measured values is calculated, which increases the number of work steps and requires complicated calculations. If the variance of each deviation amount involved in calculating the average value is large, the layer positioning accuracy will decrease even if the deviation amounts are averaged. In addition, the amount of deviation from the first layer and the amount of deviation from the second layer with respect to the third layer must be measured separately, and the processing time becomes longer as the alignment measurement process after exposure is performed multiple times. .

The present disclosure provides a method for manufacturing a semiconductor device that can suppress misalignment of a layer in a post-process with respect to a layer in a pre-process.

A first aspect of the present disclosure is a method for manufacturing a semiconductor device, which includes: a first reference mark formed in a first step; The second reference mark formed in the second step following the first step is formed by a concentric double square frame, and the first reference mark is obtained by an imaging device provided in the optical microscope of the alignment measuring machine. and the midpoint of the width of the signal waveform at a portion where the signal waveform indicating a change in contrast of the image data including the second reference mark intersects with a predetermined threshold is set as a detection position, and the detection position is set in the second step. It is used as a reference for layer positioning in the third step following .

In a first aspect of the present disclosure, the first reference mark and the second reference mark are formed by concentric double square frames, and the contrast of image data including the first reference mark and the second reference mark is changed. By using the midpoint of the width of the signal waveform at the intersection of the signal waveform indicating the intersection with the predetermined threshold value as the reference for positioning the layer related to the third step, the position of the layer in the subsequent process relative to the layer related to the previous process can be determined. Misalignment can be suppressed.

7 is a flowchart showing a processing flow from a first step, which is element isolation processing, to a second step, which is gate processing, and a third step, which is contact hole processing. FIG. 2 is a schematic diagram showing a state in which a gate pattern is formed in a second step after an element isolation pattern is formed in a first step on a semiconductor substrate; FIG. 6 is a schematic diagram showing a case where a contact hole pattern is formed in a third step after a gate pattern is formed in a second step on an element isolation pattern. FIG. 7 is an explanatory diagram showing, as an example, a reference mark for measuring misalignment used in the third step. FIG. 3 is an explanatory diagram showing an example of a signal waveform converted from an optical image recognized in a mark detection area. It is an explanatory view when the reference mark of the 2nd process shifts in the X direction with respect to the reference mark of the 1st process. FIG. 2 is a schematic diagram showing a state in which a gate pattern is formed in a second step after an element isolation pattern is formed in a first step on a semiconductor substrate; FIG. 6 is a schematic diagram showing a case where a contact hole pattern is formed in a third step after a gate pattern is formed in a second step on an element isolation pattern. FIG. 2 is an explanatory diagram of registration mark alignment that has been conventionally performed. It is a schematic diagram showing an example of misalignment of the second process with respect to the first process. It is a schematic diagram showing an example of misalignment of a third process with respect to a first process. FIG. 7B is a schematic diagram showing an example of misalignment in the third process relative to the second process when misalignment occurs in FIGS. 7A and 7B. FIG. 2 is a schematic diagram showing a state in which a gate pattern is formed in a second step after an element isolation pattern is formed in a first step on a semiconductor substrate; FIG. 6 is a schematic diagram showing a case where a contact hole pattern is formed in a third step after a gate pattern is formed in a second step on an element isolation pattern.

The technique according to the present exemplary embodiment relates to measuring the overlapping position of a plurality of layers in a photolithography process for manufacturing a semiconductor device. FIG. 1 is a flowchart showing a processing flow from the first step, which is element isolation processing, to the second step, which is gate processing, and the third step, which is contact hole processing. In step S100, a first step of element isolation processing and formation is performed, and element isolation patterns 12 are formed on the semiconductor substrate 10, as shown in FIG. 2A.

In step S102, the gate pattern 14 is formed as shown in FIG. 2A in a second process.

In step S104, a contact hole pattern 16 is formed as shown in FIG. 2B in a third process.

When performing the process shown in FIG. 1, it is necessary to accurately overlap the resist pattern with the processing pattern formed in the previous process.

FIG. 3A is an explanatory diagram showing, as an example, reference marks 22 and 24 for measuring misalignment used in the third step. The reference mark 22 is processed and formed in the first step, and the reference mark 24 is formed in the second step.

In this exemplary embodiment, the reference mark 22, which is a square frame processed and formed in the first step, and the reference mark 24, which is a square frame formed in the second step, are formed doubly at an arbitrary mark interval d21. Then, the mark detection areas 28A, 28B, 28C, and 28D are set to be sandwiched and surrounded by the reference marks 22 and 24. The resist pattern 26 in the third step is set as a square frame that is concentric with the reference marks 22 and 24 forming a double square frame and smaller than the reference marks 22 and 24.

If the width of the reference mark 22 in the first step is w1, and the width of the reference mark 24 in the second step is w2, the detection positions XoRi, XoLe, YoUp, respectively recognized in the mark detection areas 28A, 28B, 28C, 28D, The YoLo reference position obtained by averaging the reference mark 22 and the reference mark 24 is expressed by the following equations (1) to (4). In this exemplary embodiment, the square frame defined by each of the detection positions XoRi, XoLe, YoUp, and YoLo is referred to as a "reference frame for positioning the resist pattern 26 in the third step" (hereinafter referred to as "reference frame"). (abbreviated as ).
XoRi = (w1+w2+d21)/2...(1)
XoLe = (w1+w2+d21)/2...(2)
YoUp = (w1+w2+d21)/2...(3)
YoLo = (w1+w2+d21)/2...(4)

FIG. 3B is an explanatory diagram showing an example of the signal waveform S converted from the optical image recognized in the mark detection area 28A. In this exemplary embodiment, visible light is used as a light source, and the contrast of image data acquired by an imaging device included in an optical microscope of a combined measuring instrument is detected, and changes in the contrast of the image data are detected as shown in FIG. 3B. It is recognized as a signal waveform S.

In this exemplary embodiment, by setting the mark interval d21 as follows, distortion of the signal waveform due to the double square frame is avoided, and one vertex is almost the same as in the conventional case as shown in FIG. A signal waveform S having the following values is obtained, thereby obtaining good alignment measurement accuracy. As a result, it becomes possible to set the midpoint of the width of the signal waveform S at the portion that intersects the predetermined threshold Th as the detection position XoRi. Further, in the present exemplary embodiment, the mark interval d21 is set as below, and each of the predetermined threshold Th, the width w1 of the reference mark 22, and the width w2 of the reference mark 24 in the second step is measured together. It is determined based on the wavelength of the light source of the machine and the separation resolution of the optical microscope of the combined measuring machine at that wavelength. In other words, a state in which a signal waveform S having one vertex is obtained when the contrast of image data including the reference mark 22 and the reference mark 24 is detected, and the signal waveform S intersects with the predetermined threshold Th. It is sufficient to determine each of the mark interval d21, the predetermined threshold Th, the width w1 of the reference mark 22, and the width w2 of the reference mark 24 in the second step so that
Maximum amount of actual misalignment << d21 < Separation resolution of optical microscope of alignment measuring machine

FIG. 4 is an explanatory diagram when the reference mark 28 of the second step (formed during the second step photolithography) is shifted by ΔX in the X direction with respect to the reference mark 24 of the second step. Assuming that the misalignment of the reference mark 28 in the X direction in FIG. . XoRi' is a detection position affected by the misalignment amount ΔX in the mark detection area 28A, and XoLe' is a detection position affected by the misalignment amount ΔX in the mark detection area 28B.
XoRi' = (w1+w2+d21-ΔX)/2...(5)
XoLe' = (w1+w2+d21+ΔX)/2...(6)

The difference between the above equation (1) and equation (5) and the difference between the above equation (2) and equation (6) become the following equation (7) and equation (8), respectively.
|XoRi'−XoRi| =ΔX/2...(7)
|XoLe'−XoLe| =ΔX/2…(8)

Assuming that the position of the reference frame when there is no misalignment is Xo, the new position Xo' of the reference frame in consideration of the amount of misalignment ΔX is expressed by the following equation (9).
Xo' = Xo + ΔX/2...(9)

As shown in equation (9), if the reference mark 28 in the second step is shifted by ΔX in the X direction with respect to the reference mark 24, the reference frame when there is no misalignment is moved by ΔX/2 in the X direction. The new reference frame position becomes the new reference frame position.

Similarly, if the reference mark 28 in the second step is shifted by ΔX in the Y direction with respect to the reference mark 24, the reference frame is moved by ΔY/2 in the Y direction when there is no misalignment. This is the position of the reference frame. Then, a square frame obtained by moving the reference frame when there is no misalignment by ΔX/2 in the X direction or ΔY/2 in the Y direction becomes a new reference frame.

The above ΔX/2 and ΔY/2 are examples of how much the reference frame shifts. In this exemplary embodiment, since the detection position itself based on the signal waveform S detected by the alignment measuring machine includes the elements of ΔX/2 and ΔY/2, the average position with respect to the relative deviation of the two underlying layers is can be recognized as the reference position "automatically and easily".

In this exemplary embodiment, it is not necessary to consciously calculate ΔX/2 and ΔY/, but ΔX/2 and ΔY/2 are treated as correction amounts for positioning the resist pattern 26 in the third step. You can also do that. For example, the position of the resist pattern 26 in the third step relative to the reference mark 22 can be moved by ΔX/2 in the X direction and by ΔY/2 in the Y direction, thereby making it appropriate.

FIG. 5A is a schematic diagram showing a state in which the gate pattern 14 is formed in the second step after the element isolation pattern 12 is formed in the first step on the semiconductor substrate 10. In FIG. 5A, the gate pattern 14 formed on the element isolation pattern 12 has a misalignment amount ΔX in the second process with respect to the first process.

FIG. 5B is a schematic diagram showing a case where the contact hole pattern 16 is formed in the third step after the gate pattern 14 is formed in the second step on the element isolation pattern 12. In this exemplary embodiment, as shown in equation (9), in order to align the third process using a position shifted by 1/2 of the misalignment amount ΔX between the first process and the second process as a reference mark, The amount of misalignment of the contact hole pattern 16 formed in three steps is suppressed to ΔX/2. As a result, defects due to contact between the gate pattern 14 and the contact hole pattern 16 can be avoided. Furthermore, according to the present exemplary embodiment, a reference position including an appropriate amount of misalignment can be determined with only one measurement, so that it is possible to measure the amount of misalignment multiple times, unlike conventional methods. Alternatively, complicated calculations of misalignment correction amounts, etc. are no longer necessary, and it becomes possible to proceed with the manufacturing process of the semiconductor device simply and quickly.

As explained above, according to the exemplary embodiment, the reference marks of the first layer and the reference marks of the second layer, which serve as references, form a double frame arranged at an arbitrary interval. The detection area of the mark, which serves as a reference for positioning the third layer in the subsequent process, is set so as to be sandwiched and surrounded by the reference mark of the first layer and the reference mark of the second layer. As a result, the reference position of the third layer is detected as a reference position that includes the amount of misalignment between the first layer and the second layer. In addition, it is possible to obtain alignment accuracy such that the positional relationship between the second layer and the third layer has an optimal amount of alignment deviation.

The disclosure of Japanese Patent Application No. 2022-053394 filed on March 29, 2022 is incorporated herein by reference in its entirety.

All documents, patent applications, and technical standards mentioned herein are incorporated by reference to the same extent as if each individual document, patent application, and technical standard was specifically and individually indicated to be incorporated by reference. Incorporated herein by reference.

Regarding the above exemplary embodiments, the following additional notes are further disclosed.
[Additional note 1]
In measuring the overlapping position of multiple layers in the photolithography process of semiconductor device manufacturing,
A first reference mark formed in a first step and a second reference mark formed in a second step subsequent to the first step are formed by concentric double square frames,
The signal at a portion where a predetermined threshold intersects a signal waveform indicating a change in contrast of image data including the first reference mark and the second reference mark acquired by an imaging device included in an optical microscope of the alignment measuring machine. The detection position is the midpoint of the waveform width,
A method of manufacturing a semiconductor device in which the detected position is used as a reference for layer positioning in a third step subsequent to the second step.
[Additional note 2]
The semiconductor device according to supplementary note 1, wherein the distance between the first reference mark and the second reference mark is set to be sufficiently larger than the actual maximum amount of misalignment and smaller than the separation resolution of an optical microscope of the alignment measuring device. manufacturing method.
[Additional note 3]
Each of the width of the first reference mark, the width of the second reference mark, and the predetermined threshold value is set to the wavelength of the light source of the alignment measuring machine and the separation resolution of the optical microscope of the alignment measuring machine at the wavelength. The method for manufacturing a semiconductor device according to Supplementary Note 2, which is determined based on the method.
[Additional note 4]
If there is a misalignment of the actual position of the second reference mark with respect to the original position of the second reference mark, the reference for positioning the layer related to the third step is the position of the second reference mark. Supplementary Note 1: The reference for layer positioning in the third step when no misalignment occurs is a position that is moved by 1/2 of the amount of misalignment in the direction in which the position of the second reference mark is misaligned. The method for manufacturing a semiconductor device according to any one of Supplementary Items 3 to 3.
[Additional note 5]
When misalignment of the second reference mark occurs, the position of the layer related to the third step with respect to the first reference mark is changed by the amount of misalignment in the direction in which the second reference mark is misaligned. The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the semiconductor device is moved by 1/2.
[Additional note 6]
1/2 of the amount of misalignment is the difference between the detected position in the signal waveform when misalignment of the second reference mark occurs and the detected position when misalignment of the second reference mark does not occur. The method for manufacturing a semiconductor device according to Supplementary Note 4 or 5, which is a difference between the signal waveform and the detected position.

Claims

In measuring the overlapping position of multiple layers in the photolithography process of semiconductor device manufacturing,
A first reference mark formed in a first step and a second reference mark formed in a second step subsequent to the first step are formed by concentric double square frames,
The signal at a portion where a predetermined threshold intersects a signal waveform indicating a change in contrast of image data including the first reference mark and the second reference mark acquired by an imaging device included in an optical microscope of the alignment measuring machine. The detection position is the midpoint of the waveform width,
A method of manufacturing a semiconductor device in which the detected position is used as a reference for layer positioning in a third step subsequent to the second step.
The semiconductor device according to claim 1, wherein the distance between the first reference mark and the second reference mark is set to be sufficiently larger than the actual maximum amount of misalignment and smaller than the separation resolution of an optical microscope of the alignment measuring device. manufacturing method.
Each of the width of the first reference mark, the width of the second reference mark, and the predetermined threshold value is set to the wavelength of the light source of the alignment measuring machine and the separation resolution of the optical microscope of the alignment measuring machine at the wavelength. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the method is determined based on the method.
If there is a misalignment of the actual position of the second reference mark with respect to the original position of the second reference mark, the reference for positioning the layer related to the third step is the position of the second reference mark. Claim 1: A reference for layer positioning in the third step when no misalignment occurs is a position that is shifted by half the amount of misalignment in the direction in which the position of the second reference mark is misaligned. A method for manufacturing a semiconductor device according to .
When misalignment of the second reference mark occurs, the position of the layer related to the third step with respect to the first reference mark is changed by the amount of misalignment in the direction in which the second reference mark is misaligned. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is moved by 1/2.
1/2 of the amount of misalignment is the difference between the detected position in the signal waveform when misalignment of the second reference mark occurs and the detected position when misalignment of the second reference mark does not occur. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the difference is a difference between the signal waveform and the detected position.
1/2 of the amount of misalignment is the difference between the detected position in the signal waveform when misalignment of the second reference mark occurs and the detected position when misalignment of the second reference mark does not occur. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the difference is a difference between the signal waveform and the detected position.