WO2023130582A1

WO2023130582A1 - Data extraction circuit

Info

Publication number: WO2023130582A1
Application number: PCT/CN2022/081821
Authority: WO
Inventors: 李思曼
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-07
Filing date: 2022-03-18
Publication date: 2023-07-13
Also published as: CN116453557A

Abstract

Provided in the present disclosure is a data extraction circuit. The data extraction circuit comprises: a first input circuit, wherein an input end of the first input circuit establishes first input data under the triggering of a first data clock signal and establishes second input data under the triggering of a second data clock signal, and the first input circuit is used for latching the first input data and the second input data under the triggering of a latch clock signal; a second input circuit, wherein an input end of the second input circuit establishes first identification data under the triggering of the first data clock signal and establishes second identification data under the triggering of the second data clock signal, and the second input circuit is used for latching the first identification data and the second identification data under the triggering of the latch clock signal; and an output circuit, which is provided with a first output end and a second output end, wherein the output circuit is connected to the first input circuit and further connected to the second input circuit, and is used for outputting the first input data at the first output end and synchronously outputting the second input data at the second output end under the control of the first identification data and the second identification data, so as to distinguish between data in two cycles.

Description

data extraction circuit

This disclosure claims the priority of the Chinese patent application with application number 202210017756.1 and application title "Data Extraction Circuit" filed with China Patent Office on January 07, 2022, the entire contents of which are incorporated by reference in this disclosure.

technical field

The present disclosure relates to but is not limited to a data extraction circuit.

Background technique

At present, DRAM (Dynamic Random Access Memory) technology is developing rapidly, and the main applications are synchronous dynamic random access memory (SDRAM), the second generation of double data rate (DDR2) SDRAM, the third generation of double data Speed (DDR3) SDRAM, 4th generation double data rate (DDR4) SDRAM and 5th generation double data rate (DDR5) SDRAM and other types.

However, there is a problem that the data processing speed cannot match the data transmission speed of the processor, so that the DRAM cannot accurately distinguish the transmitted data from the high-speed transmitted data.

Contents of the invention

An embodiment of the present disclosure provides a data extraction circuit, including:

The first input circuit, whose input end establishes the first input data under the trigger of the first data clock signal, and whose input end also establishes the second input data under the trigger of the second data clock signal, is used for latching the clock signal Latching the first input data and the second input data under the trigger of ;

The second input circuit, its input terminal establishes the first identification data under the trigger of the first data clock signal, and its input terminal also establishes the second identification data under the trigger of the second data clock signal, which is used for latching the clock signal Latching the first identification data and the second identification data under a trigger;

An output circuit, which is provided with a first output terminal and a second output terminal, is connected to the first input circuit, and is also connected to the second input circuit, and is used to, under the control of the first identification data and the second identification data, An output end outputs first input data, and a second output end synchronously outputs second input data.

In the data extraction circuit provided by the present disclosure, the first input circuit latches the first input data and the second input data received within two clock cycles, and the second input circuit latches the first identification data received within two clock cycles The data and the second identification data are latched, so that the output circuit outputs the first input data through its first output terminal and outputs the second input data through its second output terminal under the control of the first identification data and the second identification data. data to enable extraction of input data received within two clock cycles.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic structural diagram of a data acquisition circuit provided by an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a data acquisition circuit provided by another embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a data acquisition circuit provided by another embodiment of the present disclosure;

4A and 4B are the relationship between the data clock signal and the latch clock signal provided by the present disclosure;

FIG. 5 is a schematic structural diagram of a data acquisition circuit provided by yet another embodiment of the present disclosure;

6A and 6B are schematic diagrams of data timing of a data acquisition circuit provided by yet another embodiment of the present disclosure.

By means of the above-mentioned drawings, certain embodiments of the present disclosure have been shown and will be described in more detail hereinafter. These drawings and written description are not intended to limit the scope of the disclosed concept in any way, but to illustrate the disclosed concept for those skilled in the art by referring to specific embodiments.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present disclosure as recited in the appended claims.

For high-speed input signals, the data receiving and processing end with a slow internal processing speed will receive the buffer first, and then perform data processing according to the internal processing clock. However, for high-speed data sent continuously in multiple batches, the order of receiving data cannot be judged according to the internal clock. , leading to data processing errors.

According to the JEDEC SPEC of DDR4, the input pins of DDR4 include command data (Command) pins and address data (Address) pins. The CPU sends command data and address data (CMD/ADD) based on one clock cycle.

That is, in DDR4, as shown in FIG. 1 , the data acquisition circuit includes a data receiver 201 , a data buffer 202 , a flip-flop 203 and an instruction decoder 204 , and the data acquisition circuit also includes a clock receiver 205 and a clock buffer 206 . Wherein, the output end of the data receiver 201 is connected to the input end of the data buffer 202 , and the output end of the data buffer 202 is connected to the data input end of the flip-flop 203 . The clock receiver 205 is connected to the clock terminal of the flip-flop 203 through a clock buffer 206 . The CPU sends command data and address data in one clock cycle, the data receiver 201 receives the command data and address data, the buffer 202 buffers the command data and address data, and the flip-flop 203 controls the input terminal under the control of the clock signal. The command data and address data are sampled, and the sampled data is output to the command decoder 204. The data processed by the command decoder 204 is within the same clock cycle, and there is no interference of processing data of multiple cycles at the same time.

But as far as DDR5 is concerned, for an activate command, the CPU sends command data and address data (CMD/ADD) based on two clock cycles, and when the identification data (CS) is low (L), it indicates that the CPU The first data clock (CK) information in the sent operation instruction (Operation) contains instruction data, such as: Command and BA/BG information, when the identification data (CS) is high level (H), it indicates the CPU sent The second data clock (CK) in the operation command (Operation) contains address data, such as: row address (Row Address) data and column address (Column Address) data. The instruction data and address data are transmitted to the instruction decoder by the input and output interface, and for the instruction decoder, it needs to process the instruction data and address data received by an activate instruction, but does not receive the identification data data processing signal, As a result, the received instruction data and address data cannot be effectively distinguished, which will cause decoding errors.

In DDR5, it is particularly important to design the data extraction circuit to distinguish the information of the two clocks in the CPU sending operation instructions. Moreover, due to the high input speed of the interface in DDR5, the data clock (CK) needs to be converted due to the limitations brought about by the process and design to be suitable for the internal data processing speed of DDR5. Due to the internal processing clock circuit of the instruction decoder and the interface Different data transmission clocks make it impossible to distinguish the information received in one interface data transmission cycle according to the internal processing clock frequency, which also increases the difficulty of data extraction circuit design to a certain extent.

As shown in FIG. 2 , an embodiment of the present disclosure provides a data extraction circuit. The data extraction circuit includes a first input circuit 110 , a second input circuit 120 and an output circuit 130 .

The data to be extracted includes first input data C0 and second input data C1. The first input data C0 and the second input data C1 are received through a plurality of data pins of the chip, and the data to be extracted is sent through two clock signal cycles, marked as the first data clock signal CK0 and the second data clock signal CK1 . The first data clock signal CK0 and the second data clock signal CK1 have the same clock period, and the phase of the first data clock signal CK0 is earlier than that of the second data clock signal CK1 by 360°.

The first identification data S1 is used to identify the type of the first input data C0, and the second identification data S2 is used to identify the type of the second input data C1. For example: the first identification data S1 indicates that the first input data C0 is command data, and the second identification data S2 indicates that the second input data C1 is address data.

Wherein, the first input circuit 110 is provided with an input terminal, the first input data C0 is established at the input terminal of the first input circuit 110 under the trigger of the first data clock signal CK0, and the first input data C0 is established at the input terminal of the first input circuit 110 under the trigger of the second data clock signal CK1. An input terminal of an input circuit 110 establishes second input data C1. That is, the input terminal of the first input circuit 110 receives the first input data C0 and the second input data C1 within two data clock cycles.

After establishing the first input data C0 and the second input data C1 at the input end of the first input circuit 110, the first input circuit 110 is also used to latch the first input data C0 and the second input data under the trigger of the latch clock signal Data C1.

The second input circuit 120 is also provided with an input terminal, the first identification data S1 is established at the input terminal of the second input circuit 120 under the trigger of the first data clock signal CK0, and the first identification data S1 is established at the input terminal of the second input circuit 120 under the trigger of the second data clock signal CK1. The input of the input circuit 120 creates second identification data S2. That is, the input terminal of the second input circuit 120 receives the first identification data S1 and the second identification data S2 based on two data clock cycles.

After the first identification data S1 and the second identification data S2 are established at the input end of the second input circuit 120, the second input circuit 120 is also used to latch the first identification data S1 and the second identification data under the trigger of the latch clock signal Data S2.

The output circuit 130 is provided with an input terminal, and the output circuit 130 is also provided with two output terminals, which are sequentially marked as a first output terminal CA1st and a second output terminal CA2nd. The input end of the output circuit 130 is connected to the output end of the first input circuit 110 , and the input end of the output circuit 130 is also connected to the output end of the second input circuit 120 .

The output circuit 130 is used for outputting the first input data C0 at the first output terminal CA1st and synchronously outputting the second input data C1 at the second output terminal CA2nd under the control of the first identification data S1 and the second identification data S2.

Among them, the first data clock signal CK0 and the second data clock signal CK1 are used to control the moment when the first input data C0 and the second input data C1 are established at the input end of the first input circuit 110, and are also used to control the The input of the circuit 120 establishes the time instants of the first identification data S1 and the second identification data S2.

The latch clock signal is used to control the moment when the output terminal of the first input circuit 110 outputs the first input data C0 and the second input data C1, and because the first input data C0 and the second input data C1 are in the first input circuit 110 The setup times of the input terminals are different, and the output terminal of the first input circuit 110 may output the first input data C0 and the second input data C1 with different time sequences.

The latch clock signal is also used to control the moment when the output terminal of the second input circuit 120 outputs the first identification data S1 and the second identification data S2, and because the first identification data S1 and the second identification data S2 are in the second input circuit 120 The setup time of the input terminals of the second input circuit 120 is different, and the first identification data S1 and the second identification data S2 of different timings can be output at the output terminals of the second input circuit 120 .

By setting the timing relationship between the latch clock signal and the first data clock signal CK0 and the second data clock signal CK1, adjust the first input data C0, the second input data C1, the first identification data S1 and the second identification data S2 In order to realize that in the output circuit 130, the first input data C0 is controlled by the first identification data S1 and the second identification data S2 to output via the first output terminal CA1st of the output circuit 130, and the second input data C1 is output via The second output terminal CA2nd of the circuit 130 outputs.

In the above technical solution, the first input circuit 110 latches the first input data C0 and the second input data C1 received within two clock cycles, and the second input circuit 120 latches the first input data C0 received within two clock cycles The first identification data S1 and the second identification data S2 are latched, so that the output circuit 130 outputs the first input data C0 through its first output terminal CA1st under the control of the first identification data S1 and the second identification data S2, and through Its second output terminal CA2nd outputs the second input data C1, so as to distinguish the received input data within two clock cycles.

In one embodiment, referring to FIG. 3 , the data extraction circuit further includes a clock circuit 140, the clock circuit 140 is connected to the clock terminal of the first input circuit 110, and the clock circuit 140 is also connected to the clock terminal of the second input circuit 120 for The first latch clock signal CKT and the second latch clock signal CKTB are generated according to the first data clock signal CK0.

Wherein, the clock periods of the first latch clock signal CKT and the second latch clock signal CKTB are the same, the phase difference between the first latch clock signal CKT and the second latch clock signal CKTB is 180°, and the first latch The signal period of the storage clock signal CKT is twice the signal period of the first data clock signal CK0.

In the above technical solution, the period of the two latch clock signals output by the output end of the clock circuit is twice that of the data clock signal, which can extend the clock period inside the data extraction circuit to reduce the data processing rate inside the data extraction circuit, Improve the accuracy of data processing and meet the requirements of subsequent data processing.

In one embodiment, referring to FIG. 3 , the first input circuit 110 includes a first latch circuit 111 and a second latch circuit 112 . The first latch circuit 111 is provided with one input terminal and two output terminals, which are marked as a first output terminal CA1 and a second output terminal CA2 in sequence. Two output terminals of the first latch circuit 111 are connected to input terminals of the output circuit 130 . The input terminal of the first latch circuit 111 is used to create the first input data C0 triggered by the first data clock signal CK0 and create the second input data C1 triggered by the second data clock signal CK1 .

The second latch circuit 112 is similar to the first latch circuit 111 . An input terminal and two output terminals are also provided, denoted in turn as a first output terminal CA3 and a second output terminal CA4. Two output terminals of the second latch circuit 112 are connected to input terminals of the output circuit 130 . The input terminal of the second latch circuit 112 is used for establishing the first input data C0 triggered by the first data clock signal CK0 and establishing the second input data C1 triggered by the second data clock signal CK1 .

The second input circuit 120 includes a third latch circuit 121 and a fourth latch circuit 122 . The third latch circuit 121 has an input terminal and an output terminal CS1. The output terminal CS1 of the third latch circuit 121 is connected to the control terminal of the output circuit 130 . The input terminal of the third latch circuit 121 is used for establishing the first identification data S1 under the trigger of the first data clock signal CK0 , and establishing the second identification data S2 under the trigger of the second data clock signal CK1 .

The fourth latch circuit 122 also has an input terminal and an output terminal CS2. The output terminal CS2 of the fourth latch circuit 122 is connected to the control terminal of the output circuit 130 . The input end of the fourth latch circuit 122 is used for establishing the first identification data S1 under the trigger of the first data clock signal CK0 and establishing the second identification data S2 under the trigger of the second data clock signal CK1 .

The first latch circuit 111 and the second latch circuit 112 are configured to output corresponding input data triggered by the first latch clock signal CKT and the second latch clock signal CKTB. The third latch circuit 121 and the fourth latch circuit 122 are configured to output corresponding identification data triggered by the first latch clock signal CKT and the second latch clock signal CKTB.

When the phase relationship between the two latch clock signals and the two data clock signals is different, the data output by the two output terminals of the first latch circuit 111 and the data output by the two output terminals of the second latch circuit 112 data will also change. The data output by the output terminal of the third latch circuit 121 and the data output by the output terminal of the fourth latch circuit 122 also change.

When designing the latch sequence of the four latch circuits, the data output by the first latch circuit 111 corresponds to the data output by the third latch circuit 121, and the data output by the second latch circuit 112 corresponds to the output data of the fourth latch circuit. 122 output data corresponding. That is, when the first latch circuit 111 outputs the first input data C0, the third latch circuit 121 outputs the first identification data S1. When the second latch circuit 112 outputs the second input data C1, the fourth latch circuit 122 outputs the second identification data S2. Such setting facilitates the design of the corresponding output circuit 130 to ensure that the first output terminal CA1st of the output circuit 130 outputs the first input data C0, and the second output terminal CA2nd outputs the second input data C1.

Referring to FIG. 4A, if the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the first data clock signal CK0, the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the time corresponding to the rising edge of the first latch clock signal. The falling edges of CKT correspond to the same time, and the first latch circuit 111 is used to sequentially establish the first output terminal CA1 and the second output terminal CA2 under the trigger of the first latch clock signal CKT and the second latch clock signal CKTB. - Input data C0. That is, the first input data C0 is first established at the first output terminal CA1 of the first latch circuit 111 , and then the first input data C0 is established at the second output terminal CA2 of the first latch circuit 111 . The second latch circuit 112 is used to sequentially create the second input data C1 at the first output terminal CA3 and the second output terminal CA4 under the trigger of the first latch clock signal CKT and the second latch clock signal CKTB. That is, the second input data C1 is first established at the first output terminal CA3 of the second latch circuit 112 , and then the second input data C1 is established at the second output terminal CA4 of the second latch circuit 112 .

Correspondingly, the third latch circuit 121 is triggered by the first latch clock signal CKT and the second latch clock signal CKTB to create the first identification data S1 at its output terminal CS1, and the fourth latch circuit 122 is used for Triggered by a latch clock signal CKT and a second latch clock signal CKTB, the second identification data S2 is established at its output terminal CS2.

Referring to FIG. 4B, if the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the time corresponding to the rising edge of the first data clock signal CK0, the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the second latch clock signal. The falling edges of CKTB correspond to the same time, and the first latch circuit 111 is used to sequentially establish the first output terminal CA1 and the second output terminal CA2 under the trigger of the first latch clock signal CKT and the second latch clock signal CKTB. Two input data C1. The second latch circuit 112 is used for sequentially establishing the first input data C0 at the first output terminal CA3 and the second output terminal CA4 under the trigger of the first latch clock signal CKT and the second latch clock signal CKTB.

Correspondingly, the third latch circuit 121 is triggered by the first latch clock signal CKT and the second latch clock signal CKTB to create the second identification data S2 at its output terminal CS1, and the fourth latch circuit 122 is used for Triggered by a latch clock signal CKT and a second latch clock signal CKTB, the first identification data S1 is established at its output terminal CS2.

In the above technical solution, the input data and input data timing output by the output terminals of the first latch circuit 111 and the second latch circuit 112 are controlled by two latch signals with a phase difference of 180° and the same period. The latch signal is also used to control the identification data output by the output terminals of the third latch circuit 121 and the fourth latch circuit 122, so that the output circuit 130 can be controlled to output the first input data via its first output terminal CA1st according to the identification data C0 outputs the second input data C1 through its second output terminal CA2nd. And the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the first data clock signal CK0, or the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the rising edge of the first data clock signal CK0 When the corresponding times of the edges are the same, the first output terminal CA1st can output the first input data, and the second output terminal CA2nd can output the second input data.

In an embodiment, referring to FIG. 3 , the output circuit 130 includes a first selection circuit 131 and a second selection circuit 132 . Wherein, the first selection circuit 131 is provided with two input terminals, two control terminals and one output terminal, and the output terminal is used as the first output terminal CA1st of the output circuit. The two input terminals are marked as the first input terminal and the second input terminal in sequence, and the two control terminals are marked as the first control terminal and the second control terminal in sequence.

The first input terminal of the first selection circuit 131 is connected to the second output terminal CA2 of the first latch circuit 111 , and the second input terminal of the first selection circuit 131 is connected to the second output terminal CA4 of the second latch circuit 112 . The first control terminal of the first selection circuit 131 is connected to the output terminal CS1 of the third latch circuit 121 , and the second control terminal of the first selection circuit 131 is connected to the output terminal CS2 of the fourth latch circuit 122 . The first selection circuit 131 is used to establish the first input data C0 at its output terminal under the control of the first identification data S1 and the second identification data S2.

With such setting, if the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the first data clock signal CK0, the first input terminal of the first selection circuit 131 receives the first input data C0, and the first The second input terminal of the selection circuit 131 receives the second input data C1. If the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the time corresponding to the rising edge of the first data clock signal CK0, the first input terminal of the first selection circuit 131 receives the second input data C1, and the first selection circuit 131 The second input terminal receives the first input data C0. That is, when the timing between the latch clock signal and the data clock signal is different, the first selection circuit 131 will receive both the first input data C0 and the second input data C1, and then based on the first identification data S1 and the second The identification data S2 selects the output of the first input data C0 from the first input data C0 and the second input data C1 to ensure that the first output terminal CA1st of the output circuit 130 is output at the same time when the timing between the latch clock signal and the data clock signal is different. The first input data C0 is output.

Wherein, the second selection circuit 132 is provided with two input terminals, two control terminals and one output terminal, and the output terminal is used as the second output terminal CA2nd of the output circuit. The two input terminals are marked as the first input terminal and the second input terminal in sequence, and the two control terminals are marked as the first control terminal and the second control terminal in sequence.

The first input terminal of the second selection circuit 132 is connected to the first output terminal CA3 of the second latch circuit 112 , and the second input terminal of the second selection circuit 132 is connected to the first output terminal CA1 of the first latch circuit 111 . The first control terminal of the second selection circuit 132 is connected with the output terminal CS1 of the third latch circuit 121, the second control terminal of the second selection circuit 132 is connected with the output terminal CS2 of the fourth latch circuit 122, and the second selection circuit 132 is used to create the second input data C1 at its output under the control of the first identification data S1 and the second identification data S2.

With such setting, if the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the first data clock signal CK0, the first input terminal of the second selection circuit 132 receives the second input data C1, and the second The second input terminal of the selection circuit 132 receives the first input data C0. If the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the time corresponding to the rising edge of the first data clock signal CK0, the first input end of the second selection circuit 132 receives the first input data C0, and the second selection circuit 132 The second input terminal receives second input data C1. That is, the second selection circuit 132 will receive the first input data C0 and the second input data C1, and then select the second input data C0 and the second input data C1 based on the first identification data S1 and the second identification data S2. The input data C1 is output to ensure that the second output terminal CA2nd of the output circuit 130 outputs the second input data C1 when the timings of the latch clock signal and the data clock signal are different.

In one embodiment, the first input circuit 110 further includes a first receiving circuit 113, the output terminal of the first receiving circuit 113 is connected to the input terminal of the first latch circuit 111, and the output terminal of the first receiving circuit 113 is also connected to the first receiving circuit 113. The input terminals of the second latch circuit 112 are connected, and the first receiving circuit 113 is used for amplifying the first input data C0 and the second input data C1 to realize signal enhancement of the two input data.

In one embodiment, the second input circuit 120 further includes a second receiving circuit 123, the output terminal of the second receiving circuit 123 is connected to the input terminal of the third latch circuit 121, and the output terminal of the second receiving circuit 123 is also connected to the first The input terminals of the four latch circuits 122 are connected to the second receiving circuit 123 for amplifying the first identification data S1 and the second identification data S2, so as to realize the signal enhancement of the two identification data.

In one embodiment, the clock circuit 140 includes a third receiving circuit 141 and a frequency dividing circuit 142, the input terminal of the frequency dividing circuit 142 is connected to the third receiving circuit 141, and the output terminal of the frequency dividing circuit 142 is connected to the first input circuit 110. connected to the clock terminal, and the output terminal of the frequency division circuit 142 is also connected to the clock terminal of the second input circuit 120 . The third receiving circuit 141 is used to receive the first data clock signal CK0, and the frequency division circuit 142 is used to perform frequency division processing on the first data clock signal CK0 to output the first latch clock signal CKT and the second latch clock signal CKTB , by performing frequency division processing on the data clock signal, the data processing speed inside the data extraction circuit can be reduced. The first data clock signal CK0 can be a single clock signal or a differential clock signal.

In one embodiment, the first input circuit 110 further includes a first buffer circuit 114, the input end of the first buffer circuit 114 is connected to the first receiving circuit 113, the output end of the first buffer circuit 114 is connected to the first latch circuit 111 The input end is connected, and the output end of the first buffer circuit 114 is also connected to the input end of the second latch circuit 112, and the first buffer circuit 114 is used for buffering the first input data C0 and the second input data C1 for signal amplification deal with.

The second input circuit 120 also includes a second buffer circuit 124, the input end of the second buffer circuit 124 is connected to the second receiving circuit 123, the output end of the second buffer circuit 124 is connected to the input end of the third latch circuit 121, and the second The output end of the buffer circuit 124 is also connected to the input end of the fourth latch circuit 122, and the second buffer circuit 124 is used for buffering the first identification data S1 and the second identification data S2 for signal amplification.

The clock circuit 140 also includes a third buffer circuit 143, the third buffer circuit 143 is connected to the output terminal of the frequency dividing circuit 142, and the third buffer circuit 143 is used for performing a process on the first latch clock signal CKT and the second latch clock signal CKTB Cache handling.

In the above technical solution, by setting the buffer circuit inside the first input circuit, the second input circuit and the clock circuit, data loss caused by the difference between the external clock and the internal clock of the data extraction circuit can be avoided, and the two input data, Synchronization of both identification data and latch clock signals.

In one embodiment, referring to FIG. 5 , the first latch circuit 111 includes a first flip-flop F1 and a second flip-flop F2. The input end of the first flip-flop F1 receives the first input data C0 and the second input data C1, the clock end of the first flip-flop F1 receives the first latch clock signal CKT, and the output end of the first flip-flop F1 is the first lock The first output terminal CA1 of the storage circuit 111.

The input end of the second flip-flop F2 is connected to the output end of the first flip-flop F1, the clock end of the second flip-flop F2 receives the second latch clock signal CKTB, and the output end of the second flip-flop F2 is the first latch circuit 111's second output terminal CA2.

Continuing to refer to FIG. 5, the second latch circuit 112 includes a third flip-flop F3 and a fourth flip-flop F4, the input terminal of the third flip-flop F3 receives the first input data C0 and the second input data C1, and the third flip-flop F3 The clock terminal of the third flip-flop F3 receives the second latch clock signal CKTB, and the output terminal of the third flip-flop F3 is the first output terminal CA3 of the second latch circuit 112 .

The input end of the fourth flip-flop F4 is connected to the output end of the third flip-flop F3, the clock end of the fourth flip-flop F4 is used to receive the first latch clock signal CKT, and the output end of the fourth flip-flop F4 is the second lock The second output terminal CA4 of the storage circuit 112.

Referring to FIG. 6A , if the rising edge of the first latch clock signal CKT is at the same time as the rising edge of the first data clock signal CK0 , the difference between the first latch clock signal CKT and the second latch clock signal CKTB is 180°.

Between time t0 and time t1, that is, at the rising edge of the first input clock cycle CK0 of the two input data clocks, the first input circuit 110 receives the first input data C0, that is, the first data clock cycle is at the first The input of the flip-flop F1 establishes the first input data C0.

At time t1, the rising edge of the first latch clock signal CKT arrives, and the output terminal of the first flip-flop F1 outputs the first input data C0, that is, the first input data is output at the first output terminal CA1 of the first latch circuit 111 C0, and establish the first input data C0 at the input terminal of the second flip-flop F2.

At time t2, the rising edge of the second latch clock signal CKTB arrives, and the second flip-flop F2 outputs the first input data C0 under the control of the second latch clock signal CKTB, that is, in the second latch circuit 111 The output terminal CA2 outputs the first input data C0, and the phase of the first input data C0 output by the second output terminal CA2 is 180° later than the phase of the first input data C0 output by the first output terminal CA1.

Between time t1 and time t2, at the rising edge of the second data clock cycle CK1 of the two input data clocks, the first input circuit 110 receives the second input data C1, that is, the input terminal of the third flip-flop F3 establishes The second input data C1.

At time t2, the rising edge of the second latch clock signal CKTB arrives, and the third flip-flop F3 outputs the second input data C1 under the control of the second latch clock signal CKTB. An output terminal CA3 outputs the second input data C1, and establishes the second input data C1 at the input terminal of the fourth flip-flop F4.

At time t3, the rising edge of the first latch clock signal CKT arrives again, and the fourth flip-flop F4 outputs the second input data C1 under the control of the first latch clock signal CKT, that is, in the second latch circuit 112 The second output terminal CA4 outputs the second input data C1, and the phase of the second input data C1 output by the second output terminal CA4 is 180° later than the phase of the second input data C1 output by the first output terminal CA3.

Continuing to refer to FIG. 6A, if the time corresponding to the rising edge of the first latch clock signal CKT is the same as the time corresponding to the rising edge of the first data clock signal CK0, the second output terminal CA2 of the first latch circuit 111 outputs the first input data C0 The moment t2 of the second latch circuit 112 is the same as the moment t2 when the second input data C1 is output from the first output terminal CA3 of the second latch circuit 112, that is, the moment when the first input data C0 is established at the first input terminal of the first selection circuit 131 is the same as The first input terminal of the second selection circuit 132 establishes the same moment of the second input data C1, so that under the control of the first identification data S1 and the second identification data S2, the data of the first input terminal of the first selection circuit 131 can be Output through its output end, let the data of the first input end of the second selection circuit 132 output through its output end, so as to realize outputting the first input data C0 at the output end of the first selection circuit 131, and outputting the first input data C0 at the output end of the second selection circuit 132 The terminal synchronously outputs the second input data C1.

Referring to FIG. 6B , if the rising edge of the second latch clock signal CKTB is at the same time as the rising edge of the first data clock signal CK0 , the difference between the first latch clock signal CKT and the second latch clock signal CKTB is 180°.

Between time t4 and time t5, that is, on the rising edge of the first input clock cycle CK0 of the two input data clocks, the first input circuit 110 receives the first input data C0, that is, at the input of the third flip-flop F3 The terminal creates the first input data C0.

At time t5, the rising edge of the second latch clock signal CKTB arrives, and the output terminal of the third flip-flop F3 outputs the first input data C0, that is, the first output terminal CA3 of the second latch circuit 112 outputs the first input data. Data C0, and establish the first input data C0 at the input terminal of the fourth flip-flop F4.

At time t6, the rising edge of the first latch clock signal CKT arrives, and the fourth flip-flop F4 outputs the first input data C0 under the control of the first latch clock signal CKT, that is, in the second latch circuit 112 The second output terminal CA4 outputs the first input data C0, and the phase of the second output terminal CA4 outputting the first input data C0 is 180° later than the phase of the first output terminal CA3 outputting the first input data C0.

Between time t5 and time t6, that is, on the rising edge of the second input clock cycle CK1 of the two input data clocks, the first input circuit 110 receives the second input data C1, which is the input terminal of the first flip-flop F1 The second input data C1 is created.

At time t6, the rising edge of the first latch clock signal CKT arrives, and the output terminal of the first flip-flop F1 outputs the second input data C1, that is, the first output terminal CA1 of the first latch circuit 111 outputs the second input data. Data C1, and establish the second input data C1 at the input terminal of the second flip-flop F2.

At time t7, the rising edge of the second latch clock signal CKTB arrives again, and the output terminal of the second flip-flop F2 outputs the second input data C1, that is, the second output terminal CA2 of the first latch circuit 111 outputs the second input data C1. The input data C1 is input, and the phase of the second input data C1 output from the second output terminal CA2 is 180° later than the phase of the second input data C1 output from the first output terminal CA1.

If the time corresponding to the rising edge of the second latch clock signal CKTB is the same as the time corresponding to the rising edge of the first data clock signal CK0, the time t6 and The moment t6 at which the first output terminal CA1 of the first latch circuit 111 outputs the second input data C1 is the same, and the moment at which the second input terminal of the first selection circuit 131 establishes the first input data C0 is the same as the second input terminal CA1 of the second selection circuit 132. The two input terminals create the second input data C1 at the same moment, so that under the control of the first identification data S1 and the second identification data S2, the data of the second input terminal of the first selection circuit 131 can be output through its output terminal, so that The data of the second input end of the second selection circuit 132 is output through its output end, so as to realize outputting the first input data C0 at the output end of the first selection circuit 131, and synchronously outputting the second input data at the output end of the second selection circuit 132 C1.

Continuing to refer to FIG. 5 , the third latch circuit 121 includes a fifth flip-flop F5 and a sixth flip-flop F6 . The input terminal of the fifth flip-flop F5 receives the first identification data S1 and the second identification data S2, and the clock terminal of the fifth flip-flop F5 receives the first latch clock signal CKT. The input end of the sixth flip-flop F6 is connected to the output end of the fifth flip-flop F5, the clock end of the sixth flip-flop F6 receives the second latch clock signal CKTB, and the output end of the sixth flip-flop F6 is the third latch circuit 121 output terminal CS1.

The fourth latch circuit 122 includes a seventh flip-flop F7 and an eighth flip-flop F8, the input end of the seventh flip-flop F7 receives the first identification data S1 and the second identification data S2, and the clock end of the seventh flip-flop F7 receives the first identification data S2. Two latch clock signals CKTB, and the input end of the eighth flip-flop F8 are connected with the output end of the seventh flip-flop F7, the clock end of the eighth flip-flop F8 receives the first latch clock signal CKT, the eighth flip-flop F8 The output terminal is the output terminal CS2 of the fourth latch circuit 122 .

Between time t0 and time t1, that is, on the rising edge of the first input clock cycle CK0 of the two input data clocks, the second input circuit 120 receives the first identification data S1, that is, at the input of the fifth flip-flop F5 The terminal establishes the first identification data S1.

At time t1, the rising edge of the first latch clock signal CKT arrives, the output terminal of the fifth flip-flop F5 outputs the first identification data S1, and the first identification data S1 is established at the input terminal of the sixth flip-flop F6. At time t2, the second latch clock signal CKTB arrives, and the sixth flip-flop F6 outputs the first identification data S1 under the control of the second latch clock signal CKTB, that is, the output terminal CS1 of the third latch circuit 121 outputs The first identification data S1.

Between time t1 and time t2, that is, the rising edge of the second input clock cycle CK1 of the two input data clocks, the second input circuit 120 receives the second identification data S2, and establishes at the input end of the seventh flip-flop F7 The second identification data S2.

At time t2, the rising edge of the second latch clock signal CKTB arrives, and the seventh flip-flop F7 outputs the second identification data S2 under the control of the second latch clock signal CKTB. At time t3, the rising edge of the first latch clock signal CKT arrives again, and the eighth flip-flop F8 outputs the second identification data S2 under the control of the first latch clock signal CKT, that is, in the fourth latch circuit 122 The output terminal CS2 outputs the second identification data S2.

Between time t4 and time t5, that is, on the rising edge of the first input clock cycle CK0 of the two input data clocks, the second input circuit 120 receives the first identification data S1, and the input terminal of the seventh flip-flop F7 establishes the first An identification data S1.

At time t5, the rising edge of the second latch clock signal CKTB arrives, and the output terminal of the seventh flip-flop F7 outputs the first identification data S1. At time t6, the rising edge of the first latch clock signal CKT arrives again, and the eighth flip-flop F8 outputs the first identification data S1 under the control of the first latch clock signal CKT, that is, in the fourth latch circuit 122 The output terminal CS2 outputs the first identification data S1.

Between time t5 and time t6, that is, on the rising edge of the second input clock cycle CK1 of the two input data clocks, the second input circuit 120 receives the second identification data S2, that is, the input terminal of the fifth flip-flop F5 is established The second identification data S2.

At time t6, the rising edge of the first latch clock signal CKT arrives, the output terminal of the fifth flip-flop F5 outputs the second identification data S2, and the second identification data S2 is established at the input terminal of the sixth flip-flop F6. At time t7, the rising edge of the second latch clock signal CKTB arrives again, and the output terminal of the sixth flip-flop F6 outputs the second identification data S2, that is, the output terminal CS1 of the third latch circuit 121 outputs the second identification data S2.

Continuing to refer to FIG. 5 , the first selection circuit 131 includes a first transmission gate G1 and a second transmission gate G2 . The input terminal of the first transmission gate G1 is the first input terminal of the first selection circuit 131 , and is used for connecting with the second output terminal CA2 of the first latch circuit 111 . The control terminal of the first transmission gate G1 is the first control terminal of the first selection circuit 131 , and the output terminal of the first transmission gate G1 is the output terminal of the first selection circuit 131 , serving as the first output terminal CA1st of the output circuit.

The input end of the second transmission gate G2 is the second input end of the first selection circuit 131 , and is used for connecting with the second output end CA4 of the second latch circuit 112 . The control terminal of the second transmission gate G2 is the second control terminal of the first selection circuit 131 , and the output terminal of the second transmission gate G2 is connected to the output terminal of the first transmission gate G1 .

The second selection circuit 132 includes a third transmission gate G3 and a fourth transmission gate G4. The input terminal of the third transmission gate G3 is the first input terminal of the second selection circuit 132 , and is used for connecting with the first output terminal CA3 of the second latch circuit 112 . The control terminal of the third transmission gate G3 is the first control terminal of the second selection circuit 132 , and the output terminal of the third transmission gate G3 is the output terminal of the second selection circuit 132 , serving as the second output terminal CA2nd of the output circuit.

The input terminal of the fourth transmission gate G4 is the second input terminal of the second selection circuit 132 , and is used for connecting with the first output terminal CA1 of the first latch circuit 111 . The control terminal of the fourth transmission gate G4 is the second control terminal of the second selection circuit 132 , and the output terminal of the fourth transmission gate G4 is connected to the output terminal of the first transmission gate G1 .

Continuing to refer to FIG. 6A, the first identification data S1 is used to control the control terminal of the first transmission gate G1 and the control terminal of the third transmission gate G3, and the second identification data S2 is used to control the control terminal of the second transmission gate G2 and the control terminal of the fourth transmission gate G2. The control terminal of the transmission gate G4, and outputs the first identification data S1 at the time t2, the first identification data S1 is low level, the first transmission gate G1 and the third transmission gate G3 are turned on, and the first transmission gate G1 outputs at the time t2 The first input data C0, the third transmission gate G3 outputs the second input data C1 at t2.

Continuing to refer to FIG. 6B, the second identification data S2 is used to control the control terminal of the first transmission gate G1 and the control terminal of the third transmission gate G3, and the first identification data S1 is used to control the control terminal of the second transmission gate G2 and the control terminal of the fourth transmission gate G2. The control terminal of the transmission gate G4, and outputs the first identification data S1 at time t6, the first identification data S1 is low level, the second transmission gate G2 and the fourth transmission gate G4 are turned on, and the second transmission gate G2 outputs at time t6 The first input data C0, the fourth transmission gate G4 outputs the second input data C1 at t6.

In the first input circuit 110, by setting the structure of the first latch circuit and the structure of the second latch circuit to be symmetrical to each other, the first input circuit can output the first input data of two timings and the second input data of two timings. Two input data, and the first selection circuit is connected to the two latch circuits, so as to ensure that the first selection circuit can still receive the first input data when the timing of the latch clock signal and the data clock signal are different, thereby ensuring the first The selection circuit can output the first input data under the control of the first identification data and the second identification data. The same principle ensures that the second selection circuit can output the second input data. By fixing the transmission channel of the first input data and the second input data, the instruction decoder of the latter stage can accurately distinguish the first input data and the second input data according to the fixed data transmission channel, regardless of the data input frequency and internal data processing frequency impact.

Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present disclosure is intended to cover any modification, use or adaptation of the present disclosure. These modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. . The specification and examples are to be considered exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It should be understood that the present disclosure is not limited to the precise constructions which have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

A data extraction circuit, comprising:

The first input circuit (110), its input end establishes the first input data under the trigger of the first data clock signal, and its input end also establishes the second input data under the trigger of the second data clock signal, which is used for locking Latching the first input data and the second input data triggered by a clock signal;

The second input circuit (120), whose input terminal establishes first identification data under the trigger of the first data clock signal, and whose input terminal also establishes second identification data under the trigger of the second data clock signal, is used Latching the first identification data and the second identification data under the trigger of the latch clock signal;

an output circuit (130), which is provided with a first output terminal and a second output terminal, which is connected to the first input circuit (110) and also connected to the second input circuit (120), for use in the Under the control of the first identification data and the second identification data, the first input data is output at the first output terminal, and the second input data is synchronously output at the second output terminal.
The data extraction circuit according to claim 1, wherein the first data clock signal and the second data clock signal have the same clock period, and the phase of the first data clock signal is larger than that of the second data clock The phase of the signal is 360° earlier;

The latched clock signal includes a first latched clock signal and a second latched clock signal having the same clock cycle; a phase difference between the phase of the first latched clock signal and the phase of the second latched clock signal 180°.
The data extraction circuit according to claim 2, wherein the first input circuit (110) comprises:

The first latch circuit (111), which is provided with a first output terminal and a second output terminal, is used to sequentially output the first latch circuit under the trigger of the first latch clock signal and the second latch clock signal terminal and said second output terminal to establish said first input data;

The second latch circuit (112), which is provided with a first output terminal and a second output terminal, is used for sequentially switching on the first output under the trigger of the first latch clock signal and the second latch clock signal terminal and the second output terminal to establish the second input data;

Wherein, the time corresponding to the rising edge of the first latch clock signal is the same as the time corresponding to the rising edge of the first data clock signal.
The data extraction circuit according to claim 2, wherein the first input circuit (110) comprises:

The first latch circuit (111), which is provided with a first output terminal and a second output terminal, is used to sequentially output the first latch circuit under the trigger of the first latch clock signal and the second latch clock signal terminal and the second output terminal to establish the second input data;

The second latch circuit (112), which is provided with a first output terminal and a second output terminal, is used for sequentially switching on the first output under the trigger of the first latch clock signal and the second latch clock signal terminal and said second output terminal to establish said first input data;

Wherein, the time corresponding to the rising edge of the second latch clock signal is the same as the time corresponding to the rising edge of the first data clock signal.
The data extraction circuit according to claim 3 or 4, wherein;

The first latch circuit (111) includes:

A first flip-flop (F1), whose input terminal receives the first input data and the second input data, whose clock terminal receives the first latch clock signal, and whose output terminal is the first latch circuit a first output terminal of (111);

The second flip-flop (F2), its input end is connected with the output end of the first flip-flop (F1), its clock end receives the second latch clock signal, and its output end is the first latch circuit (111) second output terminal;

The second latch circuit (112) includes:

A third flip-flop (F3), whose input terminal receives the first input data and the second input data, whose clock terminal receives the second latch clock signal, and whose output terminal is the second latch circuit a first output terminal of (112);

A fourth flip-flop (F4), whose input end is connected to the output end of the third flip-flop (F3), whose clock end is used to receive the first latch clock signal, and whose output end is the second latch clock signal. The second output terminal of the storage circuit (112).
The data extraction circuit according to claim 2, wherein the second input circuit (120) comprises:

A third latch circuit (121), which is provided with an output terminal, configured to establish the first identification data at its output terminal triggered by the first latch clock signal and the second latch clock signal;

A fourth latch circuit (122), which is provided with an output terminal, configured to establish the second identification data at its output terminal triggered by the second latch clock signal;

Wherein, the time corresponding to the rising edge of the first latch clock signal is the same as the time corresponding to the rising edge of the second data clock signal.
The data extraction circuit according to claim 2, wherein the second input circuit (120) comprises:

A third latch circuit (121), which is provided with an output terminal, configured to establish the second identification data at its output terminal triggered by the first latch clock signal and the second latch clock signal;

A fourth latch circuit (122), which is provided with an output terminal, configured to establish the first identification data at its output terminal triggered by the second latch clock signal;

Wherein, the time corresponding to the rising edge of the second latch clock signal is the same as the time corresponding to the rising edge of the second data clock signal.
The data extraction circuit according to claim 6 or 7, wherein;

The third latch circuit (121) includes:

A fifth flip-flop (F5), whose input terminal receives the first identification data and the second identification data, and whose clock terminal receives the first latch clock signal;

The sixth flip-flop (F6), its input end is connected to the output end of the fifth flip-flop (F5), its clock end receives the second latch clock signal, and its output end is the third latch circuit (121) output terminal;

The fourth latch circuit (122) includes:

A seventh flip-flop (F7), whose input terminal receives the first identification data and the second identification data, and whose clock terminal receives the second latch clock signal;

The eighth flip-flop (F8), whose input end is connected to the output end of the seventh flip-flop (F7), whose clock end receives the first latch clock signal, and whose output end is the fourth latch circuit (122) output.
The data extraction circuit according to claim 3 or 4, wherein the output circuit (130) comprises:

The first selection circuit (131), its first input terminal is connected with the second output terminal of the first latch circuit (111), its second input terminal is connected with the second output terminal of the second latch circuit (112). The output terminal is connected, its first control terminal is connected with the output terminal of the third latch circuit (121), and its second control terminal is connected with the output terminal of the fourth latch circuit (122), which is used to identify establishes at its output the first input data under the control of data and said second identification data;

The second selection circuit (132), its first input terminal is connected to the first output terminal of the second latch circuit (112), its second input terminal is connected to the first output terminal of the first latch circuit (111) The output terminal is connected, its first control terminal is connected with the output terminal of the third latch circuit (121), and its second control terminal is connected with the output terminal of the fourth latch circuit (122), for Establishing second input data at its output under the control of said first identification data and said second identification data.
The data extraction circuit according to claim 9, wherein;

The first selection circuit (131) includes:

The first transmission gate (G1), its input terminal is the first input terminal of the first selection circuit (131), its control terminal is the first control terminal of the first selection circuit (131), its output terminal is an output terminal of the first selection circuit (131);

The second transmission gate (G2), its input terminal is the second input terminal of the first selection circuit (131), its control terminal is the second control terminal of the first selection circuit (131), its output terminal is connected the output terminal of the first transmission gate (G1);

The second selection circuit (132) includes:

The third transfer gate (G3), its input terminal is the first input terminal of the second selection circuit (132), its control terminal is the first control terminal of the second selection circuit (132), its output terminal is an output terminal of the second selection circuit (132);

The fourth transmission gate (G4), whose input end is the second input end of the second selection circuit (132), whose control end is the second control end of the second selection circuit (132), and whose output end is connected to The output of the first transmission gate (G1).
The data extraction circuit according to claim 3 or 4, wherein;

The first input circuit (110) also includes:

The first receiving circuit (113), its output end is connected with the input end of the first latch circuit (111), and its output end is also connected with the input end of the second latch circuit (112), for performing amplification processing on the first input data and the second input data;

The second input circuit (120) also includes:

The second receiving circuit (123), its output end is connected with the input end of the third latch circuit (121), and its output end is also connected with the input end of the fourth latch circuit (122), for the first The identification data and the second identification data are enlarged.
The data extraction circuit according to any one of claims 1 to 4, wherein the data extraction circuit further comprises:

a clock circuit (140), which is connected to the clock terminal of the first input circuit (110), and is also connected to the clock terminal of the second input circuit (120), for generating a clock signal according to the first data A first latch clock signal and a second latch clock signal.
The data extraction circuit according to claim 12, wherein the clock circuit (140) specifically comprises:

A third receiving circuit (141), configured to receive the first data clock signal;

A frequency division circuit (142), which is connected to the third receiving circuit (141), its output terminal is connected to the clock terminal of the first input circuit (110), and its output terminal is also connected to the second input circuit ( 120) is connected to the clock terminal, which is used to divide the frequency of the first data clock signal to output the first latch clock signal and the second latch clock signal.
The data extraction circuit according to claim 13, wherein the signal period of the first latch clock signal is twice the signal period of the first data clock signal.
The data extraction circuit according to claim 11, wherein;

The first input circuit (110) also includes:

The first buffer circuit (114), its input terminal is connected to the first receiving circuit (113), its output terminal is connected to the input terminal of the first latch circuit (111), and its output terminal is also connected to the second The input end of the latch circuit (112) is connected to buffer the first input data and the second input data for signal amplification;

The second input circuit (120) also includes:

The second buffer circuit (124), its input terminal is connected to the second receiving circuit (123), its output terminal is connected to the input terminal of the third latch circuit (121), and its output terminal is also connected to the fourth The input end of the latch circuit (122) is connected to buffer the first identification data and the second identification data for signal amplification.
The data extraction circuit according to any one of claims 1 to 4, wherein the first input data is instruction data, and the second input data is address data.