WO2021184907A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2021184907A1
WO2021184907A1 PCT/CN2020/140841 CN2020140841W WO2021184907A1 WO 2021184907 A1 WO2021184907 A1 WO 2021184907A1 CN 2020140841 W CN2020140841 W CN 2020140841W WO 2021184907 A1 WO2021184907 A1 WO 2021184907A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
layer
substrate
emitting
optical sensor
Prior art date
Application number
PCT/CN2020/140841
Other languages
English (en)
French (fr)
Inventor
韩影
王玲
林奕呈
徐攀
张星
王国英
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/416,522 priority Critical patent/US20220359635A1/en
Publication of WO2021184907A1 publication Critical patent/WO2021184907A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • This article relates to, but is not limited to, the field of display technology, in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Device
  • OLED Organic Light-Emitting Device
  • the present disclosure provides a display substrate, a preparation method thereof, and a display device.
  • the present disclosure provides a display substrate including: a substrate and a plurality of light-emitting units and a plurality of light-detecting units on the substrate; at least one light-emitting unit includes: a light-emitting element and a pixel coupled to the light-emitting element Drive circuit, at least one light detection unit includes: an optical sensor element and a light emission detection circuit coupled to the optical sensor element; the optical sensor element is located in the light emission detection circuit and the pixel drive circuit away from the One side of the substrate is located between the light-emitting element and the substrate; the light-emitting element emits light from the side away from the substrate, and the light-emitting element has a light-transmitting element on the side facing the optical sensor element.
  • Light area, and the orthographic projection of the light-transmitting area on the substrate and the orthographic projection of the optical sensing element on the substrate at least partially overlap.
  • the present disclosure provides a display device including the display substrate as described above.
  • the present disclosure provides a method for manufacturing a display substrate, including: forming a pixel driving circuit of a light emitting unit and a light detecting circuit of a light detecting unit on a substrate; and forming a light detecting unit on the pixel driving circuit and the light emitting detecting circuit
  • the optical sensor element wherein the optical sensor element is coupled to the light-emitting detection circuit; the light-emitting element of the light-emitting unit is formed on the optical sensor element, wherein the light-emitting element and the pixel
  • the driving circuit is coupled, the light-emitting element emits light from a side away from the substrate, the light-emitting element has a light-transmitting area on the side facing the optical sensor element, and the light-transmitting area is on the substrate
  • the orthographic projection on the substrate and the orthographic projection of the optical sensing element on the substrate at least partially overlap.
  • FIG. 1 is a schematic diagram of the structure of a bottom-emission OLED display substrate
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • FIG. 3 is an example diagram of a partial cross-sectional structure of a display substrate provided by an embodiment of the present disclosure
  • FIG. 4 is a diagram showing an example of the structure of a pixel driving circuit in an embodiment of the disclosure.
  • FIG. 5 is a diagram showing an example of the structure of a luminescence detection circuit in an embodiment of the disclosure.
  • FIG. 6 is a working sequence diagram of a display substrate according to an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of an embodiment of the disclosure after a pattern of a shielding layer is formed
  • FIG. 8 is a schematic diagram after forming an active layer pattern according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an embodiment of the disclosure after forming a gate electrode pattern
  • FIG. 10 is a schematic diagram after a third insulating layer pattern is formed according to an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of an embodiment of the disclosure after source electrode and drain electrode patterns are formed
  • FIG. 12 is a schematic diagram of an embodiment of the disclosure after forming a fifth insulating layer pattern
  • FIG. 13 is a schematic diagram of an embodiment of the disclosure after forming a second cathode pattern connecting electrodes and optical sensor elements;
  • 15 is a schematic diagram of an embodiment of the disclosure after forming a second flat layer pattern
  • FIG. 16 is a schematic diagram after forming a first anode pattern of a light-emitting element according to an embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of an embodiment of the disclosure after forming a pixel definition layer pattern
  • FIG. 18 is a schematic diagram after forming the first cathode of the light-emitting element according to an embodiment of the present disclosure
  • FIG. 19 is a schematic diagram of the influence of the first flat layer on the dark-state current provided by an embodiment of the present disclosure.
  • 20 is a partial cross-sectional structure example diagram of a display substrate provided by another embodiment of the present disclosure.
  • FIG. 22 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique technical solution defined by the claims.
  • Any feature or element of any embodiment can also be combined with features or elements from other technical solutions to form another unique technical solution defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure can be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
  • one or more modifications and changes may be made within the protection scope of the appended claims.
  • the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method or process should not be limited to performing their steps in the written order, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.
  • Electrode connection includes the case where the constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements. Examples of “elements having a certain electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, a state where the angle is -5° or more and 5° or less is also included.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the “semiconductor” in the present disclosure can sometimes be replaced with an “insulator”.
  • the “insulator” in the present disclosure can sometimes be replaced with a “semiconductor”.
  • the “insulator” in the present disclosure may sometimes be replaced with a “semi-insulator”.
  • the “semiconductor” in the present disclosure can sometimes be replaced with “conductor”.
  • the “conductor” in the present disclosure can sometimes be replaced with a “semiconductor”.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in the present disclosure, the “source electrode” and the “drain electrode” can be interchanged with each other.
  • FIG. 1 is a schematic diagram of the structure of a bottom-emission OLED display substrate.
  • the circuit structure 12, the optical sensor element 14, and the light-emitting element 16 are arranged on the substrate 10 and are all located under the cover plate 17.
  • the light-emitting element 16 emits light from the side of the substrate 10; wherein, the circuit structure 12 includes a coupling
  • the pixel driving circuit connected to the light-emitting element 16 and the light-emitting detection circuit coupled to the optical sensor element 14.
  • the circuit structure 12 needs to occupy a part of the opening area of the light-emitting element 16, which will limit the pixel aperture ratio and resolution (PPI, Pixels Per Inch) of the bottom-emission OLED display substrate; moreover, the optical sensor element 14 needs to receive light.
  • the light-receiving area of the optical sensor element 14 will additionally occupy a part of the opening area of the light-emitting element 16, thereby further limiting the pixel aperture ratio and resolution of the bottom-emitting OLED display substrate.
  • This embodiment provides a display substrate, including: a base, a plurality of light-emitting units and a plurality of light-detecting units on the base, at least one light-emitting unit includes a light-emitting element and a pixel drive circuit coupled to the light-emitting element, and at least one light-detecting unit
  • the unit includes an optical sensor element and a light-emitting detection circuit coupled with the optical sensor element; wherein the optical sensor element is located on the side of the light-emitting detection circuit and the pixel driving circuit away from the substrate, and is located between the light-emitting element and the substrate; Light is emitted from the side away from the substrate, the light-emitting element has a light-transmitting area on the side facing the optical sensor element, and the orthographic projection of the light-transmitting area on the substrate and the orthographic projection of the optical sensor element on the substrate at least partially overlap .
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure. As shown in FIG. 2, the pixel drive circuit 21 and the light emission detection circuit 22 are arranged on the substrate 20, the optical sensor element 24 is located on the side of the pixel drive circuit 21 and the light emission detection circuit 22 away from the substrate 20, and the light emitting element 26 is located on the optical sensor.
  • the cover plate 27 is located above the light-emitting element 26; the light-emitting element 26 emits light from the side away from the substrate 20, and the light-emitting element 26 has a light-transmitting area on the side facing the optical sensor element 24, and the light-transmitting area
  • the orthographic projection on the substrate and the orthographic projection of the optical sensing element 24 on the substrate 20 at least partially overlap.
  • the optical sensor element 24 located below the light-emitting element 26 can receive the light emitted by the light-emitting element 26, so that the light-emitting detection circuit 22 detects the brightness signal of the light-emitting element 26 through the optical sensor element 24, and emits light according to the brightness signal.
  • Element 26 performs brightness compensation.
  • the light emitting element 26 emits light upward (that is, emitting light to the side away from the substrate 20) to achieve display, and a part of the light emitted by the light emitting element 26 downward (that is, the side facing the substrate 20) can be provided to the optical sensor element. 24, so that the optical sensor element 24 can detect the luminous brightness, and the remaining light can be directly reflected back to the upper surface of the luminous element 26 for display.
  • the display substrate with the top emission structure provided in this embodiment can greatly increase the pixel aperture ratio and resolution to support obtaining a better display effect.
  • the light-emitting element may include: a first anode, a light-emitting functional layer, and a first cathode that are sequentially stacked in a direction away from the substrate; the first cathode uses a light-transmitting material; the first anode includes a reflective layer and a light-transmitting material.
  • the orthographic projection of the light-transmitting layer on the substrate and the orthographic projection of the optical sensor element on the substrate at least partially overlap, and the overlap area is the photosensitive area of the optical sensor element to the light-emitting element.
  • the light-transmitting design is implemented in the area where the first anode of the light-emitting element corresponds to the optical sensor element, so that the part of the light-emitting element on the side facing the optical sensor element is transparent.
  • the optical sensor element can receive the light emitted by the light-emitting element, and does not occupy the opening area of the light-emitting unit.
  • the orthographic projection of the light-transmitting layer on the substrate covers the orthographic projection of the reflective layer on the substrate, and an area of the light-transmitting layer that is not blocked by the reflective layer forms a light-transmitting area.
  • this disclosure is not limited to this.
  • the orthographic projection of the light-transmitting layer on the substrate and the orthographic projection of the reflective layer on the substrate may only partially overlap.
  • the display substrate may further include: a first flat layer, and the first flat layer is located between the optical sensor element and the light-emitting detection circuit.
  • the first flat layer is located between the optical sensor element and the light-emitting detection circuit.
  • the display substrate may further include: a first passivation layer and a second passivation layer, the first passivation layer is located between the luminescence detection circuit and the first flat layer, and the second passivation layer is located on the second passivation layer. Between a flat layer and the optical sensor element. In this exemplary embodiment, by providing passivation layers on both sides of the first flat layer, the influence of the first flat layer on other film layers and structures can be blocked.
  • the light emitting unit and the light detecting unit may have a one-to-one correspondence relationship, or the light emitting unit and the light detecting unit may have a many-to-one correspondence relationship.
  • one light-emitting unit can be optically compensated by one light-detecting unit, or multiple light-emitting units can be multiplexed with one light-detecting unit for optical compensation.
  • FIG. 3 is an example diagram of a partial cross-sectional structure of a display substrate provided by an embodiment of the present disclosure.
  • at least one light-emitting unit includes a pixel driving circuit and a light-emitting element sequentially arranged on the substrate 20, wherein the pixel driving circuit includes a plurality of thin film transistors, which may be 2T1C, 3T1C Or a 7T1C design.
  • the pixel driving circuit includes a plurality of thin film transistors, which may be 2T1C, 3T1C Or a 7T1C design.
  • the pixel driving circuit includes a plurality of thin film transistors, which may be 2T1C, 3T1C Or a 7T1C design.
  • the pixel driving circuit includes a plurality of thin film transistors, which may be 2T1C, 3T1C Or a 7T1C design.
  • the pixel driving circuit includes a plurality of thin film transistors, which may be 2T1C, 3T1C Or a
  • the pixel driving circuit may adopt a 3T1C design
  • the luminescence detection circuit may adopt a 1T1C design.
  • this disclosure is not limited to this.
  • FIG. 4 is a diagram showing an example of the structure of a pixel driving circuit in an embodiment of the disclosure.
  • the pixel driving circuit in this embodiment may include: a driving transistor M1, a first switching transistor M2, a second switching transistor M3, and a first storage capacitor C1.
  • FIG. 5 is a diagram showing an example of the structure of a light emission detection circuit in an embodiment of the disclosure.
  • the light emission detection circuit includes: a third switch transistor M4 and a second storage capacitor C2.
  • the control electrode of the third switch transistor M4 is coupled to the second scan signal line G2
  • the first electrode of the third switch transistor M4 is coupled to the detection signal line SL
  • the second electrode of the third switch transistor M4 is coupled to the optical sensor
  • the second cathode of the element DP is coupled;
  • the first electrode of the second storage capacitor C2 is coupled to the second cathode of the optical sensor element DP, and the second electrode of the second storage capacitor C2 is coupled to the second anode of the optical sensor element DP Coupled
  • the second storage capacitor C2 is configured to store the electrical signal converted by the optical sensor element DP;
  • the second anode of the optical sensor element DP is coupled to the second reference signal line V2.
  • the optical sensor element DP may be a PIN-type photodiode
  • FIG. 6 is a working sequence diagram of the display substrate of this embodiment.
  • the switching transistors M2 to M4 and the driving transistor M1 in the circuit provided in this embodiment as an example of N-type transistors for description.
  • the N-type switching transistor is turned on when the gate is at a high level, and turned off when the gate is at a low level.
  • the switching transistors and driving transistors in the embodiments of the present disclosure may also be P-type transistors. Among them, the P-type switching transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level.
  • the display substrate provided by this embodiment can perform optical compensation through the following five working stages.
  • the third switch transistor M4 is turned on under the high-level control of the signal g2 of the second scan signal line G2, and connects the second cathode of the optical sensor element DP to the detection signal line SL. Is turned on, so that the second cathode of the optical sensor element DP is applied with a positive voltage; the reference signal line V2 is applied with a negative voltage (for example, -5V), and the second anode of the optical sensor element DP is applied with a negative voltage, thereby optical transmission
  • the sensing element DP works in a reverse bias state.
  • the first switching transistor M2 and the second switching transistor M3 are turned off under the low level control of the signal g1 of the first scan signal line G1.
  • the first switching transistor M2 and the second switching transistor M3 are turned on under the high-level control of the signal g1 of the first scan signal line G1; the first switching transistor M2 transfers the data
  • the signal dl (data voltage Vdata) provided by the signal line DL is provided to the control electrode of the driving transistor M1, so that the gate voltage of the driving transistor M1 is Vdata, which is stored by the first storage capacitor C1;
  • a reference voltage signal (for example, 0V) transmitted on a reference signal line V1 is provided to the light-emitting element EL, and the voltage value of the reference voltage signal is smaller than the voltage value of the signal of the second power terminal VSS, so that the light-emitting element EL is in a reverse bias state.
  • the third switch transistor M4 is turned off under the low level control of the signal g2 of the second scan signal terminal G2.
  • the first switching transistor M2 and the second switching transistor M3 are turned off under the low level control of the signal g1 of the first scanning signal terminal G1, and the third switching transistor M4 is in the second scanning signal
  • the signal g2 at the terminal G2 is turned off under the low level control.
  • Vs is the source voltage of the driving transistor M1
  • Vth is the threshold voltage of the driving transistor M1
  • K is a fixed constant related to the process parameters and geometric dimensions of the driving transistor M1.
  • the source voltage Vs of the driving transistor M1 may be the voltage value of the reference voltage signal transmitted on the first reference signal line V1.
  • the driving current I generated by the driving transistor M1 can drive the light-emitting element EL to emit light, so that the optical sensor element DP can receive the light emitted by the light-emitting element EL and convert the received light into electric current, so that the optical sensor element DP
  • the voltage of the second cathode changes.
  • the first switching transistor M2 and the second switching transistor M3 are turned on under the high-level control of the signal g1 of the first scan signal terminal G1; the turned-on first switching transistor M2
  • the signal dl (0V data voltage) provided by the data signal line DL is provided to the control electrode of the driving transistor M1, and the turned-on second switching transistor M3 transmits the reference voltage signal (for example, 0V) transmitted on the first reference signal line V1
  • the light-emitting element EL is provided so that the light-emitting element EL stops emitting light, thereby ensuring that the voltage of the second cathode of the optical sensor element PD is stable.
  • the third switching transistor M4 is turned on under the high-level control of the signal g2 of the second scanning signal line G2, so as to conduct the optical sensor element DP and the detection signal line SL. , Thereby transmitting the voltage of the second cathode of the optical sensor element DP to the detection signal line SL.
  • the voltage on the detection signal line SL is obtained by the driver integrated circuit (IC) for analysis and compensation calculation, so as to improve the screen display effect.
  • the thin film transistor in the second area A2 shown in FIG. 3 may be the driving transistor M1 in the pixel driving circuit shown in FIG. 4.
  • the driving transistor M1 includes: a first active layer 212, a first gate electrode 215, a first source electrode 221, a first drain electrode 220, a first connection electrode 223, and a second connection electrode 222; a light emitting element It includes a first anode, a pixel defining layer 263, a light-emitting function layer 264, and a first cathode 265.
  • the first anode includes a reflective layer 261 and a light-transmitting layer 262; the reflective layer 261 of the first anode is coupled to the first connecting electrode 223 , The first connection electrode 223 is coupled to the first source electrode 221 of the driving transistor M1 to realize the coupling between the first anode and the first source electrode 221 of the driving transistor M1.
  • the thin film transistor in the first area A1 shown in FIG. 3 may be the third switch transistor M4 in the light emission detection circuit shown in FIG. 5.
  • the third switching transistor M4 includes: a second active layer 213, a second gate electrode 216, a second source electrode 219, and a second drain electrode 218;
  • the optical sensor element includes a second cathode 241, photoelectric conversion The structure 242, the second anode 243, and the third connecting electrode 244; the second cathode 241 is coupled to the second source electrode 219 of the third switching transistor M4.
  • the structure of the thin film transistor in the pixel driving circuit and the structure of the thin film transistor in the light emission detection circuit can be the same, and they can be prepared simultaneously through the same process.
  • the light-emitting element emits light from the side away from the substrate 20, and the light-emitting element transmits light to the optical sensor element through the light-transmitting area formed by the light-transmitting layer 262 and the reflective layer 261, so that the optical sensor element
  • the light emitted by the light-emitting element can be received for light-emitting brightness detection to realize optical compensation.
  • the technical solution of this embodiment is further described below through the preparation process of the display substrate of this embodiment.
  • the "patterning process” referred to in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping.
  • Known and mature preparation processes can be used.
  • the deposition may use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating may use a known coating process, and the etching may use a known method, which is not limited herein.
  • thin film refers to a thin film made by depositing a certain material on a substrate or other processes.
  • the preparation process of the display substrate provided in this embodiment may include the following steps (1) to (14).
  • a shield layer pattern is formed on the substrate.
  • Forming the shielding layer pattern includes depositing a shielding film on the substrate 20, patterning the shielding film through a patterning process, and forming a shielding layer 210 pattern on the substrate 20, as shown in FIG. 7.
  • a shielding layer 210 can be provided at a corresponding position of each thin film transistor, and the shielding layer 210 can effectively absorb and shield ambient light.
  • the substrate 20 may be a flexible substrate, using materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • surface-treated polymer soft film PI
  • Forming the active layer pattern includes: sequentially depositing a first insulating film and an active film on the substrate 20 formed with the aforementioned pattern, and patterning the active film through a patterning process to form a first insulating layer 211 covering the shielding layer 210. And the first active layer 212 and the second active layer 213 formed on the first insulating layer 211, as shown in FIG. 8. Among them, the first active layer 212 serves as the active layer of the driving transistor M1, and the second active layer 213 serves as the active layer of the third switching transistor M4.
  • the first insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high dielectric constant (High-k) materials, such as aluminum oxide (AlOx), Hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • the first insulating layer 211 is referred to as a buffer layer.
  • the active film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si) ), hexathiophene, polythiophene and other one or more materials, that is, this embodiment is suitable for thin film transistors (TFT, Thin Film) manufactured based on oxide (Oxide) technology, silicon technology, and organic technology. Transistor) display substrate.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • hexathiophene polythiophene
  • Transistor Transistor
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum neodymium (AlNd), molybdenum niobium
  • the alloy (MoNb), etc. can be a multilayer metal, such as Mo/Cu/Mo, etc., or can be a stack structure formed by a metal and a transparent conductive material, such as ITO/Ag/ITO, etc.
  • the second insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx), Tantalum oxide (TaOx), etc., can be a single layer, a multi-layer or a composite layer.
  • the second insulating layer 214 is referred to as a gate insulating (GI) layer.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate 20 formed with the aforementioned pattern, and patterning the third insulating film through a patterning process to form a pattern of the third insulating layer 217 covering the aforementioned structure;
  • the layer 217 is provided with a plurality of via holes, which are respectively the first via holes V11 and V12 at the two ends of the first active layer 212, and the first via holes V13 and V14 at the two ends of the second active layer 213, as shown in FIG. 10 shown.
  • the third insulating layer can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx), Tantalum oxide (TaOx), etc., can be a single layer, a multi-layer or a composite layer.
  • the third insulating layer 217 is referred to as an interlayer insulation (ILD) layer.
  • ILD interlayer insulation
  • Forming source and drain electrode patterns includes: depositing a second metal film on the substrate 20 formed with the above structure, patterning the second metal film through a patterning process, and forming a power supply line on the third insulating layer 217 (not shown) Out), the data signal line (not shown in the figure), the reference signal line (not shown in the figure), the first source electrode 221, the first drain electrode 220, the second source electrode 219 and the second drain electrode 218 pattern, as shown in the figure 11 shown.
  • the second metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum neodymium alloy (AlNd), molybdenum niobium
  • the alloy (MoNb), etc. can be a multilayer metal, such as Mo/Cu/Mo, etc., or can be a stack structure formed by a metal and a transparent conductive material, such as ITO/Ag/ITO, etc.
  • Forming the fourth insulating layer, the first flat layer, and the fifth insulating layer includes: first depositing a fourth insulating film on the first area A1 and the second area A2 on the substrate 20 formed with the aforementioned pattern to form a structure covering the aforementioned structure Then, the first planarization film is coated on the first area A1, and the first planarization layer 232 covering the aforementioned structure is formed in the first area A1 through the photolithography process of mask exposure and development, and then in the first area A1 A fifth insulating film is deposited in the area A1 and the second area A2 to form a pattern of the fifth insulating layer 233 covering the foregoing structure; the fifth insulating layer 233 is formed with second via holes V21, V22, and V23; wherein, the second via hole V21 Located at the position of the second source electrode 219, the fourth insulating layer 231, the first flat layer 232, and
  • the fourth insulating film and the fifth insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high-k materials, such as aluminum oxide (AlOx), oxide Hafnium (HfOx), tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • the material of the first planarization film includes, but is not limited to, polysiloxane-based materials, acrylic-based materials, or polyimide-based materials.
  • the fourth insulating layer 231 and the fifth insulating layer 233 are called passivation (PVX, Passivation) layers
  • the fourth insulating layer 231 is the aforementioned first passivation layer
  • the fifth insulating layer 233 is the aforementioned first passivation layer. Two passivation layer.
  • a second cathode pattern connecting the electrode and the optical sensor element is formed.
  • Forming the second cathode pattern connecting the electrode and the optical sensor element includes: depositing a third metal film on the substrate 20 formed with the aforementioned pattern, and patterning the third metal film through a patterning process to form the first connecting electrode 223,
  • the pattern of the second connecting electrode 222 and the second cathode 241 of the optical sensor element is as shown in FIG. 13.
  • the first connection electrode 223 is coupled to the first source electrode 221 through the second via hole V23
  • the second connection electrode 222 is coupled to the first gate electrode 215 through the second via hole V22
  • the second cathode 241 is coupled to the first gate electrode 215 through the second via hole V22.
  • the hole V21 is coupled to the second source electrode 219.
  • the third metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum neodymium alloy (AlNd), molybdenum niobium
  • the alloy (MoNb), etc. can be a multilayer metal, such as Mo/Cu/Mo, etc., or can be a stack structure formed by a metal and a transparent conductive material, such as ITO/Ag/ITO, etc.
  • the simultaneous preparation of the thin film transistor located in the first area A1 and the thin film transistor located in the second area A2 can be completed on the substrate 20.
  • the driving transistor M1 located in the second area A2 may include: a first active layer 212, a first gate electrode 215, a first source electrode 221, a first drain electrode 220, a first connection electrode 223, and a second connection electrode 222 .
  • the third switching transistor M4 located in the first region A1 may include: a second active layer 213, a second gate electrode 216, a second source electrode 219, and a second drain electrode 218.
  • the second cathode 241 of the optical sensor element can be multiplexed as the first electrode of the second storage capacitor C2 coupled to it, and the second electrode of the second storage capacitor C2 can be connected to the
  • the second source electrode 219 and the second drain electrode 218 of the third switch transistor M4 are made of the same layer and the same material.
  • this disclosure is not limited to this.
  • the layout of the second storage capacitor can be determined according to actual needs.
  • the first active layer 212 and the second active layer 213 are arranged in the same layer, and are formed at the same time through the same patterning process; the first gate electrode 215 and the second gate electrode 216 are arranged in the same layer, and are formed through the same layer.
  • the second patterning process is formed at the same time; the first source electrode 221, the first drain electrode 220, the second source electrode 219, the second drain electrode 218, and the first electrode of the second storage capacitor are arranged in the same layer, and are formed at the same time through the same patterning process ;
  • the first connection electrode 223, the second connection electrode 222 and the second electrode of the second storage capacitor are arranged in the same layer, and are formed at the same time through the same patterning process.
  • Forming the photoelectric conversion structure of the optical sensor element and the second anode pattern includes: forming a photoelectric conversion structure 242 on the second cathode 241 in the first area A1, depositing a first transparent conductive film on the photoelectric conversion structure 242, and The patterning process patterns the first transparent conductive film to form a pattern of the second anode 243, as shown in FIG. 14.
  • the optical sensor element may be a PIN-type photodiode; wherein, the photoelectric conversion structure 242 includes: a PN junction and a layer of I-type semiconductor with a very low concentration doped in the middle of the PN junction;
  • the concentration of I-type semiconductor is low, almost intrinsic (Intrinsic) semiconductor, therefore, it can also be called I-layer, on both sides of I-layer are P-type semiconductor and N-type semiconductor with high doping concentration, that is, P-layer and N-layer are formed
  • the P and N layers are very thin, and the proportion of absorbing incident light is very small, so that most of the incident light is absorbed in the I layer and generate a large number of electron-hole pairs, while the I layer is thicker, almost occupying the entire
  • the depletion zone can be realized by increasing the width of the depletion zone to reduce the influence of diffusion movement and improve the response speed of the photodiode.
  • the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO) or the like.
  • the sixth insulating layer 251 and the second flat layer 252 in the third via V3 are removed, exposing the first The surface of the second anode 243; the fourth via hole V4 is located at the position of the first connecting electrode 223, the sixth insulating layer 251 and the second flat layer 252 in the fourth via hole V4 are removed, exposing the surface of the first connecting electrode 223 , As shown in Figure 15.
  • the sixth insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx), Tantalum oxide (TaOx), etc., can be a single layer, a multi-layer or a composite layer.
  • the sixth insulating layer may be referred to as a passivation (PVX) layer.
  • the material of the second planarization film includes, but is not limited to, polysiloxane-based materials, acrylic-based materials, or polyimide-based materials.
  • Forming the pattern of the first anode and the third connecting electrode includes: depositing a fourth metal film on the substrate 20 forming the aforementioned pattern, and patterning the fourth metal film through a patterning process to form a pattern of the reflective layer 261; then, forming the aforementioned structure
  • a second transparent conductive film is deposited on the substrate 20 of, and the second transparent conductive film is patterned through a patterning process to form a pattern of the light-transmitting layer 262 and the third connecting electrode 244, as shown in FIG. 16.
  • the third connecting electrode 244 is located in the first area A1, the third connecting electrode 244 is coupled to the second anode 243 of the optical sensor element through the third via V3, and the third connecting electrode 244 can also be coupled to the second reference signal.
  • Line V2 to realize the coupling between the second anode 243 and the second reference signal line V2.
  • the reflective layer 261 is coupled to the first connection electrode 223 through the fourth via hole V4 to realize the coupling between the first anode of the light emitting element and the first source electrode 221 of the driving transistor M1.
  • the light-transmitting layer 262 and the reflective layer 261 are both conductive materials, which can transmit the driving current provided by the first source electrode 221 of the driving transistor M1 to the light-emitting function layer of the light-emitting element.
  • the transparent layer 262 is located on the reflective layer 261, the orthographic projection of the transparent layer 262 on the substrate 20 covers the orthographic projection of the reflective layer 261 on the substrate 20; the orthographic projection of the transparent layer 262 on the substrate 20 It overlaps with the orthographic projection of the photoelectric conversion structure 242 of the optical sensor element on the substrate 20, that is, the orthographic projection of the light-transmitting layer 262 on the substrate 20 overlaps with the orthographic projection of the photosensitive area of the optical sensor element.
  • the light-transmitting area of the light-emitting element is formed by the area of the light-transmitting layer 262 that is not blocked by the reflective layer 261.
  • the light-transmitting area of the light-emitting element may be formed by a light-transmitting layer that is not blocked by the reflective layer.
  • the light-transmitting layer may not cover the reflective layer, and part of the light emitted downward by the light-emitting element can pass through the light-transmitting layer.
  • the layer irradiates the photosensitive area of the optical sensor element so that the optical sensor element can perform brightness detection.
  • the remaining light emitted by the light-emitting element downward can directly illuminate the emitting layer, and this part of the light is reflected to the light-emitting side of the light-emitting element by the reflective layer. Used for display.
  • the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the optical sensor element located in the first area A1 includes: a second cathode 241, a photoelectric conversion structure 242, and a second The anode 243 and the third connection electrode 244.
  • the third connecting electrode 244 and the light-transmitting layer 262 of the first anode of the light-emitting element are arranged in the same layer, and are formed at the same time through the same patterning process.
  • Forming the pattern of the pixel definition layer includes: coating a pixel definition film on the substrate 20 forming the aforementioned pattern, forming a pattern of the pixel definition layer 263 through mask exposure and development, and defining an opening area KA that exposes the light-transmitting layer 262 of the first anode , As shown in Figure 17.
  • the pixel definition film can be made of materials such as polyimide, acrylic or polyethylene terephthalate.
  • Forming the pattern of the light-emitting functional layer includes: forming a pattern of the light-emitting functional layer 264 in the opening area KA by evaporation or inkjet printing on the substrate 20 forming the aforementioned pattern, the light-emitting functional layer 264 and the light-transmitting layer of the first anode 262 coupling, as shown in Figure 18.
  • the light-emitting function layer 264 includes an luminescent material layer (EML, Emitting Layer).
  • EML luminescent material layer
  • the light-emitting function layer 264 may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer sequentially arranged to improve the efficiency of electrons and holes injection into the light-emitting layer.
  • Forming the first cathode pattern of the light-emitting element includes: forming the first cathode 265 of the light-emitting element by evaporation on the substrate 20 forming the aforementioned pattern, and the first cathode 265 is coupled to the light-emitting function layer 264, as shown in FIG. 18.
  • the material of the first cathode 265 may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the light emitting element can emit light from the side away from the substrate 20 through the transparent first cathode 265 to achieve top emission.
  • the light-emitting element includes the first anode (the reflective layer 261 and the light-transmitting layer 262), the pixel defining layer 263, and the light-emitting function layer 264. And the first cathode 265.
  • the encapsulation layer can be an inorganic/organic/inorganic three-layer structure to complete the encapsulation of the display substrate.
  • the circuit structure in the first area A1 and the second area A2 is synchronously prepared on the substrate in this embodiment, and then the optical sensor is prepared in the first area A1.
  • Components, light-emitting components are prepared in the first area A1 and the second area A2 to realize the display substrate of the top emission structure, and the arrangement of the optical sensor element will not affect the pixel aperture ratio of the display substrate, thereby greatly improving the pixel aperture of the display substrate Rate and resolution are suitable for high PPI displays, reducing power consumption; moreover, the circuit structures in the first area A1 and the second area A2 can be prepared simultaneously, with high integration, simplifying the preparation process of the display substrate and saving Preparation cost.
  • the bottom of the optical sensing element is provided with a first flat layer, which can ensure the usability of the optical sensing element on the basis of a high level difference at the bottom.
  • the optical sensing element as a PIN photodiode as an example, when the bottom segment of the PIN photodiode is large, the dark state current will be high.
  • FIG. 19 is a schematic diagram of the influence of the first flat layer on the dark-state current provided by an embodiment of the disclosure.
  • the solid line indicates the case where there is a first flat layer and pattern under the PIN-type photodiode (that is, there is a step at the bottom), and the dotted line indicates the case where there is no first flat layer under the PIN-type photodiode and there is a pattern underneath.
  • the line represents the case where there is no first flat layer under the PIN-type photodiode and there is no pattern under it.
  • the dark-state current of the PIN-type photodiode is relatively large.
  • the PIN-type photodiode After the first flat layer is added below, the PIN-type photodiode’s
  • the dark-state current can be reduced by about 64%, which is comparable to that of the PIN-type photodiode without a step.
  • setting the first flat layer under the PIN photodiode can ensure that the characteristics of the PIN photodiode can be used in the case of a high-level difference at the bottom, and avoid affecting the accuracy of the brightness signal detected by the PIN photodiode, thereby ensuring The accuracy and effect of optical compensation.
  • the structure (or method) shown in this embodiment mode can be appropriately combined with the structure (or method) shown in other embodiments.
  • FIG. 20 is a partial cross-sectional structure example diagram of a display substrate provided by another embodiment of the present disclosure.
  • the main structure of the display substrate provided in this embodiment is basically the same as the embodiment described in FIG. 3, except that the structure and preparation method of the first anode of the light-emitting element of the display substrate in this embodiment are different.
  • the process of preparing the pixel driving circuit, the luminescence detection circuit, and the second cathode of the optical sensor element, the photoelectric conversion structure, and the second anode are the same as those in the previous embodiment. You can refer to steps (1) to (1) to the previous embodiment. Step (9).
  • Step (10) forming the first anode and the third connecting electrode pattern.
  • Forming the first anode and third connecting electrode patterns includes: sequentially depositing a transparent conductive film, a metal film, and a transparent conductive film on the substrate 20 forming the aforementioned pattern, and etching the transparent conductive film and the metal film on the top layer through a patterning process, A pattern of the reflective layer 261 is formed, and then the transparent conductive film on the bottom layer is etched to form a pattern of the light-transmitting layer 262 and the third connecting electrode 244, as shown in FIG. 20.
  • part of the light emitted downward from the light-emitting element can be irradiated to the photosensitive area of the optical sensor element through the light-transmitting layer 262, so that the optical sensor element can perform brightness detection, and the remaining light emitted downward from the light-emitting element can be directly irradiated to the light-emitting area.
  • the layer 261 reflects this part of the light to the light-emitting side of the light-emitting element by the reflective layer 261 for display.
  • the subsequent preparation process of the remaining structure and encapsulation layer of the light-emitting element in this embodiment is the same as that of the foregoing embodiment, and can refer to step (11) to step (14) of the foregoing embodiment.
  • This embodiment also implements a display substrate with a top emission structure, and the arrangement of the optical sensor element does not affect the pixel aperture ratio of the display substrate, thereby greatly improving the pixel aperture ratio and resolution of the display substrate, and is suitable for high PPI display.
  • the power consumption is reduced; moreover, the circuit structures in the first area A1 and the second area A2 can be prepared simultaneously, the integration is high, the preparation process flow of the display substrate is simplified, and the preparation cost is saved.
  • the structure (or method) shown in this embodiment mode can be appropriately combined with the structure (or method) shown in other embodiments.
  • FIG. 21 is an example diagram of a partial top view structure of a display substrate provided by an embodiment of the disclosure.
  • the pixel driving circuit may be as shown in FIG. 4, and the light emission detection circuit may be as shown in FIG. 5.
  • the display substrate includes a plurality of scanning signal lines G1 and G2 arranged in parallel, and a plurality of data signal lines DL and a detection signal line SL arranged in parallel.
  • the lines perpendicularly intersect to define a plurality of light emitting units 31 arranged regularly.
  • Each pixel of the display substrate provided in this embodiment may include four light-emitting units (sub-pixels); for example, the four light-emitting units may be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.
  • One pixel unit may include three light-emitting units, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • the light emitted by the first column of light-emitting units from the left is red light
  • the corresponding data signal line is DL(R)
  • the light emitted by the second column of light-emitting units is green light
  • the corresponding data signal line is DL(G)
  • the light emitted by the third column of light-emitting units is blue light
  • the corresponding data signal line is DL(B)
  • the light emitted by the fourth column of light-emitting units is white light
  • the corresponding data signal line is DL(W).
  • the main structure of the display substrate includes: a light-emitting area B1 and a light detection area B2, and the light-emitting area B1 and the light detection area B2 partially overlap.
  • the light-emitting area B1 may include a plurality of light-emitting units 31 distributed in an array.
  • the multiple light-emitting units 31 are configured to emit light from a side away from the substrate to realize display.
  • Each light-emitting unit 31 includes a pixel driving circuit 310 and a light-emitting element; a light detection area B2 includes a light detecting unit 32 configured to detect the intensity of the light emitted by the light emitting unit 31, so as to perform brightness compensation on the light emitting unit 31 according to the detected brightness signal.
  • the eight light-emitting units 31 arranged in an array (arranged according to the rule of two rows and four columns) multiplex a light detection unit 32, and the orthographic projections of the optical sensing elements of the light detection unit 32 on the substrate are respectively The orthographic projections of the light-transmitting areas of the light-emitting elements of the eight light-emitting units 31 overlap on the substrate.
  • one optical sensor element can receive the light emitted by the eight light-emitting elements, so as to realize the Perform brightness detection and optical compensation.
  • FIG. 21 the eight light-emitting units 31 arranged in an array (arranged according to the rule of two rows and four columns) multiplex a light detection unit 32, and the orthographic projections of the optical sensing elements of the light detection unit 32 on the substrate are respectively The orthographic projections of the light-transmitting areas of the light-emitting elements of the eight light-emitting units 31 overlap on the substrate.
  • one optical sensor element can receive the light emitted by the eight light-emitting elements, so
  • the overlap area between the orthographic projection of the light-transmitting area of a light-emitting element on the substrate and the orthographic projection of the optical sensor element of the light detection unit 32 on the substrate is the light-sensing effect of the optical sensor element on the light-emitting element.
  • the size of the photosensitive area 320 of the light detecting unit 32 to the eight light emitting units 31 may be the same. However, this disclosure is not limited to this.
  • FIG. 22 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 22, the method for preparing a display substrate provided by an embodiment of the present disclosure includes:
  • Step 101 forming a pixel driving circuit of a light-emitting unit and a light-emitting detection circuit of a light detecting unit on a substrate;
  • Step 102 forming an optical sensor element of the light detection unit on the pixel drive circuit and the light emission detection circuit, wherein the optical sensor element is coupled to the light emission detection circuit;
  • Step 103 forming a light-emitting element of the light-emitting unit on the optical sensor element, wherein the light-emitting element is coupled to the pixel driving circuit, the light-emitting element emits light from the side away from the substrate, and the light-emitting element has a side facing the optical sensor element.
  • the light-transmitting area, and the orthographic projection of the light-transmitting area on the substrate and the orthographic projection of the optical sensing element on the substrate at least partially overlap.
  • the orthographic projection of the light-transmitting area on the substrate completely overlaps the orthographic projection of the optical sensing element on the substrate.
  • the light-emitting element forming the light-emitting unit on the optical sensor element may include: sequentially forming a first anode, a light-emitting functional layer, and a first cathode that are stacked on the optical sensor element.
  • a cathode adopts a light-transmitting material
  • the first anode includes a reflective layer and a light-transmitting layer stacked on the substrate.
  • the orthographic projection of the light-transmitting layer on the substrate covers the orthographic projection of the reflective layer on the substrate. The area forms a light-transmitting area.
  • the manufacturing method of this embodiment may further include: forming a first flat layer on the light-emitting detection circuit;
  • forming the optical sensing element of the light detection unit on the pixel driving circuit and the light-emitting detection circuit may include: forming the optical sensing element on the first flat layer.
  • the preparation method of this embodiment may further include: forming a first passivation layer between the luminescence detection circuit and the first flat layer; and forming a first passivation layer between the first flat layer and the optical sensor element. Two passivation layer.
  • the preparation method of the display substrate of this embodiment also realizes the display substrate of the top emission structure, and the arrangement of the optical sensor element does not affect the pixel aperture ratio of the display substrate, thereby greatly improving the pixel aperture ratio and resolution of the display substrate. It is suitable for high PPI display, reducing power consumption; moreover, the pixel driving circuit and the light-emitting detection circuit can be prepared simultaneously, and the integration is high, which simplifies the preparation process of the display substrate and saves the preparation cost.
  • the embodiment of the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Sustainable Development (AREA)
  • Inorganic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括：基底以及位于基底上的多个发光单元和多个光检测单元；至少一个发光单元包括：发光元件以及与发光元件耦接的像素驱动电路，至少一个光检测单元包括：光学传感元件以及与光学传感元件耦接的发光检测电路；光学传感元件位于发光检测电路和像素驱动电路远离基底的一侧，且位于发光元件与基底之间；发光元件从远离基底的一侧出光，发光元件在面对光学传感元件的一侧具有透光区域，且透光区域在基底上的正投影与光学传感元件在基底上的正投影至少部分交叠。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年3月20日提交中国专利局、申请号为202010205098.X、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light-Emitting Device)显示器具备低能耗、自发光、温度特性好、响应快、可弯曲、超轻薄和成本低等优点，被广泛应用在手机、平板电脑、数码相机等显示领域，受到越来越多的关注。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种显示基板及其制备方法、显示装置。
一方面，本公开提供一种显示基板，包括：基底以及位于所述基底上的多个发光单元和多个光检测单元；至少一个发光单元包括：发光元件以及与所述发光元件耦接的像素驱动电路，至少一个光检测单元包括：光学传感元件以及与所述光学传感元件耦接的发光检测电路；所述光学传感元件位于所述发光检测电路和所述像素驱动电路远离所述基底的一侧，且位于所述发光元件与所述基底之间；所述发光元件从远离所述基底的一侧出光，所述发光元件在面对所述光学传感元件的一侧具有透光区域，且所述透光区域在所述基底上的正投影与所述光学传感元件在所述基底上的正投影至少部分交叠。
另一方面，本公开提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开提供一种显示基板的制备方法，包括：在基底上形成发光单元的像素驱动电路和光检测单元的发光检测电路；在所述像素驱动电路和发光检测电路上形成光检测单元的光学传感元件，其中，所述光学传感元件与所述发光检测电路耦接；在所述光学传感元件上形成所述发光单元的发光元件，其中，所述发光元件与所述像素驱动电路耦接，所述发光元件从远离所述基底的一侧出光，所述发光元件在面对所述光学传感元件的一侧具有透光区域，且所述透光区域在所述基底上的正投影与所述光学传感元件在所述基底上的正投影至少部分交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种底发射OLED显示基板的结构示意图；
图2为本公开一实施例提供的显示基板的结构示意图；
图3为本公开一实施例提供的显示基板的局部剖视结构示例图；
图4为本公开一实施例中的像素驱动电路的结构示例图；
图5为本公开一实施例中的发光检测电路的结构示例图；
图6为本公开一实施例的显示基板的工作时序图；
图7为本公开一实施例形成遮挡层图案后的示意图；
图8为本公开一实施例形成有源层图案后的示意图；
图9为本公开一实施例形成栅电极图案后的示意图；
图10为本公开一实施例形成第三绝缘层图案后的示意图；
图11为本公开一实施例形成源电极和漏电极图案后的示意图；
图12为本公开一实施例形成第五绝缘层图案后的示意图；
图13为本公开一实施例形成连接电极和光学传感元件的第二阴极图案 后的示意图；
图14为本公开一实施例形成光学传感元件的第二阳极图案后的示意图；
图15为本公开一实施例形成第二平坦层图案后的示意图；
图16为本公开一实施例形成发光元件的第一阳极图案后的示意图；
图17为本公开一实施例形成像素定义层图案后的示意图；
图18为本公开一实施例形成发光元件的第一阴极后的示意图；
图19为本公开一实施例提供的第一平坦层对暗态电流的影响示意图；
图20为本公开另一实施例提供的显示基板的局部剖视结构示例图；
图21为本公开另一实施例提供的显示基板的局部俯视结构示例图；
图22为本公开一实施例提供的显示基板的制备方法的流程图。
附图标记说明：
10，20-基底；12-电路结构；14，24，DP-光学传感元件；16，26，EL-发光元件；17，27-盖板；21，310-像素驱动电路；22-发光检测电路；31-发光单元；32-光检测单元；320-感光区域；210-遮挡层；211-第一绝缘层；212-第一有源层；213-第二有源层；214-第二绝缘层；215-第一栅电极；216-第二栅电极；217-第三绝缘层；218-第二漏电极；219-第二源电极；220-第一漏电极；221-第一源电极；222-第二连接电极；223-第一连接电极；231-第四绝缘层；232-第一平坦层；233-第五绝缘层；241-第二阴极；242-光电转换结构；243-第二阳极；244-第三连接电极；251-第六绝缘层；252-第二平坦层；261-反射层；262-透光层；263-像素定义层；264-发光功能层；265-第一阴极；V11，V12，V13，V14-第一过孔；V21，V22，V23-第二过孔；V3-第三过孔；V4-第四过孔；KA-开口区域；A1-第一区域；A2-第二区域；B1-发光区域；B2-光检测区域；M1-驱动晶体管；M2-第一开关晶体管；M3-第二开关晶体管；M4-第三开关晶体管；C1-第一存储电容；C2-第二存储电容；DL-数据信号线；G1-第一扫描信号线；G2-第二扫描信号线；SL-检测信号线；VDD-第一电源线；VSS-第二电源线；V1-第一参考信号线；V2-第二参考信号线。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的独特的技术方案。因此，应当理解，在本公开中示出或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行一种或多种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
下面参照附图对实施方式进行说明。其中，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为不同形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。
在附图中，有时为了明确起见，夸大表示了每个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中每个 部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。在本公开中，“多个”表示两个或两个以上的数目。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“电性的连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本公开中，例如当导电性充分低时，有时“半导体”具有“绝缘体”的特性。此外，由于“半导体”和“绝缘体”的边界不太清晰，因此有时不 能精确地区别“半导体”和“绝缘体”。由此，有时可以将本公开中的“半导体”换成为“绝缘体”。同样地，有时可以将本公开中的“绝缘体”换成为“半导体”。另外，有时可以将本公开中的“绝缘体”换成为“半绝缘体”。
在本公开中，例如当导电性充分高时，有时“半导体”具有“导电体”的特性。此外，由于“半导体”和“导电体”的边界不太其清晰，因此有时不能精确地区别“半导体”和“导电体”。由此，有时可以将本公开中的“半导体”换成为“导电体”。同样地，有时可以将本公开中的“导电体”换成为“半导体”。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本公开中，沟道区域是指电流主要流过的区域。
在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
本领域技术人员可以理解，本公开所有实施例中采用的开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。示例性地，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，控制极为栅极，为区分开关晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。
OLED亮度补偿方式可以分为电学补偿和光学补偿。电学补偿可以补偿阈值电压以及迁移率变化，光学补偿不区分引起亮度变化的原因，可以对更多引起亮度不均匀的因素进行补偿。在光学补偿方式中，发光检测电路可以通过光学传感元件检测OLED器件的亮度信号，以根据亮度信号对OLED器件进行亮度补偿。目前采用光学补偿方式的OLED显示基板均采用底发射结构。
图1为一种底发射OLED显示基板的结构示意图。如图1所示，电路结构12、光学传感元件14以及发光元件16设置在基底10上，且均位于盖板17下；发光元件16从基底10一侧出光；其中，电路结构12包括耦接发光元件16的像素驱动电路和耦接光学传感元件14的发光检测电路。由图1可见，电路结构12需占据发光元件16的一部分开口区域，会限制底发射OLED显示基板的像素开口率和分辨率(PPI，Pixels Per Inch)；而且，光学传感元件14需要接收发光元件16发出的光，光学传感元件14的收光区域会另外占据发光元件16的一部分开口区域，从而进一步限制底发射OLED显示基板的像素开口率和分辨率。
本公开实施例提供一种显示基板及其制备方法、显示装置，通过设计顶发射结构的显示基板来实现光学补偿，可以大大提升显示基板的像素开口率和分辨率。
本实施例提供一种显示基板，包括：基底以及位于基底上的多个发光单元和多个光检测单元，至少一个发光单元包括发光元件以及与发光元件耦接的像素驱动电路，至少一个光检测单元包括光学传感元件以及与光学传感元件耦接的发光检测电路；其中，光学传感元件位于发光检测电路和像素驱动电路远离基底的一侧，且位于发光元件与基底之间；发光元件从远离基底的一侧出光，发光元件在面对光学传感元件的一侧具有透光区域，且透光区域在基底上的正投影与光学传感元件在基底上的正投影至少部分交叠。
图2为本公开一实施例提供的显示基板的结构示意图。如图2所示，像素驱动电路21和发光检测电路22设置在基底20上，光学传感元件24位于像素驱动电路21和发光检测电路22远离基底20的一侧，发光元件26位于光学传感元件24的上方，盖板27位于发光元件26的上方；发光元件26从远离基板20的一侧出光，发光元件26在面对光学传感元件24的一侧具有透光区域，且透光区域在基底上的正投影与光学传感元件24在基底20上的正投影至少部分交叠。如此一来，位于发光元件26下方的光学传感元件24可以接收到发光元件26发出的光，以便发光检测电路22通过光学传感元件24检测发光元件26的亮度信号，并根据亮度信号对发光元件26进行亮度补偿。
如图2所示，发光元件26向上发光(即向远离基板20一侧出光)，实 现显示，发光元件26向下(即面对基板20一侧)发出的光一部分可以提供给光学传感元件24，以便光学传感元件24进行发光亮度探测，其余光可以直接反射回发光元件26的上表面用于显示。
本实施例提供的顶发射结构的显示基板，可以大大提升像素开口率和分辨率，以支持得到更好的显示效果。
在一示例性实施方式中，透光区域在基底上的正投影与光学传感元件在基底上的正投影完全交叠。
在一示例性实施方式中，发光元件可以包括：沿远离基底的方向依次层叠设置的第一阳极、发光功能层和第一阴极；第一阴极采用透光材料；第一阳极包括反射层和透光层，其中，透光区域由透光层和反射层形成。其中，透光层在基底上的正投影与光学传感元件在基底上的正投影至少部分交叠，交叠区域为光学传感元件对发光元件的感光区域。本示例性实施方式中，通过对发光元件的阳极图形化，在发光元件的第一阳极对应光学传感元件的区域实现透光设计，使得发光元件面对光学传感元件一侧的部分区域透光，以便光学传感元件可以接收到发光元件发出的光，而且不会占用发光单元的开口区域。
在一示例性实施方式中，透光层在基底上的正投影覆盖反射层在基底上的正投影，透光层中未被反射层遮挡的区域形成透光区域。然而，本公开对此并不限定。比如，透光层在基底上的正投影与反射层在基底上的正投影可以仅部分交叠。
在一示例性实施方式中，透光层可以位于反射层远离基底的一侧，或者，反射层可以位于透光层远离基底的一侧。然而，本公开对此并不限定。
在一示例性实施方式中，光学传感元件可以包括：沿远离基底的方向依次层叠设置的第二阴极、光电转换结构以及第二阳极；其中，第二阴极采用遮光材料，第二阳极采用透光材料。在一示例中，光学传感元件可以为PIN型光电二极管。然而，本公开对此并不限定。
在一示例性实施方式中，显示基板还可以包括：第一平坦层，第一平坦层位于光学传感元件和发光检测电路之间。本示例性实施方式中，通过在光 学传感元件的下方设置第一平坦层，可以保证光学传感元件在底部高段差基础上的可用性。
在一示例性实施方式中，显示基板还可以包括：第一钝化层和第二钝化层，第一钝化层位于发光检测电路与第一平坦层之间，第二钝化层位于第一平坦层与光学传感元件之间。本示例性实施方式中，通过在第一平坦层的两侧设置钝化层，可以阻挡第一平坦层对其他膜层和结构的影响。
在一示例性实施方式中，发光单元与光检测单元可以为一一对应关系，或者，发光单元与光检测单元可以为多对一的对应关系。其中，一个发光单元可以通过一个光检测单元进行光学补偿，或者，多个发光单元可以复用一个光检测单元进行光学补偿。
下面通过示例详细说明本公开实施例的技术方案。
图3为本公开一实施例提供的显示基板的局部剖视结构示例图。如图3所示，在垂直于显示基板的平面上，至少一个发光单元包括依次设置在基底20上的像素驱动电路和发光元件，其中，像素驱动电路包括多个薄膜晶体管，可以是2T1C、3T1C或7T1C设计，图3中仅以一个发光元件和一个薄膜晶体管为例进行示意；至少一个光检测单元包括依次设置在基底20上的发光检测电路和光学传感元件。在图3中，发光检测电路和光学传感元件位于左侧的第一区域A1，像素驱动电路位于右侧的第二区域A2；其中，发光检测电路和像素驱动电路同步制备形成。
在本实施例中，像素驱动电路可以采用3T1C设计，发光检测电路可以采用1T1C设计。然而，本公开对此并不限定。
图4为本公开一实施例中的像素驱动电路的结构示例图。如图4所示，本实施例中的像素驱动电路可以包括：驱动晶体管M1、第一开关晶体管M2、第二开关晶体管M3以及第一存储电容C1。其中，第一开关晶体管M2的控制极与第一扫描信号线G1耦接，第一开关晶体管M2的第一极与数据信号线DL耦接，第一开关晶体管M2的第二极与驱动晶体管M1的控制极耦接；驱动晶体管M1的第一极与第一电源线VDD耦接，驱动晶体管M1的第二极与发光元件EL的第一阳极耦接；发光元件EL的第一阴极与第二电源端VSS耦接；第二开关晶体管M3的控制极与第一扫描信号线G1耦接，第二开关 晶体管M3的第一极与第一参考信号线V1耦接，第二开关晶体管M3的第二极与驱动晶体管M1的第二极耦接；第一存储电容C1的第一电极与驱动晶体管M1的控制极耦接，第一存储电容C1的第二电极与驱动晶体管M1的第二极耦接。
图5为本公开一实施例中的发光检测电路的结构示例图。如图5所示，发光检测电路包括：第三开关晶体管M4和第二存储电容C2。其中，第三开关晶体管M4的控制极与第二扫描信号线G2耦接，第三开关晶体管M4的第一极与检测信号线SL耦接，第三开关晶体管M4的第二极与光学传感元件DP的第二阴极耦接；第二存储电容C2的第一电极与光学传感元件DP的第二阴极耦接，第二存储电容C2的第二电极与光学传感元件DP的第二阳极耦接，第二存储电容C2配置为存储光学传感元件DP转换得到的电信号；光学传感元件DP的第二阳极与第二参考信号线V2耦接。在本示例中，光学传感元件DP可以为PIN型光电二极管。然而，本公开对此并不限定。
下面以图4所示的像素驱动电路和图5所示的发光检测电路为例，说明本实施例提供的显示基板的工作过程。图6为本实施例的显示基板的工作时序图。以本实施例提供的电路中的开关晶体管M2至M4以及驱动晶体管M1均为N型晶体管为例进行说明。其中，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。然而，本公开对此并不限定。本公开实施例中的开关晶体管和驱动晶体管亦可以为P型晶体管。其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。
如图6所示，本实施例提供的显示基板可以通过以下五个工作阶段进行光学补偿。
在第一阶段T1(即复位阶段)，第三开关晶体管M4在第二扫描信号线G2的信号g2的高电平控制下导通，将光学传感元件DP的第二阴极与检测信号线SL导通，以使光学传感元件DP的第二阴极加载正电压；参考信号线V2上加载负电压(例如，-5V)，使光学传感元件DP的第二阳极加载负电压，从而光学传感元件DP工作在反偏状态。并且，第一开关晶体管M2和第二开关晶体管M3在第一扫描信号线G1的信号g1的低电平控制下截止。
在第二阶段T2(即输入写入阶段)，第一开关晶体管M2和第二开关晶 体管M3在第一扫描信号线G1的信号g1的高电平控制下导通；第一开关晶体管M2将数据信号线DL提供的信号dl(数据电压为Vdata)提供给驱动晶体管M1的控制极，使驱动晶体管M1的栅极电压为Vdata，并通过第一存储电容C1进行存储；第二开关晶体管M3将第一参考信号线V1上传输的参考电压信号(例如，0V)提供给发光元件EL，参考电压信号的电压值小于第二电源端VSS的信号的电压值，以使发光元件EL处于反偏状态。并且，第三开关晶体管M4在第二扫描信号端G2的信号g2的低电平控制下截止。
在第三阶段T3(即显示阶段)，第一开关晶体管M2和第二开关晶体管M3在第一扫描信号端G1的信号g1的低电平控制下截止，第三开关晶体管M4在第二扫描信号端G2的信号g2的低电平控制下截止。驱动晶体管M1在其栅极电压和源极电压的共同控制下产生驱动电流I，且驱动电流I满足以下式子：I＝K[Vgs-Vth] 2＝K[Vdata-Vs-Vth] 2；其中，Vs为驱动晶体管M1的源极电压，Vth表示驱动晶体管M1的阈值电压，K为与驱动晶体管M1的工艺参数和几何尺寸有关的固定常数。其中，驱动晶体管M1的源极电压Vs可以为第一参考信号线V1上传输的参考电压信号的电压值。
在本阶段，驱动晶体管M1产生的驱动电流I可以驱动发光元件EL发光，使得光学传感元件DP可以接收发光元件EL发出的光，并将接收的光转换为电流，从而使光学传感元件DP的第二阴极的电压变化。
在第四阶段T4(即显示关闭阶段)，第一开关晶体管M2和第二开关晶体管M3在第一扫描信号端G1的信号g1的高电平控制下导通；导通的第一开关晶体管M2将数据信号线DL提供的信号dl(0V的数据电压)提供给驱动晶体管M1的控制极，导通的第二开关晶体管M3将第一参考信号线V1上传输的参考电压信号(例如，0V)提供给发光元件EL，使得发光元件EL停止发光，从而保证光学传感元件PD的第二阴极的电压稳定。
在第五阶段T5(即光学检测阶段)，第三开关晶体管M4在第二扫描信号线G2的信号g2的高电平控制下导通，以将光学传感元件DP与检测信号线SL导通，从而将光学传感元件DP的第二阴极的电压传输给检测信号线SL。通过驱动集成电路(IC)获取检测信号线SL上的电压进行分析补偿计算，以提高画面显示效果。
基于图4所示的像素驱动电路，还可以通过将第二开关晶体管M3的第一极耦接一条检测信号线，来实现电学补偿。然而，本公开对此并不限定。
在本实施例中，在图3示意的第二区域A2内的薄膜晶体管可以为图4所示的像素驱动电路中的驱动晶体管M1。如图3所示，驱动晶体管M1包括：第一有源层212、第一栅电极215、第一源电极221、第一漏电极220、第一连接电极223以及第二连接电极222；发光元件包括第一阳极、像素定义层263、发光功能层264以及第一阴极265，其中，第一阳极包括反射层261和透光层262；第一阳极的反射层261与第一连接电极223耦接，第一连接电极223与驱动晶体管M1的第一源电极221耦接，以实现第一阳极与驱动晶体管M1的第一源电极221之间的耦接。
在本实施例中，在图3示意的第一区域A1内的薄膜晶体管可以为图5所示的发光检测电路中的第三开关晶体管M4。如图3所示，第三开关晶体管M4包括：第二有源层213、第二栅电极216、第二源电极219以及第二漏电极218；光学传感元件包括第二阴极241、光电转换结构242、第二阳极243以及第三连接电极244；第二阴极241与第三开关晶体管M4的第二源电极219耦接。
在本实施例中，像素驱动电路内的薄膜晶体管的结构与发光检测电路内的薄膜晶体管的结构可以相同，且通过相同的工艺同步制备。
如图3所示，发光元件从远离基板20一侧出光，且发光元件通过由透光层262和反射层261形成的透光区域向光学传感元件一侧透光，以使光学传感元件可以接收到发光元件发出的光，以进行发光亮度检测实现光学补偿。
下面通过本实施例的显示基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，可以采用已知成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。
本实施例提供的显示基板的制备过程可以包括以下步骤(1)至(14)。
(1)在基底上形成遮挡(Shield)层图案。形成遮挡层图案包括：在基底20上沉积遮挡薄膜，通过构图工艺对遮挡薄膜进行构图，在基底20上形成遮挡层210图案，如图7所示。其中，每个薄膜晶体管对应的位置可以设置遮挡层210，遮挡层210可以有效吸收和遮挡环境光。
其中，基底20可以为柔性基底，采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。
(2)形成有源(Active)层图案。形成有源层图案包括：在形成有前述图案的基底20上，依次沉积第一绝缘薄膜和有源薄膜，通过构图工艺对有源薄膜进行构图，形成覆盖遮挡层210的第一绝缘层211，以及形成在第一绝缘层211上的第一有源层212和第二有源层213，如图8所示。其中，第一有源层212作为驱动晶体管M1的有源层，第二有源层213作为第三开关晶体管M4的有源层。
其中，第一绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或者可以采用高介电常数(High k)材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第一绝缘层211称之为缓冲(Buffer)层。
其中，有源薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本实施例适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的基于顶栅(Top Gate)薄膜晶体管(TFT，Thin Film Transistor)的显示基板。
(3)形成栅电极图案。形成栅电极图案包括：在形成上述结构的基底20上，依次沉积第二绝缘薄膜和第一金属薄膜，先在第一金属薄膜上涂覆一层光刻胶，通过掩模、曝光和显影形成光刻胶图案，利用刻蚀工艺刻蚀第一金属薄膜后，利用第一金属薄膜作为掩模自对准向下刻蚀第二绝缘薄膜，形成第二绝缘层214图案、以及设置在第二绝缘层214上的第一栅电极215、第二栅电极216以及扫描信号线(图未示)图案，如图9所示。
其中，第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝钕合金(AlNd)、钼铌合金(MoNb) 等，可以是多层金属，如Mo/Cu/Mo等，或者可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
其中，第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或者可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第二绝缘层214称之为栅绝缘(GI)层。
(4)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成有前述图案的基底20上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层217图案；第三绝缘层217上开设有多个过孔，分别为暴露出第一有源层212两端的第一过孔V11和V12，暴露出第二有源层213两端的第一过孔V13和V14，如图10所示。
其中，第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或者可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第三绝缘层217称之为层间绝缘(ILD)层。
(5)形成源(Source)电极和漏(Drain)电极图案。形成源电极和漏电极图案，包括：在形成上述结构的基底20上，沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，在第三绝缘层217上形成电源线(图未示出)、数据信号线(图未示出)、参考信号线(图未示出)、第一源电极221、第一漏电极220、第二源电极219和第二漏电极218图案，如图11所示。
其中，第二金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝钕合金(AlNd)、钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等，或者可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
(6)形成第四绝缘层、第一平坦层和第五绝缘层图案。形成第四绝缘层、第一平坦层和第五绝缘层图案，包括：在形成有前述图案的基底20上，在第一区域A1和第二区域A2先沉积第四绝缘薄膜，形成覆盖前述结构的第四绝缘层231，然后在第一区域A1涂覆第一平坦化薄膜，通过掩膜曝光显影的光刻工艺在第一区域A1形成覆盖前述结构的第一平坦层232，然后在第一区域 A1和第二区域A2沉积第五绝缘薄膜，形成覆盖前述结构的第五绝缘层233图案；第五绝缘层233上形成有第二过孔V21、V22和V23；其中，第二过孔V21位于第二源电极219的位置，第二过孔V21内的第四绝缘层231、第一平坦层232和第五绝缘层233被去掉，暴露出第二源电极219的表面；第二过孔V22位于第一栅电极215的位置，第二过孔V22内的第五绝缘层233、第四绝缘层231和第三绝缘层217被去掉，暴露出第一栅电极215的表面；第二过孔V23位于第一源电极221的位置，第二过孔V23内的第五绝缘层233和第四绝缘层231被去掉，暴露出第一源电极221的表面，如图12所示。
其中，第四绝缘薄膜和第五绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或者可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。
其中，第一平坦化薄膜的材料包含但不限于聚硅氧烷系材料、亚克力系材料或聚酰亚胺系材料等。
通常，第四绝缘层231和第五绝缘层233称之为钝化(PVX，Passivation)层，第四绝缘层231即为前述的第一钝化层，第五绝缘层233即为前述的第二钝化层。通过设置第四绝缘层231和第五绝缘层233可以阻挡第一平坦层232对其他膜层及结构的影响。
(7)形成连接电极和光学传感元件的第二阴极图案。形成连接电极和光学传感元件的第二阴极图案，包括：在形成有前述图案的基底20上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第一连接电极223、第二连接电极222和光学传感元件的第二阴极241图案，如图13所示。其中，第一连接电极223通过第二过孔V23与第一源电极221耦接，第二连接电极222通过第二过孔V22与第一栅电极215耦接，第二阴极241通过第二过孔V21与第二源电极219耦接。
其中，第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝钕合金(AlNd)、钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等，或者可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
通过步骤(1)至(7)的制备过程，即可在基底20上完成位于第一区域A1的薄膜晶体管和位于第二区域A2的薄膜晶体管的同步制备。其中，位于第二区域A2的驱动晶体管M1可以包括：第一有源层212、第一栅电极215、第一源电极221、第一漏电极220、第一连接电极223和第二连接电极222。位于第一区域A1的第三开关晶体管M4可以包括：第二有源层213、第二栅电极216、第二源电极219和第二漏电极218。
在第一区域A1内的发光检测电路中，光学传感元件的第二阴极241可以复用作为与其耦接的第二存储电容C2的第一电极，第二存储电容C2的第二电极可以与第三开关晶体管M4的第二源电极219和第二漏电极218同层同材料制备。在本实施例中，可以避免增加专门用于制作第二存储电容C2的第一电极和第二电极的工艺流程，可以简化显示基板的制作工艺流程，并节约显示基板的制作成本。然而，本公开对此并不限定。第二存储电容的布局方式可以根据实际需要确定。
在本实施例中，第一有源层212和第二有源层213同层设置，且通过同一次构图工艺同时形成；第一栅电极215和第二栅电极216同层设置，且通过同一次构图工艺同时形成；第一源电极221、第一漏电极220、第二源电极219、第二漏电极218以及第二存储电容的第一电极同层设置，且通过同一次构图工艺同时形成；第一连接电极223、第二连接电极222与第二存储电容的第二电极同层设置，并通过同一次构图工艺同时形成。
(8)形成光学传感元件的光电转换结构和第二阳极图案。形成光学传感元件的光电转换结构和第二阳极图案，包括：在第一区域A1内，在第二阴极241上形成光电转化结构242，在光电转换结构242上沉积第一透明导电薄膜，通过构图工艺对第一透明导电薄膜进行构图，形成第二阳极243图案，如图14所示。
在本实施例中，光学传感元件可以为PIN型光电二极管；其中，光电转换结构242包括：PN结和在该PN结中间掺入的一层浓度很低的I型半导体；由于掺入的I型半导体浓度低，近乎本征(Intrinsic)半导体，因此，也可称为I层，在I层两侧是掺杂浓度很高的P型半导体和N型半导体，即形成P层和N层，P层和N层很薄，吸收入射光的比例很小，使得绝大部分的入射 光在I层内被吸收并产生大量的电子-空穴对，而I层较厚，几乎占据了整个耗尽区，从而可实现通过增大耗尽区的宽度，达到减小扩散运动的影响，提高光电二极管响应速度。
其中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
(9)形成第六绝缘层和第二平坦层图案。形成第六绝缘层和第二平坦层图案，包括：形成有前述图案的基底20上，先沉积第六绝缘薄膜，形成覆盖前述结构的第六绝缘层251，然后涂覆第二平坦化薄膜，利用第二平坦化薄膜作为光刻胶，通过掩膜、曝光和显影，对第六绝缘层251进行刻蚀，形成覆盖前述结构的第二平坦层252图案；其中，第二平坦层252上形成有第三过孔V3和第四过孔V4，第三过孔V3位于第二阳极243的位置，第三过孔V3内的第六绝缘层251和第二平坦层252被去掉，暴露出第二阳极243的表面；第四过孔V4位于第一连接电极223的位置，第四过孔V4内的第六绝缘层251和第二平坦层252被去掉，暴露出第一连接电极223的表面，如图15所示。
其中，第六绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或者可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第六绝缘层可以称之为钝化(PVX)层。
其中，第二平坦化薄膜的材料包含但不限于聚硅氧烷系材料、亚克力系材料或聚酰亚胺系材料等。
(10)形成第一阳极和第三连接电极图案。形成第一阳极和第三连接电极图案，包括：在形成前述图案的基底20上沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，形成反射层261图案；然后，在形成前述结构的基底20上沉积第二透明导电薄膜，通过构图工艺对第二透明导电薄膜进行构图，形成透光层262和第三连接电极244图案，如图16所示。其中，第三连接电极244位于第一区域A1，第三连接电极244通过第三过孔V3与光学传感元件的第二阳极243耦接，第三连接电极244还可以耦接第二参考信号线V2，以实现第二阳极243与第二参考信号线V2之间的耦接。反射层261 通过第四过孔V4与第一连接电极223耦接，以实现发光元件的第一阳极与驱动晶体管M1的第一源电极221之间的耦接。
其中，透光层262和反射层261均为导电材料，可以向发光元件的发光功能层传输驱动晶体管M1的第一源电极221提供的驱动电流。
本实施例中，透光层262位于反射层261之上，透光层262在基底20上的正投影覆盖反射层261在基底20上的正投影；透光层262在基底20上的正投影与光学传感元件的光电转换结构242在基底20上的正投影部分交叠，即透光层262在基底20上的正投影与光学传感元件的感光区域的正投影部分交叠。其中，发光元件的透光区域由透光层262中未被反射层261遮挡的区域形成。如此一来，发光元件向下发出的一部分光可以通过透光层262照射到光学传感元件的感光区域，以便光学传感元件进行发光亮度检测，发光元件向下发出的其余光可以通过透光层262照射到发射层261，由反射层261将这部分光反射到发光元件的出光侧，用于显示。然而，本公开对此并不限定。在其他实现方式中，发光元件的透光区域可以由未被反射层遮挡的透光层形成，此时，透光层可以不覆盖反射层，则发光元件向下发出的一部分光可以通过透光层照射到光学传感元件的感光区域，以便光学传感元件进行亮度检测，发光元件向下发出的其余光可以直接照射到发射层，由反射层将这部分光反射到发光元件的出光侧，用于显示。
其中，第四金属薄膜可以采用金属材料，如镁(Mg)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、锂(Li)等，或上述金属的合金材料，如铝铌合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，或者可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO、Mo/AlNd/ITO等反射型材料。
其中，第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
通过步骤(7)至步骤(10)的制备过程，即完成了光学传感元件的制备，其中，位于第一区域A1的光学传感元件包括：第二阴极241、光电转换结构242、第二阳极243和第三连接电极244。其中，第三连接电极244与发光元件的第一阳极的透光层262同层设置，通过同一次构图工艺同时形成。
(11)形成像素定义层(Pixel Define Layer)图案。形成像素定义层图案，包括：在形成前述图案的基底20上涂覆像素定义薄膜，通过掩膜曝光和显影形成像素定义层263图案，限定出暴露第一阳极的透光层262的开口区域KA，如图17所示。
其中，像素定义薄膜可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等材料。
(12)形成发光功能层图案。形成发光功能层图案，包括：在形成前述图案的基底20上，采用蒸镀或喷墨打印方式，在开口区域KA内形成发光功能层264图案，发光功能层264与第一阳极的透光层262耦接，如图18所示。
其中，发光功能层264包括发光材料层(EML，Emitting Layer)。在实际实施时，发光功能层264可以包括依次设置的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层，以提高电子和空穴注入发光层的效率。
(13)形成发光元件的第一阴极图案。形成发光元件的第一阴极图案包括：在形成前述图案的基底20上，采用蒸镀方式形成发光元件的第一阴极265，第一阴极265与发光功能层264耦接，如图18所示。
其中，第一阴极265的材料可以为氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。发光元件可以通过透明的第一阴极265从远离基底20一侧出光，实现顶发射。
通过步骤(10)至步骤(13)的制备过程，即完成了发光元件的制备，其中，发光元件包括第一阳极(反射层261和透光层262)、像素定义层263、发光功能层264以及第一阴极265。
(14)形成封装层图案。其中，封装层可以为无机/有机/无机的三层结构，以完成显示基板的封装。
通过本实施例的显示基板的结构及制备过程可以看出，本实施例通过在基底上同步制备第一区域A1和第二区域A2内的电路结构，然后，在第一区域A1制备光学传感元件，在第一区域A1和第二区域A2制备发光元件，实现顶发射结构的显示基板，且光学传感元件的设置不会影响显示基板的像素 开口率，从而可以大大提升显示基板的像素开口率和分辨率，适用于高PPI显示，降低了功耗；而且，第一区域A1和第二区域A2内的电路结构可以同步制备，集成度高，简化了显示基板的制备工艺流程，节约了制备成本。
本实施例中，光学传感元件的底部设置有第一平坦层，可以保证底部高段差基础上光学传感元件的可用性。以光学传感元件为PIN型光电二极管为例，当PIN型光电二极管底部段差较大时，会造成暗态电流较高。图19为本公开一实施例提供的第一平坦层对暗态电流的影响示意图。在图19中，实线表示PIN型光电二极管下方有第一平坦层和图案(即底部有段差)的情况，虚线表示PIN型光电二极管下方没有第一平坦层且下方有图案的情况，点划线表示PIN型光电二极管下方没有第一平坦层且下方也没有图案的情况。如图19可见，当PIN型光电二极管的下方有段差且不采用第一平坦层进行平坦时，PIN型光电二极管的暗态电流较大，在下方增加第一平坦层后，PIN型光电二极管的暗态电流可以降低约64％，与PIN型光电二极管的下方无段差情况达到相当水平。根据图19可见，在PIN型光电二极管的下方设置第一平坦层，可以保证底部高段差情况下PIN型光电二极管的特性可用，避免影响PIN型光电二极管检测到的亮度信号的准确性，从而确保光学补偿的准确性和效果。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图20为本公开另一实施例提供的显示基板的局部剖视结构示例图。本实施例提供的显示基板的主体结构与图3所述实施例基本相同，所不同的是，本实施例中显示基板的发光元件的第一阳极的结构和制备方式有所不同。
在本实施例中，制备像素驱动电路、发光检测电路和光学传感元件的第二阴极、光电转换结构以及第二阳极的过程与前述实施例相同，可以参见前述实施例的步骤(1)至步骤(9)。
步骤(10)、形成第一阳极和第三连接电极图案。形成第一阳极和第三连接电极图案，包括：在形成前述图案的基底20上依次沉积透明导电薄膜、金属薄膜和透明导电薄膜，通过构图工艺对顶层的透明导电薄膜和金属薄膜进行刻蚀，形成反射层261图案，然后对底层的透明导电薄膜进行刻蚀，形 成透光层262和第三连接电极244图案，如图20所示。
本实施例中，反射层261位于透光层262之上，透光层262在基底20上的正投影覆盖反射层261在基底20上的正投影；透光层262在基底20上的正投影与光学传感元件的光电转换结构242在基底20上的正投影部分交叠，即透光层262在基底20上的正投影与光学传感元件的感光区域的正投影部分交叠。其中，发光元件的透光区域由透光层262中未被反射层261遮挡的区域形成。如此一来，发光元件向下发出的一部分光可以通过透光层262照射到光学传感元件的感光区域，以便光学传感元件进行亮度检测，发光元件向下发出的其余光可以直接照射到发射层261，由反射层261将这部分光反射到发光元件的出光侧，用于显示。
本实施例中，金属薄膜可以采用金属材料，如镁(Mg)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、锂(Li)等，或上述金属的合金材料，如铝铌合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，或者是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO、Mo/AlNd/ITO等反射型材料。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
本实施例后续制备发光元件的其余结构和封装层的过程与前述实施例相同，可以参见前述实施例的步骤(11)至步骤(14)。
本实施例同样实现了顶发射结构的显示基板，且光学传感元件的设置不会影响显示基板的像素开口率，从而可以大大提升显示基板的像素开口率和分辨率，适用于高PPI显示，降低了功耗；而且，第一区域A1和第二区域A2内的电路结构可以同步制备，集成度高，简化了显示基板的制备工艺流程，节约了制备成本。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图21为公开一实施例提供的显示基板的局部俯视结构示例图。在本实施例中，像素驱动电路可以如图4所示，发光检测电路可以如图5所示。
如图21所示，显示基板包括多条平行设置的扫描信号线G1和G2以及 多条平行设置的数据信号线DL和检测信号线SL，多条扫描信号线与多条数据信号线和检测信号线垂直交叉限定出规则排布的多个发光单元31。本实施例提供的显示基板的每个像素可以包括四个发光单元(子像素)；示例性地，四个发光单元可以分别为红色子像素、绿色子像素、蓝色子像素以及白色子像素。然而，本公开对此并不限定。一个像素单元可以包括三个发光单元，比如，红色子像素、绿色子像素和蓝色子像素。
如图21所示，从左边起第一列发光单元发出的光为红光，对应的数据信号线为DL(R)，第二列发光单元发出的光为绿光，对应的数据信号线为DL(G)，第三列发光单元发出的光为蓝光，对应的数据信号线为DL(B)，第四列发光单元发出的光为白光，对应的数据信号线为DL(W)。
如图21所示，在平行于显示基板的平面上，显示基板的主体结构包括：发光区域B1和光检测区域B2，且发光区域B1和光检测区域B2部分重叠。发光区域B1可以包括呈阵列分布的多个发光单元31，多个发光单元31配置为从远离基底一侧发光，以实现显示，每个发光单元31包括像素驱动电路310和发光元件；光检测区域B2包括光检测单元32，光检测单元32配置为对发光单元31发出的光的强度进行检测，以根据检测到的亮度信号对发光单元31进行亮度补偿。
如图21所示，阵列排布的八个发光单元31(按照两行四列规则排布)复用一个光检测单元32，光检测单元32的光学传感元件在基底上的正投影分别与八个发光单元31的发光元件的透光区域在基底上的正投影交叠，如此一来，一个光学传感元件可以分别接收到八个发光元件所发出的光，从而实现对每个发光元件进行亮度检测和光学补偿。如图21所示，一个发光元件的透光区域在基底上的正投影与光检测单元32的光学传感元件在基底上的正投影的交叠区域为光学传感元件对该发光元件的感光区域320。光检测单元32对八个发光单元31的感光区域320的大小可以相同。然而，本公开对此并不限定。
本实施例中，多个发光单元可以复用同一个光检测单元，使得显示基板中，光检测单元占用的面积进一步缩小，从而更有利于提升显示基板的像素开口率；而且，还可以减少显示基板中光学传感元件的数目，从而进一步减 少发光检测电路的暗态电流。
图22为本公开一实施例提供的显示基板的制备方法的流程图。如图22所示，本公开实施例提供的显示基板的制备方法，包括：
步骤101、在基底上形成发光单元的像素驱动电路和光检测单元的发光检测电路；
步骤102、在像素驱动电路和发光检测电路上形成光检测单元的光学传感元件，其中，光学传感元件与发光检测电路耦接；
步骤103、在光学传感元件上形成发光单元的发光元件，其中，发光元件与像素驱动电路耦接，发光元件从远离基底的一侧出光，发光元件在面对光学传感元件的一侧具有透光区域，且透光区域在基底上的正投影与光学传感元件在基底上的正投影至少部分交叠。
在一示例性实施方式中，透光区域在基底上的正投影与光学传感元件在基底上的正投影完全交叠。
在一示例性实施方式中，在光学传感元件上形成发光单元的发光元件，可以包括：在光学传感元件上依次形成层叠设置的第一阳极、发光功能层和第一阴极，其中，第一阴极采用透光材料，第一阳极包括层叠设置的反射层和透光层，透光层在基底上的正投影覆盖反射层在基底上的正投影，透光层中未被反射层遮挡的区域形成透光区域。
在一示例性实施方式中，在基底上形成发光单元的像素驱动电路和光检测单元的发光检测电路之后，本实施例的制备方法还可以包括：在发光检测电路上形成第一平坦层；
其中，在像素驱动电路和发光检测电路上形成光检测单元的光学传感元件，可以包括：在第一平坦层上形成光学传感元件。
在一示例性实施方式中，本实施例的制备方法还可以包括：在发光检测电路与第一平坦层之间形成第一钝化层；在第一平坦层与光学传感元件之间形成第二钝化层。
有关显示基板的制备过程，已在之前的实施例中详细说明，这里不再赘述。
本实施例的显示基板的制备方法同样实现了顶发射结构的显示基板，且光学传感元件的设置不会影响显示基板的像素开口率，从而可以大大提升显示基板的像素开口率和分辨率，适用于高PPI显示，降低了功耗；而且，像素驱动电路和发光检测电路可以同步制备，集成度高，简化了显示基板的制备工艺流程，节约了制备成本。
本公开实施例还提供一种显示装置，包括前述的显示基板。显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种显示基板，包括：基底以及位于所述基底上的多个发光单元和多个光检测单元；至少一个发光单元包括：发光元件以及与所述发光元件耦接的像素驱动电路，至少一个光检测单元包括：光学传感元件以及与所述光学传感元件耦接的发光检测电路；
    所述光学传感元件位于所述发光检测电路和所述像素驱动电路远离所述基底的一侧，且位于所述发光元件与所述基底之间；所述发光元件从远离所述基底的一侧出光，所述发光元件在面对所述光学传感元件的一侧具有透光区域，且所述透光区域在所述基底上的正投影与所述光学传感元件在所述基底上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其中，所述透光区域在所述基底上的正投影与所述光学传感元件在所述基底上的正投影完全交叠。
  3. 根据权利要求1所述的显示基板，其中，所述发光元件包括：沿远离所述基底的方向依次层叠设置的第一阳极、发光功能层和第一阴极；所述第一阴极采用透光材料；所述第一阳极包括反射层和透光层，所述透光区域通过所述透光层和所述反射层形成。
  4. 根据权利要求3所述的显示基板，其中，所述透光层在所述基底上的正投影覆盖所述反射层在所述基底上的正投影，所述透光层中未被所述反射层遮挡的区域形成所述透光区域。
  5. 根据权利要求3所述的显示基板，其中，所述透光层位于所述反射层远离所述基底的一侧，或者，所述反射层位于所述透光层远离所述基底的一侧。
  6. 根据权利要求1所述的显示基板，其中，所述光学传感元件，包括：沿远离所述基底的方向依次层叠设置的第二阴极、光电转换结构以及第二阳极；其中，所述第二阴极采用遮光材料，所述第二阳极采用透光材料。
  7. 根据权利要求1所述的显示基板，还包括：第一平坦层，所述第一平坦层位于所述光学传感元件和所述发光检测电路之间。
  8. 根据权利要求7所述的显示基板，还包括：第一钝化层和第二钝化层， 所述第一钝化层位于所述发光检测电路与所述第一平坦层之间，所述第二钝化层位于所述第一平坦层与所述光学传感元件之间。
  9. 根据权利要求1所述的显示基板，其中，所述发光单元与所述光检测单元为一一对应关系，或者，所述发光单元与所述光检测单元为多对一的对应关系。
  10. 根据权利要求9所述的显示基板，其中，阵列排布的八个发光单元复用一个光检测单元。
  11. 一种显示装置，包括如权利要求1至10中任一项所述的显示基板。
  12. 一种显示基板的制备方法，包括：
    在基底上形成发光单元的像素驱动电路和光检测单元的发光检测电路；
    在所述像素驱动电路和发光检测电路上形成光检测单元的光学传感元件，其中，所述光学传感元件与所述发光检测电路耦接；
    在所述光学传感元件上形成所述发光单元的发光元件，其中，所述发光元件与所述像素驱动电路耦接，所述发光元件从远离所述基底的一侧出光，所述发光元件在面对所述光学传感元件的一侧具有透光区域，且所述透光区域在所述基底上的正投影与所述光学传感元件在所述基底上的正投影至少部分交叠。
  13. 根据权利要求12所述的制备方法，其中，所述在所述光学传感元件上形成所述发光单元的发光元件，包括：
    在所述光学传感元件上依次形成层叠设置的第一阳极、发光功能层和第一阴极，其中，所述第一阴极采用透光材料，所述第一阳极包括层叠设置的反射层和透光层，所述透光层在所述基底上的正投影覆盖所述反射层在所述基底上的正投影，所述透光层中未被所述反射层遮挡的区域形成所述透光区域。
PCT/CN2020/140841 2020-03-20 2020-12-29 显示基板及其制备方法、显示装置 WO2021184907A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/416,522 US20220359635A1 (en) 2020-03-20 2020-12-29 Display Substrate and Preparation Method Thereof, and Display Apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010205098.XA CN111370458B (zh) 2020-03-20 2020-03-20 显示基板及其制备方法、显示装置
CN202010205098.X 2020-03-20

Publications (1)

Publication Number Publication Date
WO2021184907A1 true WO2021184907A1 (zh) 2021-09-23

Family

ID=71210552

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/140841 WO2021184907A1 (zh) 2020-03-20 2020-12-29 显示基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US20220359635A1 (zh)
CN (1) CN111370458B (zh)
WO (1) WO2021184907A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370458B (zh) * 2020-03-20 2023-04-28 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN111430414A (zh) * 2020-03-31 2020-07-17 京东方科技集团股份有限公司 Oled显示面板及制备方法、显示装置
CN114187870B (zh) * 2020-09-14 2023-05-09 京东方科技集团股份有限公司 光电检测电路及其驱动方法、显示装置及其制作方法
GB2610947A (en) * 2021-02-10 2023-03-22 Boe Technology Group Co Ltd Display substrate and manufacturing method therefor, and display device
CN113053966B (zh) * 2021-03-09 2023-08-22 京东方科技集团股份有限公司 显示面板、亮度补偿方法和显示装置
CN113224119B (zh) * 2021-04-28 2022-09-13 合肥京东方卓印科技有限公司 显示面板及其制造方法、显示装置
CN113345947A (zh) * 2021-05-31 2021-09-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113345946A (zh) * 2021-05-31 2021-09-03 京东方科技集团股份有限公司 一种显示基板及其制作方法、控制方法、显示装置
KR20230036485A (ko) * 2021-09-07 2023-03-14 엘지디스플레이 주식회사 표시 장치 및 그 동작 방법
CN113782557B (zh) * 2021-09-10 2024-03-08 京东方科技集团股份有限公司 一种发光基板和发光装置
WO2023050347A1 (zh) * 2021-09-30 2023-04-06 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2023097500A1 (zh) * 2021-11-30 2023-06-08 京东方科技集团股份有限公司 显示基板及其制备方法、补偿方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120267611A1 (en) * 2011-04-21 2012-10-25 Jin-Koo Chung Organic light-emitting display device
CN109065582A (zh) * 2018-08-02 2018-12-21 京东方科技集团股份有限公司 一种阵列基板及显示面板、显示装置
CN110047906A (zh) * 2019-05-21 2019-07-23 京东方科技集团股份有限公司 基于透明光电二极管的显示装置、显示面板及其制造方法
CN110164946A (zh) * 2019-06-06 2019-08-23 京东方科技集团股份有限公司 显示基板及制造方法、显示装置
CN111370458A (zh) * 2020-03-20 2020-07-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285870B (zh) * 2018-09-28 2021-01-22 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板
CN110660356B (zh) * 2019-09-30 2021-03-19 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120267611A1 (en) * 2011-04-21 2012-10-25 Jin-Koo Chung Organic light-emitting display device
CN109065582A (zh) * 2018-08-02 2018-12-21 京东方科技集团股份有限公司 一种阵列基板及显示面板、显示装置
CN110047906A (zh) * 2019-05-21 2019-07-23 京东方科技集团股份有限公司 基于透明光电二极管的显示装置、显示面板及其制造方法
CN110164946A (zh) * 2019-06-06 2019-08-23 京东方科技集团股份有限公司 显示基板及制造方法、显示装置
CN111370458A (zh) * 2020-03-20 2020-07-03 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
US20220359635A1 (en) 2022-11-10
CN111370458A (zh) 2020-07-03
CN111370458B (zh) 2023-04-28

Similar Documents

Publication Publication Date Title
WO2021184907A1 (zh) 显示基板及其制备方法、显示装置
CN112071882B (zh) 显示基板及其制备方法、显示装置
CN108877653B (zh) 像素电路、显示装置及其制造方法
US11342392B2 (en) Display panel and manufacturing method thereof
WO2020042616A1 (en) Display panel and fabricating method thereof
CN110660356B (zh) 一种显示基板及其制作方法、显示装置
US10964772B2 (en) OLED plate, display panel and display device using the same
CN109326624B (zh) 像素电路、其制造方法及显示装置
US8183769B2 (en) Organic electroluminescent display unit and method for fabricating the same
US11183542B2 (en) Display panel and method for manufacturing display panel
US20230045968A1 (en) Display substrate and display apparatus
US11877482B2 (en) Display substrate and method for manufacturing the same, driving method and display device
US11985874B2 (en) Display substrate and display device
US11637152B2 (en) Array substrate and method for manufacturing the same, and display device having photosensitive element, light emitting device and sensing transistor
CN111627963B (zh) 一种像素单元及显示面板
US10770532B2 (en) Display substrate and method for preparing the same, and display device
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
CN113345947A (zh) 显示基板及其制备方法、显示装置
US20240215332A1 (en) Display Substrate and Preparation Method thereof, and Display Apparatus
CN115497998A (zh) 显示基板及其制备方法、显示装置
JP2019129221A (ja) 表示装置および表示装置の製造方法
CN113345946A (zh) 一种显示基板及其制作方法、控制方法、显示装置
US20230180521A1 (en) Display Substrate, Preparation Method thereof, and Display Apparatus
US20220320225A1 (en) Display substrate and method for manufacturing the same, and display device
CN115735427A (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20926105

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20926105

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20926105

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20926105

Country of ref document: EP

Kind code of ref document: A1