WO2019071670A1 - N型薄膜晶体管及其制备方法、oled显示面板的制备方法 - Google Patents

N型薄膜晶体管及其制备方法、oled显示面板的制备方法 Download PDF

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WO2019071670A1
WO2019071670A1 PCT/CN2017/109118 CN2017109118W WO2019071670A1 WO 2019071670 A1 WO2019071670 A1 WO 2019071670A1 CN 2017109118 W CN2017109118 W CN 2017109118W WO 2019071670 A1 WO2019071670 A1 WO 2019071670A1
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layer
region
drain
source
gate
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PCT/CN2017/109118
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English (en)
French (fr)
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喻蕾
李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US15/740,595 priority Critical patent/US10672912B2/en
Publication of WO2019071670A1 publication Critical patent/WO2019071670A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an N-type thin film transistor, a method for fabricating the same, and a method for fabricating an OLED display panel.
  • the N+ region ie, the heavy-doped region
  • the N-region is also called LDD: light drain doping
  • the present invention provides an N-type thin film transistor, a method for fabricating the same, and a method for fabricating the OLED display panel, which can reduce leakage current of the thin film transistor and improve device characteristics of the thin film transistor.
  • the present invention provides an N-type thin film transistor, including a polysilicon layer, a gate layer, a source, and a drain from bottom to top;
  • the polysilicon layer comprises a channel region, and a source region and a drain region on both sides of the channel region, the gate layer is located above the channel region, and the gate layer is in the A projection on the polysilicon layer partially overlaps the source region and the drain region, the source region and a gate above the drain region
  • the thickness of the electrode layer is smaller than the thickness of the gate layer above the channel region
  • the source region and the drain region each comprise a heavy doped region and a light doped region connected to the heavy doped region, the light doped regions being located below the gate layer, the source a pole is located above the re-doping region of the source region and electrically connected to a re-doping region of the source region, the drain being located above the heavy doping region of the drain region and The heavy junction of the polar region is electrically connected.
  • the ions doped in the heavy-doped region and the light-doped region are all phosphorus ions.
  • a gate insulating layer is further disposed between the polysilicon layer and the gate layer;
  • a dielectric layer is further disposed on the gate insulating layer, and the dielectric layer covers the gate layer, and the dielectric layer comprises SiNx and/or SiOy, wherein x ⁇ 1, y ⁇ 1.
  • the dielectric layer is provided with two first connection holes
  • the gate insulation layer is provided with two second connection holes
  • the two first connection holes are respectively separated from the two second The connection holes are opposite
  • the two second connection holes are respectively opposite to the heavy-doped region of the source region and the heavy-doped region of the drain region;
  • the source and the drain are both disposed on the dielectric layer, and the source passes through the first connection hole and the second connection hole, and a heavy doping region of the source region
  • the electrical connection is electrically connected to the heavy doping region of the drain region through the first connection hole and the second connection hole.
  • the invention also provides a preparation method of an N-type thin film transistor, comprising the following steps:
  • each set of doping regions including a heavy doping region and a lightly doped region connected to the heavy-doping region;
  • the method further comprises the steps of:
  • the method further comprises the steps of:
  • a buffer layer is formed on the substrate, wherein the buffer layer comprises SiOx and/or SiNy, x ⁇ 1, y ⁇ 1.
  • forming a polysilicon layer over the substrate comprises the steps of:
  • the amorphous silicon layer is converted into the polysilicon layer by excimer laser crystallization.
  • patterning the gate layer comprises the steps of:
  • the region where the gate layer is located in the semi-retained portion of the photoresist is partially etched.
  • ion implantation is performed on the source region and the drain region, specifically:
  • Phosphorus ions are implanted into the source region and the drain region using ion implantation techniques.
  • preparing the source and the drain over the two of the heavily doped regions comprises the steps of:
  • the metal layer is patterned to form the source and the drain.
  • a dielectric layer is formed on the gate insulating layer, specifically:
  • the dielectric layer is formed by depositing SiNx and/or SiOy on the gate insulating layer by plasma enhanced chemical vapor deposition.
  • the following steps are further included:
  • the dielectric layer is subjected to a rapid annealing treatment, wherein the rapid annealing temperature is 550 to 600 degrees Celsius, and the annealing time is 5 to 15 minutes.
  • a metal layer is deposited on the dielectric layer, specifically:
  • Molybdenum, aluminum, and molybdenum metal are sequentially deposited on the dielectric layer by physical vapor deposition to form the metal layer.
  • the invention also provides a preparation method of an OLED display panel, comprising the following steps:
  • a gate layer over the polysilicon layer, the gate layer being over the channel region, and a projection of the gate layer on the polysilicon layer, the source region and the drain The regions partially overlap; wherein the gate insulating layer is located between the polysilicon layer and the gate layer;
  • each set of doping regions including a heavy doping region and a lightly doped region connected to the heavy-doping region;
  • the source and the drain are prepared over the two of the heavily doped regions, comprising the steps of: forming a dielectric layer on the gate insulating layer, and the dielectric layer covers the gate layer;
  • the preparation method of the OLED display panel further includes:
  • planarization layer Forming a planarization layer on the dielectric layer, and the planarization layer covers the source and the drain;
  • An organic luminescent material is evaporated at the fourth connection hole, and the organic luminescent material is in contact with the anode.
  • the material of the flat layer and the pixel defining layer is polyimide.
  • the method further comprises the steps of:
  • the buffer layer comprises SiOx and/or SiNy, x ⁇ 1, y ⁇ 1;
  • Forming a polysilicon layer over the substrate includes the following steps:
  • Patterning the gate layer includes the following steps:
  • Phosphorus ions are implanted into the source region and the drain region using ion implantation techniques.
  • preparing the source and the drain over the two of the heavily doped regions further comprises the steps of:
  • the metal layer is patterned to form the source and the drain.
  • a dielectric layer is formed on the gate insulating layer, specifically:
  • the dielectric layer is formed by depositing SiNx and/or SiOy on the gate insulating layer by plasma enhanced chemical vapor deposition.
  • the following steps are further included:
  • Performing rapid annealing treatment on the dielectric layer wherein the rapid annealing temperature is 550-600 degrees Celsius, and the annealing time is 5-15 minutes;
  • Molybdenum, aluminum, and molybdenum metal are sequentially deposited on the dielectric layer by physical vapor deposition to form the metal layer.
  • the thickness of the gate layer corresponding to the light doping region of the N-type thin film transistor is relatively thin, and when the working voltage is applied to the thin film transistor, the electric field intensity generated at the portion is also weak, and the attracted electrons are also There are fewer, so the resistance is relatively large, which in turn acts to reduce leakage current in the LDD region, so that the device characteristics of the thin film transistor can be greatly improved.
  • FIG. 1 is a schematic structural view of an N-type thin film transistor provided by the present invention.
  • FIG. 2 is a schematic view showing the first connection hole and the second connection hole on the N-type thin film transistor provided by the present invention.
  • FIG. 3 is a schematic diagram of a third connection hole marked on the OLED display panel provided by the present invention.
  • FIG. 4 is a schematic structural view of an OLED display panel provided by the present invention.
  • FIG. 5 is a flow chart of a method of fabricating an N-type thin film transistor provided by the present invention.
  • FIG. 6 is a schematic view showing exposure of a gate layer by a semi-transmissive mask in the method for fabricating an N-type thin film transistor provided by the present invention.
  • FIG. 7 is an implanted source and drain region in an N-type thin film transistor manufacturing method provided by the present invention. Schematic diagram of phosphorus ions.
  • the present invention provides an N-type thin film transistor.
  • the N-type thin film transistor includes a polysilicon layer 1, a gate layer 2, a source 3, and a drain 4 from bottom to top.
  • An N-type thin film transistor is an N-channel thin film transistor.
  • the polysilicon layer 1 includes a channel region 11 and a source region 12 and a drain region 13 on both sides of the channel region 11, the gate layer 2 is located above the channel region 11, and the gate layer 2 is on the polysilicon layer 1.
  • the projections partially overlap the source region 12 and the drain region 13, and the thickness of the gate layer above the source region 12 and the drain region 13 is smaller than the thickness of the gate layer above the channel region 11.
  • the gate layer thickness h2 above the channel region 11 is greater than the gate layer thickness h1 above the source region 12 and the gate layer thickness h1' above the drain region 13, where h1 and h2
  • the ratio range between h1' and h2 is 1/10 to 1/5, and h1' and h1 can be equal.
  • the source region 12 and the drain region 13 each include a heavy doping region 101 and a light doping region 102 connected to the re-doping region 101, and the light doping region 102 of the source region 12 and the drain region 13 are both located at the gate.
  • the source 3 is located above the heavily doped region 101 of the source region 12 and is electrically connected to the heavily doped region 101 of the source region 12, and the drain 4 is located above the heavily doped region 101 of the drain region 13. And electrically connected to the heavy doping region 101 of the drain region 13.
  • the ions doped in the heavy doping region 101 and the light doping region 102 are all phosphorus ions; and the gate insulating layer 7 is further disposed between the polysilicon layer 1 and the gate layer 2.
  • a dielectric layer 8 is further disposed on the gate insulating layer 7, and the dielectric layer 8 covers the gate layer 2.
  • the dielectric layer 8 contains SiNx and/or SiOy, wherein x ⁇ 1, y ⁇ 1.
  • two first connection holes 14 are disposed on the dielectric layer 8
  • two second connection holes 15 are disposed on the gate insulating layer 7, and the two first connection holes 14 and the second two are respectively
  • the connection holes 15 are opposed to each other, and the two second connection holes 15 are opposed to the heavy-doping region 101 of the source region 12 and the heavy-doping region 101 of the drain region 13, respectively.
  • the source 3 and the drain 4 are both disposed on the dielectric layer 8 , and the source 3 is electrically connected to the re-doping region 101 of the source region 12 through the first connection hole 14 and the second connection hole 15 .
  • 4 is electrically connected to the heavy doping region 101 of the drain region 13 through the first connection hole 14 and the second connection hole 15.
  • the invention also provides an OLED display panel, as shown in FIG. 3 and FIG. 4, the OLED display
  • the display panel includes the above-mentioned N-type thin film transistor; a thin film transistor is provided with a substrate 5 under the polysilicon layer 1; a flat layer 9 is disposed above the dielectric layer 8 of the thin film transistor, and the flat layer 9 covers the source 3 and the drain of the thin film transistor 4, the flat layer 9 is provided with a third connection hole 16, the third connection hole 16 is located above the source 3 or the drain 4, the third connection hole 16 is provided with an anode 10, the anode 10 and the source 3 or the drain 4 Electrical connection.
  • the substrate 5 is a glass substrate.
  • a pixel defining layer 11 is disposed above the flat layer 9, a fourth connecting hole 17 is disposed on the pixel defining layer 11, and a fourth connecting hole 17 is disposed above the anode 10.
  • the organic light emitting material 12 is disposed in the fourth connecting hole 17, and the organic light emitting material is disposed. 12 is in contact with the anode 10.
  • the organic light-emitting material 12 is an OLED (Organic Light-Emitting Diode) light-emitting material.
  • a buffer layer 6 is disposed between the substrate 5 and the polysilicon layer 1, and the buffer layer 6 contains SiNx and/or SiOy, wherein x ⁇ 1, y ⁇ 1.
  • the invention also provides a method for preparing an N-type thin film transistor. As shown in FIG. 5, the method for preparing the N-type thin film transistor comprises the following steps:
  • a gate layer 2 is formed over the polysilicon layer 1, the gate layer 2 is located above the channel region 11, and the projection of the gate layer 2 on the polysilicon layer 1 partially overlaps the source region 12 and the drain region 13;
  • the gate layer 2 is patterned such that the thickness of the gate layer above the source region 12 and the drain region 13 is smaller than the thickness of the gate layer above the channel region 11;
  • the gate layer 2 is used as an ion implantation mask, and ion implantation is performed on the source region 12 and the drain region 13 to form two sets of doping regions, each of which includes a heavy doping region 101 and a heavy reference a light doping area 102 connected to the miscellaneous area 101;
  • the source 3 and the drain 4 are prepared over the two heavily doped regions 101, and the source 3 and the drain 4 are electrically connected to the two heavily doped regions 101, respectively (ie, form a good ohmic contact).
  • the heavy doping region 101 is also generally referred to as an N+ region, and the light doping region 102 is also referred to as an N-region or an LDD (Lightly Doped Drain) region.
  • the thickness of the gate layer 2 corresponding to the light doping region 102 is relatively thin.
  • the accumulated electric charge is relatively small, the generated electric field intensity is weak, and the electrons are attracted less. Therefore, the resistance is relatively large, thereby functioning to reduce leakage current in the LDD region, so that the device characteristics of the thin film transistor can be greatly improved.
  • a portion of the source region 12 and a portion of the drain region 13 are implanted with less ions, and may serve as the light doping region 102, not the ions implanted in the portion of the source region 12 and the portion of the drain region 13 below the gate layer 2.
  • the method for preparing the N-type thin film transistor provided by the present invention can save the process of implanting ions into the light-doped region 102 at a time, simplifying the process flow and saving manufacturing costs.
  • a gate insulating layer 7 is formed on the polysilicon layer 1; wherein the gate insulating layer 7 is located between the polysilicon layer 1 and the gate layer 2.
  • a buffer layer 6 is formed on the substrate 5, wherein the buffer layer 6 contains SiOx and/or SiNy, x ⁇ 1, y ⁇ 1.
  • the buffer layer 6 contains SiOx and/or SiNy, x ⁇ 1, y ⁇ 1.
  • an SiOx layer and a SiNy layer are successively deposited on the substrate 5.
  • the buffer layer 6 can block the entry of a part of external impurity ions.
  • Forming the polysilicon layer 1 over the substrate 5 includes the following steps:
  • amorphous silicon layer is deposited on the buffer layer 6; amorphous silicon is also amorphous silicon (a-Si).
  • the amorphous silicon layer is converted into the polysilicon layer 1 by means of excimer laser crystallization.
  • the patterned gate layer 2 includes the following steps:
  • the gate layer 2 is exposed and developed through a semi-transmissive mask to obtain a semi-retained portion of the photoresist.
  • the semi-retained portion of the photoresist is located above the source and the drain;
  • the region where the gate layer 2 is located in the semi-retained portion of the photoresist is partially etched.
  • the semi-transmissive mask comprises a light transmitting region 181, a semi-transmissive region 182, and an opaque region 183.
  • the light transmittance of the semi-transmissive region 182 ranges from 20% to 70%;
  • the opaque region 183 is located above the corresponding gate layer 2 of the channel region 11, and therefore, the photoresist coated on the gate layer 2 above the channel region 11 Without being exposed, the gate layer 2 above the channel region 11 is not etched during the etching process, and the thickness of the gate layer above the final channel region 11 is greater than the gates above the source region 12 and the drain region 13. Layer thickness.
  • ion implantation is performed on the source region 12 and the drain region 13, specifically:
  • Phosphorus ions are implanted into the source region 12 and the drain region 13 by ion implantation; a schematic diagram of implanting phosphorus ions is shown in FIG.
  • the heavy doping region 101 has a large amount of phosphorus ion implantation, and the resistance of the region is small, and a good ohmic contact can be formed with the subsequently fabricated source 3 and drain 4.
  • the thickness of the gate layer above the light doping region 102 is relatively thin, although the implantation of phosphorus ions is blocked, but when the thin film transistor operates normally, the electric field intensity generated by applying a voltage to the gate layer 2 is weak, and the attracted electrons are also Less, the resistance is relatively large, so that it can reduce the leakage current.
  • the source 3 and the drain 4 are prepared over the two heavily doped regions 101, including the following steps:
  • the patterned dielectric layer 8 and the gate insulating layer 7 form two first connection holes 14 on the dielectric layer 8, two second connection holes 15 on the gate insulating layer 7, and two first connections
  • the holes 14 are respectively opposite to the two second connecting holes 15, and the two second connecting holes 15 are respectively opposite to the two heavy doping regions 101;
  • the metal layer is patterned to form source 3 and drain 4.
  • a dielectric layer 8 is formed on the gate insulating layer 7, specifically:
  • a dielectric layer 8 is formed by depositing SiNx and/or SiOy on the gate insulating layer 7 by plasma enhanced chemical vapor deposition.
  • the dielectric layer 8 is also an ILD layer (also referred to as an interlayer insulating layer).
  • a SiNx layer and a SiOy layer are deposited on the gate insulating layer 7.
  • the dielectric layer 8 is subjected to rapid annealing activation treatment, wherein the rapid annealing temperature is 550 to 600 degrees Celsius, and the annealing time is 5 to 15 minutes.
  • a metal layer is deposited on the dielectric layer 8, specifically:
  • Molybdenum, aluminum, and molybdenum metal are sequentially deposited on the dielectric layer 8 by physical vapor deposition to form a metal layer.
  • the present invention also provides a method for fabricating an OLED display panel.
  • the method for fabricating the OLED display panel includes the method for preparing the N-type thin film transistor described above, and further includes the following steps:
  • a patterned flat layer 9 a third connection hole 16 is formed on the flat layer 9, and the third connection hole 16 is located above the source 3 or the drain 4;
  • An anode 10 is prepared at the third connection hole 16 , and the anode 10 is electrically connected to the source 3 or the drain 4 ;
  • the organic light-emitting material 12 is evaporated at the fourth connection hole 17, and the organic light-emitting material 12 is in contact with the anode 10.
  • the organic luminescent material 12 is an OLED luminescent material.
  • connection hole 16 is located above the source 3 or the drain 4.
  • the anode 10 is prepared at the third connection hole 16, specifically:
  • ITO indium tin oxide
  • the material of the flat layer 9 and the pixel defining layer 11 is polyimide.
  • the thickness of the gate layer 2 corresponding to the light doping region 102 is relatively thin, and the electric field intensity generated when the operating voltage is applied to the thin film transistor is also It is weaker and attracts less electrons, so the resistance is relatively large, which in turn acts to reduce the leakage current in the LDD region, so that the device characteristics of the thin film transistor can be greatly improved.
  • the preparation method of the thin film transistor can also save the process of implanting ions into the light-doped region 102 at one time, simplifying the process flow and saving the manufacturing cost.

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Abstract

一种N型薄膜晶体管及其制备方法、OLED显示面板的制备方法，薄膜晶体管由下至上包括：多晶硅层（1）、栅极层（2）、源极（3）、漏极（4）；其中，多晶硅层（1）包括沟道区（11），以及沟道区（11）两侧的源极区（12）和漏极区（13），栅极层（2）位于沟道区（11）上方，且栅极层（2）在多晶硅层（1）上的投影与源极区（12）和漏极区（13）部分重合，源极区（12）和漏极区（13）上方的栅极层（2）厚度，均小于沟道区（11）上方的栅极层（2）厚度；且源极区（12）和漏极区（13）均包含重掺杂区（101）和与重掺杂区（101）连接的轻掺杂区（102），轻掺杂区（102）均位于栅极层（2）下方，源极（3）位于源极区（12）的重掺杂区（101）上方且与源极区（12）的重掺杂区（101）电性连接，漏极（4）位于漏极区（13）的重掺杂区（101）上方且与漏极区（13）的重掺杂区（101）电性连接。可以减小薄膜晶体管的漏电流，改善薄膜晶体管的器件特性。

Description

N型薄膜晶体管及其制备方法、OLED显示面板的制备方法
本申请要求于2017年10月10日提交中国专利局、申请号为201710936407.9、发明名称为“N型薄膜晶体管及其制备方法、OLED显示面板及其制备方法”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种N型薄膜晶体管及其制备方法、OLED显示面板的制备方法。
背景技术
传统的方法制作低温多晶硅N型薄膜晶体管时，是在完成多晶硅的结晶和图形定义后，在制作N+区域(即重参杂区)和N-区域(N-区域又称为LDD：light drain doping，轻参杂漏结构)，需要使用两次掩膜板分别定义N+和N-区域，再进行两次磷离子的植入，再利用等离子体增强化学的气相沉积法沉积一层栅极绝缘层；传统的方法制作低温多晶硅N型薄膜晶体管工艺流程复杂，制作成本高，并且传统的方法制作出来的N型薄膜晶体管中的栅极层厚度均匀，在该薄膜晶体管处于关态时，任有较大的漏电流，导致该薄膜晶体管的关断与接通不是很灵敏，对显示面板的显示效果造成影响。
发明内容
为解决上述技术问题，本发明提供一种N型薄膜晶体管及其制备方法、OLED显示面板的制备方法，可以减小薄膜晶体管的漏电流，改善薄膜晶体管的器件特性。
本发明提供一种N型薄膜晶体管，由下至上包括：多晶硅层、栅极层、源极、漏极；
其中，所述多晶硅层包括沟道区，以及所述沟道区两侧的源极区和漏极区，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影与所述源极区和所述漏极区部分重合，所述源极区和所述漏极区上方的栅 极层厚度，均小于所述沟道区上方的栅极层厚度；
所述源极区和所述漏极区均包含重参杂区和与所述重参杂区连接的轻参杂区，所述轻参杂区均位于所述栅极层下方，所述源极位于所述源极区的重参杂区上方且与所述源极区的重参杂区电性连接，所述漏极位于所述漏极区的重参杂区上方且与所述漏极区的重参杂区电性连接。
优选地，所述重参杂区和所述轻参杂区参杂的离子均为磷离子。
优选地，所述多晶硅层与所述栅极层之间还设置有栅极绝缘层；
所述栅极绝缘层上还设置有介电层，且所述介电层覆盖所述栅极层，所述介电层包含SiNx和/或SiOy，其中，x≥1，y≥1。
优选地，所述介电层上设置有两个第一连接孔，所述栅极绝缘层上设置有两个第二连接孔，两个所述第一连接孔分别与两个所述第二连接孔正对，且两个所述第二连接孔分别与所述源极区的重参杂区和所述漏极区的重参杂区正对；
所述源极和所述漏极均设置在所述介电层上，且所述源极通过所述第一连接孔和所述第二连接孔，与所述源极区的重参杂区电性连接，所述漏极通过所述第一连接孔和所述第二连接孔，与所述漏极区的重参杂区电性连接。
本发明还提供一种N型薄膜晶体管的制备方法，包括下述步骤：
在基板上方形成多晶硅层；
图形化所述多晶硅层，形成沟道区，以及位于所述沟道区两侧的源极区和漏极区；
在所述多晶硅层上方形成栅极层，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影，与所述源极区和所述漏极区部分重合；
图形化所述栅极层，使所述源极区和所述漏极区上方的栅极层厚度，均小于所述沟道区上方的栅极层厚度；
以所述栅极层作为离子注入掩膜，向所述源极区和所述漏极区进行离子植入，形成两组参杂区，每一组参杂区包括一个重参杂区和与所述重参杂区相连的轻参杂区；
在两个所述重参杂区上方制备源极和漏极，且所述源极和所述漏极分别 与两个所述重参杂区电性连接。
优选地，在所述多晶硅层上方形成栅极层之前，还包括下述步骤：
在所述多晶硅层上形成栅极绝缘层；其中，所述栅极绝缘层位于所述多晶硅层与所述栅极层之间。
优选地，在基板上方形成多晶硅层之前，还包括下述步骤：
在所述基板上形成缓冲层，其中，所述缓冲层包含SiOx和/或SiNy，x≥1，y≥1。
优选地，在基板上方形成多晶硅层，包括下述步骤：
在所述缓冲层上沉积非晶硅层；
采用准分子镭射结晶的方式将所述非晶硅层转化为所述多晶硅层。
优选地，图形化所述栅极层，包括下述步骤：
在所述栅极层上涂布光阻；
通过半透掩膜板对所述栅极层进行曝光及显影处理，得到光阻半保留部分，所述光阻半保留部分位于所述源极和所述漏极上方；
将所述栅极层位于所述光阻半保留部分的区域进行部分刻蚀。
优选地，向所述源极区和所述漏极区进行离子植入，具体为：
采用离子注入技术，向所述源极区和所述漏极区植入磷离子。
优选地，在两个所述重参杂区上方制备源极和漏极，包括下述步骤：
在所述栅极绝缘层上形成介电层，且所述介电层覆盖所述栅极层；
图形化所述介电层和所述栅极绝缘层，在所述介电层上形成两个第一连接孔，在所述栅极绝缘层上形成两个第二连接孔，且两个所述第一连接孔分别与两个所述第二连接孔正对，两个所述第二连接孔分别与两个所述重参杂区正对；
在所述介电层上沉积金属层，且所述金属层均通过两个所述第一连接孔和两个所述第二连接孔，与两个所述重参杂区电性连接；
图形化所述金属层，形成所述源极和所述漏极。
优选地，在所述栅极绝缘层上形成介电层，具体为：
采用等离子体增强化学的气相沉积法，在所述栅极绝缘层上沉积SiNx和/或SiOy，形成所述介电层。
优选地，在图形化所述介电层和所述栅极绝缘层之前还包括下述步骤：
对所述介电层进行快速退火处理，其中快速退火的温度为550～600摄氏度，退火时间为5～15分钟。
优选地，在所述介电层上沉积金属层，具体为：
采用物理气相沉积的方式，在所述介电层上依次沉积钼、铝、钼金属，形成所述金属层。
本发明还提供一种OLED显示面板的制备方法，包括下述步骤：
在基板上方形成多晶硅层；
图形化所述多晶硅层，形成沟道区，以及位于所述沟道区两侧的源极区和漏极区；
在所述多晶硅层上形成栅极绝缘层；
在所述多晶硅层上方形成栅极层，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影，与所述源极区和所述漏极区部分重合；其中，所述栅极绝缘层位于所述多晶硅层与所述栅极层之间；
图形化所述栅极层，使所述源极区和所述漏极区上方的栅极层厚度，均小于所述沟道区上方的栅极层厚度；
以所述栅极层作为离子注入掩膜，向所述源极区和所述漏极区进行离子植入，形成两组参杂区，每一组参杂区包括一个重参杂区和与所述重参杂区相连的轻参杂区；
在两个所述重参杂区上方制备源极和漏极，且所述源极和所述漏极分别与两个所述重参杂区电性连接；
其中，在两个所述重参杂区上方制备源极和漏极，包括下述步骤：在所述栅极绝缘层上形成介电层，且所述介电层覆盖所述栅极层；
OLED显示面板的制备方法还包括：
在介电层上形成平坦层，且所述平坦层覆盖源极和漏极；
图形化所述平坦层，在所述平坦层上形成第三连接孔，所述第三连接孔位于所述源极或者所述漏极上方；
在所述第三连接孔处制备阳极，且所述阳极与所述源极或者所述漏极电性连接；
在所述平坦层上沉积像素定义层，且所述像素定义层覆盖所述阳极；
图形化所述像素定义层，在所述像素定义层上形成第四连接孔，且所述第四连接孔位于所述阳极上方；
在所述第四连接孔处蒸镀有机发光材料，且所述有机发光材料与所述阳极接触。
优选地，
在所述第三连接孔处制备阳极，具体为：
在所述第三连接孔处沉积铟锡氧化物，并将所述铟锡氧化物图形化形成所述阳极；
所述平坦层和所述像素定义层的材料均为聚酰亚胺。
优选地，在基板上方形成多晶硅层之前，还包括下述步骤：
在所述基板上形成缓冲层，其中，所述缓冲层包含SiOx和/或SiNy，x≥1，y≥1；
在基板上方形成多晶硅层，包括下述步骤：
在所述缓冲层上沉积非晶硅层；
采用准分子镭射结晶的方式将所述非晶硅层转化为所述多晶硅层；
图形化所述栅极层，包括下述步骤：
在所述栅极层上涂布光阻；
通过半透掩膜板对所述栅极层进行曝光及显影处理，得到光阻半保留部分，所述光阻半保留部分位于所述源极和所述漏极上方；
将所述栅极层位于所述光阻半保留部分的区域进行部分刻蚀；
向所述源极区和所述漏极区进行离子植入，具体为：
采用离子注入技术，向所述源极区和所述漏极区植入磷离子。
优选地，在两个所述重参杂区上方制备源极和漏极，还包括下述步骤：
图形化所述介电层和所述栅极绝缘层，在所述介电层上形成两个第一连接孔，在所述栅极绝缘层上形成两个第二连接孔，且两个所述第一连接孔分别与两个所述第二连接孔正对，两个所述第二连接孔分别与两个所述重参杂区正对；
在所述介电层上沉积金属层，且所述金属层均通过两个所述第一连接孔 和两个所述第二连接孔，与两个所述重参杂区电性连接；
图形化所述金属层，形成所述源极和所述漏极。
优选地，在所述栅极绝缘层上形成介电层，具体为：
采用等离子体增强化学的气相沉积法，在所述栅极绝缘层上沉积SiNx和/或SiOy，形成所述介电层。
优选地，在图形化所述介电层和所述栅极绝缘层之前还包括下述步骤：
对所述介电层进行快速退火处理，其中快速退火的温度为550～600摄氏度，退火时间为5～15分钟；
在所述介电层上沉积金属层，具体为：
采用物理气相沉积的方式，在所述介电层上依次沉积钼、铝、钼金属，形成所述金属层。
实施本发明，具有如下有益效果：N型薄膜晶体管的轻参杂区对应的栅极层的厚度较薄，在薄膜晶体管施加工作电压时，该处产生的电场强度也较弱，吸引的电子也较少，因此电阻相对较大，进而起到LDD区域的减小漏电流的作用，从而可以大幅改善该薄膜晶体管的器件特性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的N型薄膜晶体管的结构示意图。
图2是本发明提供的N型薄膜晶体管上标注了第一连接孔和第二连接孔的示意图。
图3是本发明提供的OLED显示面板上标注了第三连接孔的示意图。
图4是本发明提供的OLED显示面板的结构示意图。
图5是本发明提供的N型薄膜晶体管制备方法的流程图。
图6是本发明提供的N型薄膜晶体管制备方法中通过半透掩膜板对栅极层进行曝光的示意图。
图7是本发明提供的N型薄膜晶体管制备方法中向源极区和漏极区植入 磷离子的示意图。
具体实施方式
本发明提供一种N型薄膜晶体管，如图1所示，N型薄膜晶体管由下至上包括：多晶硅层1、栅极层2、源极3、漏极4。N型薄膜晶体管即N沟道薄膜晶体管。
其中，多晶硅层1包括沟道区11，以及沟道区11两侧的源极区12和漏极区13，栅极层2位于沟道区11上方，且栅极层2在多晶硅层1上的投影与源极区12和漏极区13部分重合，源极区12和漏极区13上方的栅极层厚度，均小于沟道区11上方的栅极层厚度。如图1中所示，沟道区11上方的栅极层厚度h2，大于源极区12上方的栅极层厚度h1和漏极区13上方的栅极层厚度h1’，其中，h1与h2之间的比值范围，以及h1’与h2之间的比值范围均为1/10～1/5，h1’与h1可相等。
源极区12和漏极区13均包含重参杂区101和与重参杂区101连接的轻参杂区102，源极区12和漏极区13的轻参杂区102均位于栅极层2下方，源极3位于源极区12的重参杂区101上方且与源极区12的重参杂区101电性连接，漏极4位于漏极区13的重参杂区101上方且与漏极区13的重参杂区101电性连接。
进一步地，重参杂区101和轻参杂区102参杂的离子均为磷离子；多晶硅层1与栅极层2之间还设置有栅极绝缘层7。
栅极绝缘层7上还设置有介电层8，且介电层8覆盖栅极层2，介电层8包含SiNx和/或SiOy，其中，x≥1，y≥1。
如图2所示，介电层8上设置有两个第一连接孔14，栅极绝缘层7上设置有两个第二连接孔15，两个第一连接孔14分别与两个第二连接孔15正对，且两个第二连接孔15分别与源极区12的重参杂区101和漏极区13的重参杂区101正对。
源极3和漏极4均设置在介电层8上，且源极3通过第一连接孔14和第二连接孔15，与源极区12的重参杂区101电性连接，漏极4通过第一连接孔14和第二连接孔15，与漏极区13的重参杂区101电性连接。
本发明还提供一种OLED显示面板，如图3和图4所示，该OLED显 示面板包括上述的N型薄膜晶体管；薄膜晶体管的多晶硅层1下方设置有基板5；薄膜晶体管的介电层8上方设置有平坦层9，且平坦层9覆盖薄膜晶体管的源极3和漏极4，平坦层9上设置有第三连接孔16，第三连接孔16位于源极3或者漏极4上方，第三连接孔16中设置有阳极10，阳极10与源极3或者漏极4电性连接。其中，基板5为玻璃基板。
平坦层9上方设置有像素定义层11，像素定义层11上设置有第四连接孔17，且第四连接孔17位于阳极10上方，第四连接孔17中设置有机发光材料12，有机发光材料12与阳极10接触。其中，有机发光材料12为OLED(Organic Light-Emitting Diode，有机发光半导体)发光材料。
进一步地，基板5与多晶硅层1之间设置有缓冲层6，且缓冲层6包含SiNx和/或SiOy，其中，x≥1，y≥1。
本发明还提供一种N型薄膜晶体管的制备方法，如图5所示，该N型薄膜晶体管的制备方法包括下述步骤：
在基板5上方形成多晶硅层1；
图形化多晶硅层1，形成沟道区11，以及位于沟道区11两侧的源极区12和漏极区13；
在多晶硅层1上方形成栅极层2，栅极层2位于沟道区11上方，且栅极层2在多晶硅层1上的投影，与源极区12和漏极区13部分重合；
图形化栅极层2，使源极区12和漏极区13上方的栅极层厚度，均小于沟道区11上方的栅极层厚度；
以栅极层2作为离子注入掩膜，向源极区12和漏极区13进行离子植入，形成两组参杂区，每一组参杂区包括一个重参杂区101和与重参杂区101相连的轻参杂区102；
在两个重参杂区101上方制备源极3和漏极4，且源极3和漏极4分别与两个重参杂区101电性连接(即形成良好的欧姆接触)。其中，重参杂区101一般也称为N+区域，轻参杂区102也称为N-区域或者LDD(Lightly Doped Drain，轻掺杂漏结构)区域。
轻参杂区102对应的栅极层2的厚度较薄，在薄膜晶体管施加工作电压时，该处积蓄的电荷相对较少，产生的电场强度也较弱，吸引的电子也较少， 因此电阻相对较大，进而起到LDD区域的减小漏电流的作用，从而可以大幅改善该薄膜晶体管的器件特性。并且，上述制备N型薄膜晶体管的方法中，只有一次离子植入的过程，在该次离子植入过程中，栅极层2充当了离子注入掩膜的作用，因此，位于栅极层2下方的部分源极区12和部分漏极区13植入的离子较少，可以作为轻参杂区102，不是位于栅极层2下方的部分源极区12和部分漏极区13植入的离子较多，可以作为重参杂区101；因而，本发明提供的N型薄膜晶体管的制备方法，还能够节省一次给轻参杂区102植入离子的过程，简化了工艺流程，节省制造成本。
进一步地，在多晶硅层1上方形成栅极层2之前，还包括下述步骤：
在多晶硅层1上形成栅极绝缘层7；其中，栅极绝缘层7位于多晶硅层1与栅极层2之间。
在基板5上方形成多晶硅层1之前，还包括下述步骤：
在基板5上形成缓冲层6，其中，缓冲层6包含SiOx和/或SiNy，x≥1，y≥1。优选地，在基板5上连续沉积SiOx层和SiNy层。缓冲层6可以阻挡部分外部杂质离子的进入。
在基板5上方形成多晶硅层1，包括下述步骤：
在缓冲层6上沉积非晶硅层；非晶硅也即是无定形硅(a-Si)。
采用准分子镭射结晶的方式将非晶硅层转化为多晶硅层1。
进一步地，图形化栅极层2，包括下述步骤：
在栅极层2上涂布光阻；
通过半透掩膜板对栅极层2进行曝光及显影处理，得到光阻半保留部分，
光阻半保留部分位于源极和漏极上方；
将栅极层2位于光阻半保留部分的区域进行部分刻蚀。
其中，如图6所示，半透掩膜板包括透光区181、半透光区182，不透光区183，半透光区182的透光率范围为20％～70％；通过半透掩膜板对栅极层2进行曝光处理时，不透光区183位于沟道区11对应的栅极层2上方，因此，沟道区11上方的栅极层2上涂布的光阻没有被曝光，刻蚀制程中，沟道区11上方的栅极层2不会被刻蚀，最终沟道区11上方的栅极层厚度大于源极区12和漏极区13上方的栅极层厚度。
进一步地，向源极区12和漏极区13进行离子植入，具体为：
采用离子注入技术，向源极区12和漏极区13植入磷离子；植入磷离子的示意图如图7所示。其中，重参杂区101有大量的磷离子植入，该区域的电阻会很小，与后续制作的源极3和漏极4能够形成良好的欧姆接触。轻参杂区102上方的栅极层厚度较薄，虽然会阻挡磷离子的植入，但是在薄膜晶体管正常工作时，给栅极层2施加电压所产生的电场强度较弱，吸引的电子也较少，电阻相对较大，从而可以起到减小漏电流的作用。
进一步地，在两个重参杂区101上方制备源极3和漏极4，包括下述步骤：
在栅极绝缘层7上形成介电层8，且介电层8覆盖栅极层2；
图形化介电层8和栅极绝缘层7，在介电层8上形成两个第一连接孔14，在栅极绝缘层7上形成两个第二连接孔15，且两个第一连接孔14分别与两个第二连接孔15正对，两个第二连接孔15分别与两个重参杂区101正对；
在介电层8上沉积金属层，且金属层均通过两个第一连接孔14和两个第二连接孔15，与两个重参杂区101电性连接；
图形化金属层，形成源极3和漏极4。
进一步地，在栅极绝缘层7上形成介电层8，具体为：
采用等离子体增强化学的气相沉积法，在栅极绝缘层7上沉积SiNx和/或SiOy，形成介电层8。介电层8也即是ILD层(也称为层间绝缘层)。优选地，在栅极绝缘层7上沉积SiNx层和SiOy层。
在图形化介电层8和栅极绝缘层7之前还包括下述步骤：
对介电层8进行快速退火活化处理，其中快速退火的温度为550～600摄氏度，退火时间为5～15分钟。
进一步地，在介电层8上沉积金属层，具体为：
采用物理气相沉积的方式，在介电层8上依次沉积钼、铝、钼金属，形成金属层。
本发明还提供一种OLED显示面板的制备方法，该OLED显示面板的制备方法包括上述的N型薄膜晶体管的制备方法，还包括下述步骤：
在介电层8上形成平坦层9，且平坦层9覆盖源极3和漏极4；
图形化平坦层9，在平坦层9上形成第三连接孔16，第三连接孔16位于源极3或者漏极4上方；
在第三连接孔16处制备阳极10，且阳极10与源极3或者漏极4电性连接；
在平坦层9上沉积像素定义层11，且像素定义层11覆盖阳极10；
图形化像素定义层11，在像素定义层11上形成第四连接孔17，且第四连接孔17位于阳极10上方；
在第四连接孔17处蒸镀有机发光材料12，且有机发光材料12与阳极10接触。其中，有机发光材料12为OLED发光材料。
进一步地，第三连接孔16位于源极3或者漏极4上方。
在第三连接孔16处制备阳极10，具体为：
在第三连接孔16处沉积铟锡氧化物(即ITO)，并将铟锡氧化物图形化形成阳极10；
平坦层9和像素定义层11的材料均为聚酰亚胺。
上述所说的图形化各膜层，例如金属层、平坦层9、像素定义层11，都是在该膜层上涂布光阻材料，再进行曝光及显影处理，进行刻蚀，完成各膜层的图形化处理过程。
综上所述，本发明提供的N型薄膜晶体管及其制备方法，轻参杂区102对应的栅极层2的厚度相对较薄，在薄膜晶体管施加工作电压时，该处产生的电场强度也较弱，吸引的电子也较少，因此电阻相对较大，进而起到LDD区域的减小漏电流的作用，从而可以大幅改善该薄膜晶体管的器件特性。并且，上述制备N型薄膜晶体管的方法中，只有一次离子植入的过程，在该次离子植入过程中，栅极层2充当了离子注入掩膜的作用，因此，本发明提供的N型薄膜晶体管的制备方法，还能够节省一次给轻参杂区102植入离子的过程，简化了工艺流程，节省制造成本。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种N型薄膜晶体管，其中，由下至上包括：多晶硅层、栅极层、源极、漏极；
    其中，所述多晶硅层包括沟道区，以及所述沟道区两侧的源极区和漏极区，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影与所述源极区和所述漏极区部分重合，所述源极区和所述漏极区上方的栅极层厚度，均小于所述沟道区上方的栅极层厚度；
    所述源极区和所述漏极区均包含重参杂区和与所述重参杂区连接的轻参杂区，所述轻参杂区均位于所述栅极层下方，所述源极位于所述源极区的重参杂区上方且与所述源极区的重参杂区电性连接，所述漏极位于所述漏极区的重参杂区上方且与所述漏极区的重参杂区电性连接。
  2. 根据权利要求1所述的N型薄膜晶体管，其中，
    所述重参杂区和所述轻参杂区参杂的离子均为磷离子。
  3. 根据权利要求1所述的N型薄膜晶体管，其中，
    所述多晶硅层与所述栅极层之间还设置有栅极绝缘层；
    所述栅极绝缘层上还设置有介电层，且所述介电层覆盖所述栅极层，所述介电层包含SiNx和/或SiOy，其中，x≥1，y≥1。
  4. 根据权利要求3所述的N型薄膜晶体管，其中，
    所述介电层上设置有两个第一连接孔，所述栅极绝缘层上设置有两个第二连接孔，两个所述第一连接孔分别与两个所述第二连接孔正对，且两个所述第二连接孔分别与所述源极区的重参杂区和所述漏极区的重参杂区正对；
    所述源极和所述漏极均设置在所述介电层上，且所述源极通过所述第一连接孔和所述第二连接孔，与所述源极区的重参杂区电性连接，所述漏极通过所述第一连接孔和所述第二连接孔，与所述漏极区的重参杂区电性连接。
  5. 一种N型薄膜晶体管的制备方法，其中，包括下述步骤：
    在基板上方形成多晶硅层；
    图形化所述多晶硅层，形成沟道区，以及位于所述沟道区两侧的源极区和漏极区；
    在所述多晶硅层上方形成栅极层，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影，与所述源极区和所述漏极区部分重合；
    图形化所述栅极层，使所述源极区和所述漏极区上方的栅极层厚度，均小于所述沟道区上方的栅极层厚度；
    以所述栅极层作为离子注入掩膜，向所述源极区和所述漏极区进行离子植入，形成两组参杂区，每一组参杂区包括一个重参杂区和与所述重参杂区相连的轻参杂区；
    在两个所述重参杂区上方制备源极和漏极，且所述源极和所述漏极分别与两个所述重参杂区电性连接。
  6. 根据权利要求5所述的N型薄膜晶体管的制备方法，其中，在所述多晶硅层上方形成栅极层之前，还包括下述步骤：
    在所述多晶硅层上形成栅极绝缘层；其中，所述栅极绝缘层位于所述多晶硅层与所述栅极层之间。
  7. 根据权利要求5所述的N型薄膜晶体管的制备方法，其中，
    在基板上方形成多晶硅层之前，还包括下述步骤：
    在所述基板上形成缓冲层，其中，所述缓冲层包含SiOx和/或SiNy，x≥1，y≥1。
  8. 根据权利要求5所述的N型薄膜晶体管的制备方法，其中，
    在基板上方形成多晶硅层，包括下述步骤：
    在所述缓冲层上沉积非晶硅层；
    采用准分子镭射结晶的方式将所述非晶硅层转化为所述多晶硅层。
  9. 根据权利要求5所述的N型薄膜晶体管的制备方法，其中，图形化所述栅极层，包括下述步骤：
    在所述栅极层上涂布光阻；
    通过半透掩膜板对所述栅极层进行曝光及显影处理，得到光阻半保留部分，所述光阻半保留部分位于所述源极和所述漏极上方；
    将所述栅极层位于所述光阻半保留部分的区域进行部分刻蚀。
  10. 根据权利要求5所述的N型薄膜晶体管的制备方法，其中，
    向所述源极区和所述漏极区进行离子植入，具体为：
    采用离子注入技术，向所述源极区和所述漏极区植入磷离子。
  11. 根据权利要求6所述的N型薄膜晶体管的制备方法，其中，在两个所述重参杂区上方制备源极和漏极，包括下述步骤：
    在所述栅极绝缘层上形成介电层，且所述介电层覆盖所述栅极层；
    图形化所述介电层和所述栅极绝缘层，在所述介电层上形成两个第一连接孔，在所述栅极绝缘层上形成两个第二连接孔，且两个所述第一连接孔分别与两个所述第二连接孔正对，两个所述第二连接孔分别与两个所述重参杂区正对；
    在所述介电层上沉积金属层，且所述金属层均通过两个所述第一连接孔和两个所述第二连接孔，与两个所述重参杂区电性连接；
    图形化所述金属层，形成所述源极和所述漏极。
  12. 根据权利要求11所述的N型薄膜晶体管的制备方法，其中，
    在所述栅极绝缘层上形成介电层，具体为：
    采用等离子体增强化学的气相沉积法，在所述栅极绝缘层上沉积SiNx和/或SiOy，形成所述介电层。
  13. 根据权利要求11所述的N型薄膜晶体管的制备方法，其中，
    在图形化所述介电层和所述栅极绝缘层之前还包括下述步骤：
    对所述介电层进行快速退火处理，其中快速退火的温度为550～600摄氏度，退火时间为5～15分钟。
  14. 根据权利要求11所述的N型薄膜晶体管的制备方法，其中，
    在所述介电层上沉积金属层，具体为：
    采用物理气相沉积的方式，在所述介电层上依次沉积钼、铝、钼金属，形成所述金属层。
  15. 一种OLED显示面板的制备方法，其中，包括下述步骤：
    在基板上方形成多晶硅层；
    图形化所述多晶硅层，形成沟道区，以及位于所述沟道区两侧的源极区和漏极区；
    在所述多晶硅层上形成栅极绝缘层；
    在所述多晶硅层上方形成栅极层，所述栅极层位于所述沟道区上方，且所述栅极层在所述多晶硅层上的投影，与所述源极区和所述漏极区部分重合；其中，所述栅极绝缘层位于所述多晶硅层与所述栅极层之间；
    图形化所述栅极层，使所述源极区和所述漏极区上方的栅极层厚度，均小于所述沟道区上方的栅极层厚度；
    以所述栅极层作为离子注入掩膜，向所述源极区和所述漏极区进行离子植入，形成两组参杂区，每一组参杂区包括一个重参杂区和与所述重参杂区相连的轻参杂区；
    在两个所述重参杂区上方制备源极和漏极，且所述源极和所述漏极分别与两个所述重参杂区电性连接；
    其中，在两个所述重参杂区上方制备源极和漏极，包括下述步骤：在所述栅极绝缘层上形成介电层，且所述介电层覆盖所述栅极层；
    OLED显示面板的制备方法还包括：
    在介电层上形成平坦层，且所述平坦层覆盖源极和漏极；
    图形化所述平坦层，在所述平坦层上形成第三连接孔，所述第三连接孔位于所述源极或者所述漏极上方；
    在所述第三连接孔处制备阳极，且所述阳极与所述源极或者所述漏极电性连接；
    在所述平坦层上沉积像素定义层，且所述像素定义层覆盖所述阳极；
    图形化所述像素定义层，在所述像素定义层上形成第四连接孔，且所述第四连接孔位于所述阳极上方；
    在所述第四连接孔处蒸镀有机发光材料，且所述有机发光材料与所述阳极接触。
  16. 根据权利要求15所述的OLED显示面板的制备方法，其中，
    在所述第三连接孔处制备阳极，具体为：
    在所述第三连接孔处沉积铟锡氧化物，并将所述铟锡氧化物图形化形成所述阳极；
    所述平坦层和所述像素定义层的材料均为聚酰亚胺。
  17. 根据权利要求15所述的OLED显示面板的制备方法，其中，
    在基板上方形成多晶硅层之前，还包括下述步骤：
    在所述基板上形成缓冲层，其中，所述缓冲层包含SiOx和/或SiNy，x≥1，y≥1；
    在基板上方形成多晶硅层，包括下述步骤：
    在所述缓冲层上沉积非晶硅层；
    采用准分子镭射结晶的方式将所述非晶硅层转化为所述多晶硅层；
    图形化所述栅极层，包括下述步骤：
    在所述栅极层上涂布光阻；
    通过半透掩膜板对所述栅极层进行曝光及显影处理，得到光阻半保留部分，所述光阻半保留部分位于所述源极和所述漏极上方；
    将所述栅极层位于所述光阻半保留部分的区域进行部分刻蚀；
    向所述源极区和所述漏极区进行离子植入，具体为：
    采用离子注入技术，向所述源极区和所述漏极区植入磷离子。
  18. 根据权利要求15所述的OLED显示面板的制备方法，其中，在两个所述重参杂区上方制备源极和漏极，还包括下述步骤：
    图形化所述介电层和所述栅极绝缘层，在所述介电层上形成两个第一连接孔，在所述栅极绝缘层上形成两个第二连接孔，且两个所述第一连接孔分别与两个所述第二连接孔正对，两个所述第二连接孔分别与两个所述重参杂区正对；
    在所述介电层上沉积金属层，且所述金属层均通过两个所述第一连接孔和两个所述第二连接孔，与两个所述重参杂区电性连接；
    图形化所述金属层，形成所述源极和所述漏极。
  19. 根据权利要求15所述的OLED显示面板的制备方法，其中，
    在所述栅极绝缘层上形成介电层，具体为：
    采用等离子体增强化学的气相沉积法，在所述栅极绝缘层上沉积SiNx和/或SiOy，形成所述介电层。
  20. 根据权利要求18所述的OLED显示面板的制备方法，其中，
    在图形化所述介电层和所述栅极绝缘层之前还包括下述步骤：
    对所述介电层进行快速退火处理，其中快速退火的温度为550～600摄氏 度，退火时间为5～15分钟；
    在所述介电层上沉积金属层，具体为：
    采用物理气相沉积的方式，在所述介电层上依次沉积钼、铝、钼金属，形成所述金属层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447764A (zh) * 2019-08-27 2021-03-05 苹果公司 用于显示设备的氢陷阱层及显示设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538861B (zh) * 2018-05-04 2021-03-16 武汉华星光电技术有限公司 阵列基板及其制造方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017665A1 (en) * 1996-12-06 2002-02-14 Lg Electronics, Inc. Thin film transistor and method of manufacturing the same
CN1722366A (zh) * 2004-06-01 2006-01-18 株式会社半导体能源研究所 半导体器件的制造方法
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
CN104241389A (zh) * 2013-06-21 2014-12-24 上海和辉光电有限公司 薄膜晶体管和有源矩阵有机发光二极管组件及制造方法
CN105810573A (zh) * 2016-03-15 2016-07-27 深圳市华星光电技术有限公司 薄膜晶体管的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1331202C (zh) * 2004-03-19 2007-08-08 友达光电股份有限公司 薄膜晶体管的制作方法
CN104900712A (zh) * 2015-06-09 2015-09-09 武汉华星光电技术有限公司 Tft基板结构的制作方法及tft基板结构
CN106098628B (zh) * 2016-06-07 2019-04-02 深圳市华星光电技术有限公司 Tft背板的制作方法及tft背板
CN106229347B (zh) * 2016-08-24 2019-06-07 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017665A1 (en) * 1996-12-06 2002-02-14 Lg Electronics, Inc. Thin film transistor and method of manufacturing the same
CN1722366A (zh) * 2004-06-01 2006-01-18 株式会社半导体能源研究所 半导体器件的制造方法
CN104241389A (zh) * 2013-06-21 2014-12-24 上海和辉光电有限公司 薄膜晶体管和有源矩阵有机发光二极管组件及制造方法
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
CN105810573A (zh) * 2016-03-15 2016-07-27 深圳市华星光电技术有限公司 薄膜晶体管的制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447764A (zh) * 2019-08-27 2021-03-05 苹果公司 用于显示设备的氢陷阱层及显示设备

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