WO2018154728A1

WO2018154728A1 - Display device

Info

Publication number: WO2018154728A1
Application number: PCT/JP2017/007188
Authority: WO
Inventors: 治人矢吹
Original assignee: 堺ディスプレイプロダクト株式会社
Priority date: 2017-02-24
Filing date: 2017-02-24
Publication date: 2018-08-30
Also published as: US10964278B2; CN110291574A; CN110291574B; US20200234662A1

Abstract

A display device (1) comprises a plurality of pixels (3), a plurality of gate lines (GL), a plurality of source lines (SL), and a control unit (2). The plurality of pixels are arranged in a matrix pattern. The gate lines are each connected to a group of pixels arrayed in a row direction and select the pixel groups of the rows at a prescribed interval. The source lines are each connected to a group of pixels arrayed in a column direction and supply a voltage corresponding to a prescribed gradation to the group of pixels of a selected row. The control unit, on the basis of gradation data (D(x, y, n)) representing gradations included in an image of one frame, controls the timing at which the gradations of each row within the image are displayed in sequence by the group of pixels of the corresponding row. Referring to a pixel that is to be displayed, the control unit corrects gradation data representing the gradation to be displayed by the pixel on the basis of an integrated value (A(x, y, n)) representing the integral of a voltage to be applied to the source line connected to the pixel in an upcoming one frame period (Tp).

Description

Display device

The present invention relates to a display device such as a liquid crystal display device.

A phenomenon called vertical shadow is known as one of the phenomena that deteriorates the image quality of images displayed on a liquid crystal display device.

Patent Document 1 discloses an active matrix display device for the purpose of preventing vertical shadows. In the display device disclosed in Patent Document 1, predetermined data is obtained based on data in each column included in input image data, and a vertical blanking period after an effective period of image display using the image data is obtained based on the obtained data. The voltage driving of the data signal line (source line) to which the display element (pixel) is connected is performed. Thus, the voltage held in each display element is adjusted in a lump within the vertical blanking period after the image data is supplied, thereby suppressing the vertical shadow.

JP 2008-58345 A

Vertical shadow is caused by a Csd parasitic capacitance between a pixel and a source line in a display device. The Csd parasitic capacitance also causes problems such as gradation inclination in the image displayed on the display device.

An object of the present invention is to provide a display device capable of suppressing the influence of Csd parasitic capacitance when displaying an image on the display device.

The display device according to the present invention includes a plurality of pixels, a plurality of gate lines, a plurality of source lines, and a control unit. The plurality of pixels are arranged in a matrix. The plurality of gate lines are connected to pixel groups arranged in the row direction of the pixel matrix, and sequentially select the pixel groups in each row at a predetermined frame period. The plurality of source lines are connected to a pixel group arranged in the column direction of the pixel matrix, and supply a voltage corresponding to a predetermined gradation to the pixel group in the selected row. The control unit controls the timing for sequentially displaying the gradation for one row in the video on the pixel group of each row based on the gradation data indicating the gradation included in the video of one frame. The control unit is configured to integrate a voltage applied to a source line connected to the pixel in a period for one frame with respect to a pixel to be displayed as a reference, or the same source line as the pixel in a period for one frame in the future. On the basis of the integrated value indicating the total sum of the gradation data indicating the gradation to be displayed on the other pixels connected to, the gradation data indicating the gradation to be displayed on the pixel is corrected.

According to the display device of the present invention, the gradation data for the pixel is corrected according to the integration of the voltage of the source line in one future frame, with the pixel to be displayed as a reference. Thereby, the influence of the Csd parasitic capacitance when displaying an image on the display device can be suppressed.

The figure which shows the structure of the display apparatus which concerns on Embodiment 1 of this invention. FIG. 11 is a diagram showing a structure of a pixel in a display panel of a display device The block diagram which shows the structure of the control circuit in a display apparatus 1 is a block diagram illustrating a configuration of a data correction unit according to a first embodiment. FIG. 3 is a block diagram illustrating a configuration example of a Csd correction circuit according to the first embodiment. The figure for demonstrating the vertical shadow in a display panel The figure for demonstrating the calculation method of Csd correction | amendment by a data correction part. The figure for demonstrating the outline | summary of the display apparatus which concerns on Embodiment 2. FIG. FIG. 9 is a block diagram illustrating a configuration example of a data correction unit according to the second embodiment. FIG. 3 is a block diagram illustrating a configuration example of a Csd correction circuit according to a second embodiment.

Hereinafter, an embodiment of a display device according to the present invention will be described with reference to the accompanying drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

(Embodiment 1)
1. Configuration The configuration of the display device according to the first embodiment will be described below.

The configuration of the display device according to Embodiment 1 will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of a display device 1 according to the present embodiment.

The display device 1 according to the present embodiment constitutes a liquid crystal display device such as a liquid crystal television. As shown in FIG. 1, the display device 1 includes a display panel 10, a gate driver 11, a source driver 12, and a control circuit 2.

The display panel 10 is an active matrix liquid crystal panel having a predetermined specification such as 8K, 4K, or 2K. As shown in FIG. 1, the display panel 10 includes a plurality of pixels 3, a plurality of gate lines GL, and a plurality of source lines SL. The display panel 10 includes, for example, a TFT (thin film transistor) substrate having a pixel electrode, a CF (color filter) substrate having a counter electrode, a liquid crystal layer sealed between both substrates, a polarizing plate, and the like.

The display panel 10 displays, for example, one color gradation of R, G, and B per pixel 3. In the display panel 10, the plurality of pixels 3 are arranged in a matrix. Hereinafter, the row direction of the matrix of the pixels 3 is referred to as a “horizontal direction” and is represented by a horizontal coordinate x. In addition, the column direction of the matrix of the pixels 3 is defined as “vertical direction” and is represented by the vertical coordinate y. In some cases, the positive side in the vertical direction is referred to as the lower side, and the negative side is referred to as the upper side.

The plurality of pixels 3 are provided with active element TFTs and the like. In the TFT of each pixel 3, the gate is connected to the gate line GL, and the source is connected to the source line SL (see FIG. 2). Details of the configuration of the pixel 3 will be described later.

Each gate line GL extends in the horizontal direction of the display panel 10 and is connected to one row of pixels 3 in the pixel 3 matrix. The plurality of gate lines GL are arranged side by side in the vertical direction of the display panel 10 corresponding to the vertical coordinate y of the connected pixel 3. The gate line GL is a signal line for selecting a pixel group having a common vertical coordinate y.

Each source line SL extends in the vertical direction of the display panel 10 and is connected to one column of pixels 3 in the pixel 3 matrix. The plurality of source lines SL are arranged side by side in the horizontal direction of the display panel 10 corresponding to the horizontal coordinate x of the connected pixel 3. The source line SL is a signal line that sequentially supplies a predetermined voltage to a pixel group having a common horizontal coordinate x.

The gate driving unit 11 includes an IC or the like to which a plurality of gate lines GL are connected. Under the control of the control circuit 2, the gate driving unit 11 outputs a signal for sequentially selecting a pixel group for one row corresponding to each vertical coordinate y in a predetermined frame period (for example, 1/60 seconds). To supply.

The source driver 12 is composed of an IC or the like to which a plurality of source lines SL are connected. The source driver 12 supplies a voltage corresponding to the gradation to be displayed to the pixel group in the selected row via the source line SL in synchronization with the operation of the gate driver 11 under the control of the control circuit 2. .

The control circuit 2 is composed of one or a plurality of semiconductor integrated circuits such as LSIs. The control circuit 2 generates various signals for controlling the operation timing of each part of the display device 1 as a timing controller. The control circuit 2 may control the overall operation of the display device 1.

For example, based on a video signal input from the outside, the control circuit 2 sequentially displays the gray level for one row in the frame unit video indicated by the video signal on the pixel group of each row so as to be displayed. And a control signal for the source driver 12 is generated. In addition to the control of the operation timings of the gate driving unit 11 and the source driving unit 12, the control circuit 2 performs predetermined video signal processing and the like. Details of the configuration of the control circuit 2 will be described later.

1-1. Pixel Structure of Display Panel Details of the configuration of the pixel 3 in the display panel 10 of the display device 1 will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration of the pixel 3 in the display panel 10 of the display device 1.

FIG. 2 shows the configuration of the pixel 3 having specific coordinates (x, y) on the display panel 10. For example, in a 4K, 2K RGB panel, the horizontal coordinate x of the pixel 3 is in the range of 1 to 11520 (= 3840 × 3), and the vertical coordinate y is in the range of 1 to 2160.

The pixel 3 includes a TFT 31 and a liquid crystal capacitor Clc as shown in FIG. In the TFT 31 of the pixel 3 at the coordinate (x, y), the gate is connected to the gate line GL (y) corresponding to the vertical coordinate y, the source is connected to the source line SL (x) corresponding to the horizontal coordinate x, and the drain. Is connected to one end (pixel electrode) of the liquid crystal capacitor Clc. The other end of the liquid crystal capacitor Clc is connected to a counter electrode in the display panel 10, for example.

The TFT 31 is turned on when the voltage applied to the gate based on a signal from the gate line GL (y) is equal to or higher than a predetermined threshold voltage, and turned off when the voltage is lower than the threshold voltage. The threshold voltage of the TFT 31 is, for example, 2 to 3V. The TFT 31 is an example of an active element connected to the gate line GL (y).

The liquid crystal capacitor Clc is composed of a pixel electrode, a counter electrode, and a liquid crystal layer, and changes the alignment state of the liquid crystal layer according to the charged voltage. The liquid crystal capacitor Clc charges or discharges charges based on the voltage of a signal input from the source signal line SL while the TFT 31 is on. The liquid crystal capacitor Clc holds a charging voltage obtained by charging / discharging before the TFT 31 is turned off while the TFT 31 is off.

As shown in FIG. 2, the pixel 3 has a parasitic capacitance Csd1 between the connected source line SL (x) and the pixel electrode, that is, between the source and drain of the TFT 31. In addition, the pixel 3 has a parasitic capacitance Csd2 between the adjacent source line SL (x + 1) and the pixel electrode. Each parasitic capacitance Csd is an example of a Csd parasitic capacitance between the source lines SL (x) and SL (x + 1) and the pixel 3, respectively. In order to reduce the capacitance value of such Csd parasitic capacitance, the pixel 3 may be provided with a CRE (Capacity Reduction Electrode) structure.

According to the pixel 3 configured as described above, when a voltage equal to or higher than the threshold voltage of the TFT 31 is applied from the gate line GL (y), the liquid crystal capacitor Clc can be charged and discharged, and the pixel 3 is selected. The The charging voltage for displaying the gradation of the corresponding pixel in the video is charged / discharged according to the voltage of the signal input from the source line SL (x) to the selected pixel 3.

1-2. Configuration of Control Circuit Details of the configuration of the control circuit 2 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the control circuit 2 in the display device 1.

As shown in FIG. 3, the control circuit 2 includes a reception unit 21, a gamma conversion unit 22, an overdrive conversion unit 23, a data correction unit 24, a dither processing unit 25, and a transmission unit 26. The control circuit 2 is an example of a control unit of the display device 1 in the present embodiment.

The receiving unit 21 is an input interface circuit according to a predetermined communication standard. The receiving unit 21 receives a video signal input from the outside. The external video signal includes video data indicating video for each frame, various synchronization signals, and the like.

The gamma conversion unit 22 executes gamma conversion processing for performing gamma correction on the video data in the received video signal.

The overdrive conversion unit 23 performs an overdrive conversion process on the video data after the gamma conversion process, for example. The overdrive conversion process is a process for converting the current video data with reference to the past video data in order to overshoot the pixels 3 of the display panel 10.

The data correction unit 24 performs arithmetic correction (Csd correction) for suppressing the influence of the Csd parasitic capacitance in the display panel 10 on the video data after the overdrive conversion processing, for example. The configuration of the data correction unit 24 in this embodiment will be described later.

The dither processing unit 25 performs dither processing for performing dithering on the video data corrected by the data correction unit 24 according to the number of colors that can be generated on the display panel 10.

The transmission unit 26 is an output interface circuit that conforms to a predetermined communication standard. The transmission unit 26 transmits the video data of the above various processing results to the source driving unit 12 of the display panel 10. The transmission unit 26 also outputs a control signal for the source driving unit 12, a control signal for the gate driving unit 11, a synchronization signal for synchronizing the operation timing of each unit, and the like.

The control circuit 2 includes hardware such as a dedicated electronic circuit and a reconfigurable electronic circuit designed to realize predetermined functions such as the gamma conversion unit 22, the overdrive conversion unit 23, the data correction unit 24, and the like. It may be a circuit. Further, the control circuit 2 may include a CPU or the like that realizes the various functions described above in cooperation with software. The control circuit 2 may be composed of various semiconductor integrated circuits such as a CPU, MPU, microcomputer, DSP, FPGA, and ASIC.

1-3. Data Correction Unit The configuration of the data correction unit 24 in this embodiment will be described with reference to FIGS.

FIG. 4 is a block diagram showing the configuration of the data correction unit 24 in the present embodiment. The data correction unit 24 includes a frame memory 40 and a Csd correction circuit 4 as shown in FIG.

In this embodiment, the video data D (n) input to the Csd correction circuit 4 after being delayed by one frame via the frame memory 40 in the data correction unit 24 is handled as the current video data. The video data D (n + 1) input to the Csd correction circuit 4 without going through the frame memory 40 is relatively referred to as future video data for one frame.

In the present embodiment, the frame memory 40 stores one frame of video data D (n) without being particularly compressed. Thereby, the calculation correction in the data correction unit 24 can be performed without impairing the display quality of the video data D (n) handled as the current frame (current frame).

The Csd correction circuit 4 reads the video data D (n) of the current frame from the frame memory 40, refers to the video data D (n + 1) of the next frame, and performs arithmetic correction on the video data D (n) of the current frame. Execute. Thus, the data correction unit 24 outputs the corrected video data O (n) of the current frame from the Csd correction circuit 4. FIG. 5 shows a configuration example of the Csd correction circuit 4 in this embodiment.

The Csd correction circuit 4 illustrated in FIG. 5 includes a

coefficient multipliers

41 and 42,

adders

43, 51, and 52, a subtractor 44, a line memory 45, a clear determination unit 46, and flip-

flops

47 and 48. And

function calculation units

49 and 50.

The Csd correction circuit 4 inputs one frame of video data D (n) for each gradation data D (x, y, n). The gradation data D (x, y, n) is data indicating the gradation for each pixel in the video indicated by the video data D (n), and the pixel at the corresponding coordinate (x, y) on the display panel 10. The voltage supplied to 3 is specified. The gradation data D (x, y, n) can be set to a positive value and a negative value (absolute values are gradation values) according to a driving method such as frame inversion. The gradation data D (x, y, n) is a vertical coordinate corresponding to the outside of the display panel 10 in order to define the voltage of the source line SL (x) during a vertical blanking period (described later), for example. You may have y (refer FIG. 7).

The Csd correction circuit 4 uses the horizontal direction (x) as the main scanning direction and the vertical direction (x) in a predetermined number of gradation data {D (x, y, n)} included in one frame of video data D (n). Each gradation data D (x, y, n) is input so that y) is two-dimensionally scanned in the sub-scanning direction. Further, the Csd correction circuit 4 inputs the current frame gradation data D (x, y, n) and the next frame gradation data D (x, y, n + 1) in synchronization with a predetermined synchronization signal or the like. To do.

The coefficient multipliers 41 and 42 include LUTs for calculating later-described coefficients f1 and f2 (or multiplication values of the coefficients f1 and f2 and the gradation data). The coefficient multiplication unit 41 refers to the LUT based on the gradation data D (x, y, n) of the current frame and outputs a multiplication value f1 · D (x, y, n). Similarly, the coefficient multiplier 42 outputs a multiplication value f2 · D (x, y, n + 1) based on the gradation data D (x, y, n + 1) of the next frame. For example, the

coefficient multipliers

41 and 42 output the multiplication value “0” based on the input value “0”.

The adder 43 adds the multiplication value f2 · D (x, y, n + 1) of the coefficient multiplier 42 to the read value R (x) from the line memory 45. The subtracter 44 subtracts the multiplication value f1 · D (x, y, n) of the coefficient multiplier 41 from the output value of the adder 42. The calculation result (output value of the subtractor 44) corresponds to an integrated value A (x, y, n) described later. The Csd correction circuit 4 writes the integrated value A (x, y, n) as the calculation result in the line memory 45 as the write value W (x).

The line memory 45 stores a write value {W (x) | x = 1 to X} corresponding to one horizontal line of the pixel 3 in the display panel 10 (X is the maximum value of the horizontal coordinate x). Each write value W (x) is read as a read value R (x) as appropriate. The clear determination unit 46 generates a clear signal for erasing information stored in the line memory 45 based on, for example, a trigger signal at the time of power activation.

The flip-flop 47 holds the integrated value A (x, y, n) of the calculation result. The flip-flop 48 holds the gradation data D (x, y, n) of the current frame. Each of the flip-

flops

47 and 48 delays each data by one operation cycle (corresponding to the difference “1” of the horizontal coordinate x).

The

function calculators

49 and 50 include an LUT for calculating functions f3 and f4 described later. The function calculation unit 49 outputs the calculation value of the function f3 based on the delayed gradation data D (x-1, y, n) and the integrated value A (x-1, y, n). The function calculation unit f4 outputs the calculation value of the function f4 based on the delayed gradation data D (x-1, y, n) and the integrated value A (x, y, n) without delay. For example, when the input data is “0”, the

function calculation units

49 and 50 are set so that the calculation values of the functions f3 and f4 are “0”.

The

adders

51 and 52 add the calculated value of the function f3 and the calculated value of the function f4 to the delayed gradation data D (x-1, y, n), and the gradation data D (x-1, The corrected gradation data O (x-1, y, n) for y, n) is output.

According to the Csd correction circuit 4 configured as described above, calculations of equations (2) to (5) described later are executed, and calculation correction of the gradation data D (x, y, n) is realized.

2. Operation The operation of the display device 1 configured as described above will be described below.

2-1. Vertical Shadow First, vertical shadow that may occur in the display device will be described with reference to FIG. FIG. 6 is a diagram for explaining vertical shadows in the display panel.

FIG. 6A illustrates one frame of video data D (n). FIG. 6B shows a display example of the display panel when a vertical shadow occurs in the video display based on the video data D (n) of FIG.

The video data D (n) in FIG. 6A includes a background area Rb having a predetermined gradation and an object area Ra surrounded by the background area Rb. The object area Ra has a gradation different from that of the background area Rb. When such video data D (n) is input to the display panel, as shown in FIG. 6B, the gradation (or color) shifted from the background region Rb on the upper and lower sides in the vertical direction of the object region Ra. In some cases, regions Rb1 and Rb2, that is, “vertical shadows” appear.

In the vertical shadow as described above, the pixel 3 (FIG. 1) in the regions Rb1 and Rb2 and the pixel 3 in the object region Ra are connected to the same source line SL. This is caused by Csd parasitic capacitance. In order to suppress the vertical shadow, for example, if a CRE structure that sufficiently reduces the capacitance values of the parasitic capacitances Csd1 and Csd2 (FIG. 2) is provided in each pixel 3, the transmittance of the pixel 3 decreases, Image quality can be degraded. For example, in the case of an 8K specification display panel, the size of the pixel 3 is small, and a decrease in transmittance may be a serious problem.

Therefore, in the present embodiment, the data correction unit 24 in the control circuit 2 of the display device 1 performs calculation correction (that is, Csd correction) on the video data D (n) so as to suppress the influence of the Csd parasitic capacitance. Hereinafter, details of the operation of the display device 1 according to the present embodiment will be described.

2-2. Regarding Csd Correction A calculation method of Csd correction by the data correction unit 24 of the display device 1 according to the present embodiment will be described with reference to FIG. FIG. 7 is a diagram for explaining a calculation method of Csd correction by the data correction unit 24.

FIG. 7 illustrates the operation timing of video display by the display device 1 for the video data D (n) and D (n + 1) of two consecutive frames. As shown in FIG. 7, the frame period T1 for displaying one frame of video includes a vertical display period T2 and a vertical blanking period T3.

The vertical display period T2 is a period during which one frame of video is displayed by selecting pixel groups in all rows on the display panel 10 (FIG. 1). The vertical blanking period T3 is a period in which a predetermined interval is provided between the end of the vertical display period T2 of the current frame and the start of the next frame. For example, the vertical display period T2 includes 2160 rows of charging periods for one row of pixel groups. The vertical blanking period T3 corresponds to a charging period for 90 rows, for example.

In the example of FIG. 7, the display device 1 starts displaying an image using the video data D (n) of the nth frame from time t <b> 1 under the control of the control circuit 2 (FIG. 1). During the vertical display period T2 from time t1, the control circuit 2 performs gradation data D (1, y, n) to D (X, y, n) for each row in the video data D (n) of the nth frame. Based on the above, the pixels 3 (liquid crystal capacitors Clc) in the corresponding rows in order from y = 1 are charged. Each pixel 3 displays the gradation indicated by the gradation data D (x, y, n) by holding the charging voltage corresponding to the gradation data D (x, y, n).

For example, the pixel 3 at the point P (x, y) having the coordinates (x, y) on the display panel 10 (FIG. 1) is the video data of the nth frame at time t2 within the vertical display period T2 from time t1. Charging is performed based on the corresponding gradation data D (x, y, n) in D (n). The pixel 3 at the charged point P (x, y) is in the period Tp for one frame until the time t3 when the next (n + 1) frame gradation data D (x, y, n + 1) is charged. The charging voltage is held so as to display the gradation indicated by the gradation data D (x, y, n) of the nth frame.

The source line SL (x) to which the pixel 3 at the point P (x, y) is connected in the period Tp corresponds to the video data D (n) and D (n + 1) of the nth frame or the (n + 1) th frame. A voltage based on the gradation data of the column to be applied is sequentially applied. At this time, parasitic capacitances Csd1 and Csd2 (FIG. 2) between the source line SL (x) and the adjacent source line SL (x + 1) and the pixel 3 at the point P (x, y) are connected to each source line SL (x). , SL (x + 1), the charging voltage of the pixel 3 can be varied depending on the voltage applied to it.

From the above, the present inventor shows that the influence of the Csd parasitic capacitance on the charging voltage of the pixel 3 is applied to the source line SL (x) corresponding to the gradation data D (x, y, n) of each column. It was thought that it can be estimated by integrating the applied voltage during Tp. Therefore, in the present embodiment, an integrated value (A (x, y) indicating the integration of the voltages to be sequentially applied to the common source line SL (x) during a period Tp for one future frame after the present time. , N)) is obtained and used for Csd correction of the current gradation data D (x, y, n).

2-2-1. About the theoretical formula of the integrated value The theoretical formula (1) of the integrated value A (x, y, n) employed in the present embodiment is shown below.

Here, the point P (x, y) in FIG. 7 corresponds to the time point at which the integrated value A (x, y, n) is to be calculated. As shown in the above equation (1), the integrated value A (x, y, n) in this embodiment is a floor for one frame having a horizontal coordinate x in common with the point P (x, y) between two consecutive frames. It is obtained by integrating key data D (x, y + 1, n) to D (x, y-1, n + 1).

In Equation (1), the first term A1 represents the integral amount of the voltage applied to the source line SL (x) after charging the pixel 3 at the point P (x, y) in the current frame (n frame). For the integration of the first term A1, the gradation data {D (x, y1, n) | y1 = y + 1 to Y} within a range larger than the vertical coordinate y of the point P (x, y) is multiplied by the coefficient f1. Thus, the sum is calculated by weighted addition. The upper limit value Y of the sum corresponds to the end of the vertical blanking period T3, and is Y = 2250 (= 2160 + 90), for example. The coefficient f1 is, for example, a function of the coordinates (x, y) and / or coordinates (x, y1) of the point P (x, y), and represents a variation in the display surface of the display panel 10. The coefficient f1 includes a component that converts gradation data into a voltage.

The second term A2 represents the integral amount of the voltage applied to the source line SL (x) before the start of charging the pixel 3 at the point P (x, y) in the next frame ((n + 1) frame). The integration of the second term A2 is performed on the coefficient f2 for the gradation data {D (x, y2, n + 1) | y2 = 1 to y−1} within a range smaller than the vertical coordinate y of the point P (x, y). Calculated by weighted addition based on. The coefficient f2 is a function similar to the coefficient f1, for example.

For example, the integrated value A (x, 1, n) when y = 1 is A2 = 0 because the pixel 3 at the point P (x, y) is charged at the start of the next frame, and the first term A1 Is calculated by Similarly, the integrated value A (x, Y, n) when y = Y is A1 = 0 and is calculated by the second term A2. Since it is considered that the pixel 3 is not affected by the Csd parasitic capacitance during the charging of the pixel 3 itself at the point P (x, y), the integrated value A (x, y, n) of Expression (1) Then, the gradation data D (x, y, n) of the point P (x, y) is not included in the integration target.

2-2-2. About the calculation formula of Csd correction Using the integrated value A (x, y, n) as described above, the data correction unit 24 of the display device 1 according to the present embodiment uses the gradation data D (x, y, n) is corrected. A calculation formula for Csd correction by the data correction unit 24 is shown below.

As shown in the equation (2), the corrected gradation data O (x, y, n) is corrected to the gradation data D (x, y, n) (before correction) by the correction amount ΔD (x, y, n). determined by adding n). Formula (3) is a formula for calculating the correction amount ΔD (x, y, n) based on the above integrated value A (x, y, n). The correction amount ΔD (x, y, n) for the gradation data D (x, y, n) at the point P (x, y) is the sum of the first term and the second term on the right side of Equation (3). Calculated.

The first term of the equation (3) is the gradation data D (x, y, n) of the point P (x, y) and the integrated value A (x, y, n) of the point P (x, y). It is expressed by a function f3 having an effective value A (x, y, n) / (Y-1) as an argument. The function f3 is parasitic on the liquid crystal capacitance Clc of the pixel 3 in order to correct the influence of the parasitic capacitance Csd1 (FIG. 2) due to the source line SL (x) connected to the pixel 3 itself at the point P (x, y). It is set according to the ratio with the capacitance Csd1. The function f3 includes a component that converts voltage into gradation data.

The second term of the expression (3) includes the gradation value of the gradation data D (x, y, n) at the point P (x, y) and the point P ′ (x + 1) adjacent to the point P (x, y). , Y) is represented by a function f4 having an effective value A (x + 1, y, n) / (Y-1) of an integrated value A (x + 1, y, n) as an argument. The function f4 has a ratio between the liquid crystal capacitance Clc and the parasitic capacitance Csd2 of the pixel 3 in order to correct the influence of the parasitic capacitance Csd2 due to the source line SL (x + 1) adjacent to the pixel 3 at the point P (x, y). Set accordingly. The function f4 includes a component that converts a voltage into gradation data.

The functions f3 and f4 of the first and second terms in the expression (3) are set independently so as to correct the influences of the separate parasitic capacitances Csd1 and Csd2, respectively. Each function f3, f4 may be a function depending on coordinates (x, y) in consideration of variations in the display surface of the display panel 10 and the like, similar to the above-described coefficients f1, f2.

Further, since the capacitance value of the liquid crystal capacitance Clc in the pixel 3 varies according to the charging voltage, the functions f3 and f4 are represented by gradation data D (x, y, n) that defines the charging voltage of the liquid crystal capacitance Clc. It depends.

Further, the influence of the Csd parasitic capacitance varies even when the video displayed in the vertical display period T2 is the same when the length of the vertical blanking period T3 is different. Therefore, in consideration of the influence of the length of the vertical blanking period T3, the effective value A (x, y1, t) / (Y−) obtained by dividing the integrated value A (x, y1, t) by (Y−1). 1) is used as an argument of the functions f3 and f4. Thereby, for example, even when the length (Y value) of the vertical blanking period T3 differs between a 60 Hz video signal and a 50 Hz video signal, the influence of the Csd parasitic capacitance is corrected substantially in the same manner. can do.

When the correction amount ΔD (x, y, n) as described above is obtained for each pixel 3, in this embodiment, the integrated value A (() is obtained using a recurrence formula as shown in equations (4) and (5). x, y, n) is calculated. Hereinafter, the recurrence formula of the integrated value A (x, y, n) will be described.

2-2-3. Regarding the recurrence formula of the integrated value In this embodiment, the data correction unit 24 calculates the integrated value A (x, y, n) for the future for one frame from the charging time of each pixel 3, and calculates the floor of each pixel 3. The tone data D (x, y, n) is corrected sequentially. At this time, the calculation for summing up the grayscale data D (x, y + 1, n) to D (x, y-1, n + 1) for one column as in the theoretical formula (1) is independent for all the pixels 3. In such a calculation method, the circuit scale can be enormous. Therefore, in this embodiment, a recurrence formula as shown in formulas (4) and (5) is adopted in order to obtain each integrated value A (x, y).

Equation (4) is an equation obtained by equivalently transforming Equation (1) into a recurrence form when y> 1. Equation (5) is an equation obtained by equivalently modifying Equation (1) in the same manner as Equation (4) when y = 1. When the equations (4) and (5) are employed, the coefficient f1 and the coefficient f2 are set to have the same function form in order to prevent divergence of the recurrence formula repeated calculation.

The right side of the equation (4) is the integrated value A (x, y−1) of the point P ″ (x, y−1) where the horizontal coordinate x is the same as the point P (x, y) and the vertical coordinate y is smaller by 1. , N). Since the pixel 3 at the point P ″ (x, y−1) is charged one row before (past) the pixel 3 at the point P (x, y), the point P ( When calculating the integrated value A (x, y, n) of x, y), the integrated value A (x, y-1, n) of the point P ″ (x, y−1) can be used.

Specifically, when y> 1, the data correction unit 24 applies the second value of Expression (4) to the integrated value A (x, y−1, n) of the point P ″ (x, y−1). The term f1 · D (x, y, n) is subtracted and the third term f2 · D (x, y−1, n + 1) is added, and the second term f1 · D (x, y, n) is This is the contribution of the gradation data D (x, y, n) of the point P (x, y) of the current frame in the integrated value A (x, y-1, n) (see A1 in the equation (1)). The third term f2 · D (x, y−1, n + 1) is a contribution of the gradation data D (x, y−1, n + 1) of the point P ″ (x, y−1) of the next frame (formula ( 1) A2).

When y = 1, instead of the integrated value A (x, y−1, n) at the point P ″ (x, y−1), the integrated value A (x at y = Y one frame before) , Y, n−1), the integrated value A (x, 1, n) can be calculated in the same manner as described above (see equation (5), FIG. 7).

According to the equations (4) and (5) as described above, the integrated values A (1, y−1, n) to A (X, y−1, n) for one row are stored in the line memory 45 (FIG. 5). Thus, the integrated value A (x, y, n) can be calculated sequentially from y = 1 by a simple calculation, and an increase in circuit area can be suppressed.

2-2-4. Initial Display Mode In order to make it easy to obtain the initial value of the recurrence formula as described above, in this embodiment, all the pixels 3 are displayed in the display device 1 during a predetermined period (for example, one frame or more) after the control circuit 2 is turned on. An initial display mode for displaying a black screen image having a gradation value of “0” is used. Hereinafter, an operation using the initial display mode in the display device 1 will be described.

When the display device 1 is activated, the clear determination unit 46 (FIG. 5) in the Csd correction circuit 4 generates a clear signal and erases the information stored in the line memory 45. An initial value “0” is set in the line memory 45.

In the display device 1, the control circuit 2 (FIG. 1) operates in the initial display mode for a predetermined period (for example, one frame or more) from when the power is turned on. In the initial display mode, the control circuit 2 generates video data in which all grayscale data has a grayscale value “0” regardless of the video signal from the outside, and inputs the video data to the data correction unit 24.

In this embodiment, the coefficient multipliers 41 and 42 (FIG. 5) in the data correction unit 24 output data of the output value “0” based on the input value “0”. Each of the

function calculators

49 and 50 also outputs an output value “0” based on the input value “0”. As described above, the gradation data output from the data correction unit 24 during the continuation of the initial display mode has the gradation value “0”, and a black screen image is displayed on the display device 1.

When the initial display mode is canceled, the control circuit 2 operates in the normal display mode, and inputs video data corresponding to the video signal from the outside to the data correction unit 24. Hereinafter, the video data indicating the black screen of the last one frame when the initial display mode is canceled is referred to as video data D (1) with n = 1. In this case, the gradation data D (x, y, 1) with n = 1 all have gradation values “0”, and the gradation data D (x, y, 2) with n = 2 corresponds to the video signal. It has a gradation value.

In the data correction unit 24, the Csd correction circuit 4 (FIG. 5) sequentially starts from the gradation data D (x, 1, 1) of the first row (y = 1) in the video data D (1) of n = 1. The calculation correction according to the equations (2) to (5) is executed. According to the equation (5), the integrated value A (x, 1,1) corresponding to the gradation data D (x, 1,1) in the first row is calculated by the following equation (11).

A (x, 1,1)
= A (x, Y, 0) -f1 · D (x, 1,1) + f2 · D (x, Y, 1) (11)
In the above equation (11), the first term A (x, Y, 0) on the right side is an integrated value of each gradation data D (x, y, 1) with n = 1 (see A2 in FIG. 7), and the line It matches the initial value “0” of the memory 45. Since the second term and the third term on the right side are also “0”, the integrated value A (x, 1, 1) = 0 when n = 1 and y = 1. In this case, the correction amount ΔD (x, 1,1) = 0, and the corrected gradation data O (x, 1,1) = 0. In the line memory 45, after the integrated value A (x, Y, 0) (= 0) is read, a new integrated value A (x, 1, 1) (= 0) is written.

Next, the Csd correction circuit 4 executes a correction operation on the second row (y = 2) gradation data D (x, 2, 1) in the video data D (1) with n = 1. According to the equation (4), the integrated value A (x, 2, 1) corresponding to the gradation data D (x, 2, 1) in the second row is calculated by the following equation (12).

A (x, 2,1)
= A (x, 1,1) −f1 · D (x, 2,1) + f2 · D (x, 1,2) (12)
In the above equation (12), the first and second terms on the right side are “0” as in the case of the first row, while the third term in the above equation (12) is the floor in the normal display mode. It has a value based on the key data D (x, 1, 2). Therefore, the integrated value A (x, 2, 1) where n = 1 and y = 2 is easily calculated by the calculation of the third term of the above equation (12).

The Csd correction circuit 4 obtains the correction amount ΔD (x, 2, 1) based on the calculation result of the integrated value A (x, 2, 1) as described above, and the corrected gradation data O (x, 2, 1). 1) is calculated. In the line memory 45, after the integrated value A (x, 1, 1) (= 0) is read, a new integrated value A (x, 2, 1) is written. The written integrated value A (x, 2, 1) is used for correction calculation of the gradation data D (x, 3, 1) with y = 3. The correction calculation in y = 3 and subsequent frames and subsequent frames is sequentially executed in the same manner as described above.

3. Summary As described above, the display device 1 according to the present embodiment includes the plurality of pixels 3, the plurality of gate lines GL, the plurality of source lines SL, and the control circuit 2. The plurality of pixels 3 are arranged in a matrix. The plurality of gate lines GL are connected to a group of pixels 3 arranged in the row direction of the matrix of pixels 3, and sequentially select the group of pixels 3 in each row at a predetermined frame period T1. The plurality of source lines SL are connected to a group of pixels 3 arranged in the column direction of the matrix of pixels 3 and supply a voltage corresponding to a predetermined gradation to the group of pixels 3 in a selected row. Based on the gradation data D (x, y, n) indicating the gradation included in one frame of video, the control circuit 2 sequentially displays the gradation for one row in the video on the group of pixels 3 in each row. Control the timing. In the data correction unit 24, the control circuit 2 uses the source line SL (connected to the pixel 3 in the period Tp for one future frame with reference to the pixel 3 to be displayed (point P (x, y)) as a reference. Based on the integrated value A (x, y, n) indicating the integration of the voltage applied to x), the gradation data D (x, y, n) indicating the gradation to be displayed on the pixel 3 is corrected.

In the data correction unit 24, the control circuit 2 is connected to the same source line as the pixel 3 in a period of one future frame with the pixel 3 to be displayed (point P (x, y)) as a reference. Based on the integrated value A (x, y, n) indicating the total sum of the gradation data indicating the gradation to be displayed on the other pixel 3, the gradation data D (x, y) indicating the gradation to be displayed on the pixel 3 is displayed. , N) may be corrected. In this case, the coefficient f1 and the coefficient f2 in the Csd correction circuit 4 do not include a component that converts gradation data into voltage, and the function f3 and the function f4 do not include a component that converts voltage into gradation data. The output values of the coefficient multipliers 41 and 42 (see FIG. 5), that is, the multiplication value f1 · D (x, y, n) and the multiplication value f2 · D (x, y, n + 1) are displayed on the display panel 10, for example. The gradation data is multiplied by a coefficient for taking into account in-plane variation (specifically, a difference in time constant at each position in the display surface).

According to the display device 1 described above, with reference to the pixel 3 at the point P (x, y), the gradation data D (x, y, n) for the pixel 3 is the source line SL (x ) Is integrated according to the voltage integration or the sum of the gradation data. Thereby, it is possible to suppress the influence of the Csd parasitic capacitance such as the vertical shadow and the gradation inclination when the video is displayed on the display device 1.

In the present embodiment, the control circuit 2 (the data correction unit 24 thereof) has gradation data D (showing gradation to be displayed on another pixel 3 connected to the same source line SL (x) as the pixel 3 to be displayed. Based on x, y + 1, n) to D (x, y-1, n + 1), an integrated value A (x, y, n) is calculated (formula (1)). Thus, the integrated value A (x, y, n) for suppressing the influence of the Csd parasitic capacitance is obtained based on the gradation data D (x, y + 1, n) to D (x, y-1, n + 1). Can do.

In the present embodiment, the control circuit 2 uses the calculation result of the integrated value A (x, y−1, n) for the pixel 3 obtained by correcting the gradation data D (x, y−1, n). Based on the recurrence formulas (4) and (5), an integrated value A (x, y, n) relating to the pixel 3 in the next row connected to the same source line SL (x) as the pixel 3 is calculated. Thereby, the integrated value A (x, y, n) can be calculated efficiently, and Csd correction can be easily realized.

Further, in the present embodiment, the data correction unit 24 of the control circuit 2 has gradation data D (x, y + 1, n) to D (x, x) indicating gradations in the video of the nth frame and the (n + 1) th frame. An integrated value A (x, y, n) based on y−1, n + 1) is calculated, and the calculated integrated value A (x, y, n) is gradation data D indicating the gradation in the image of the nth frame. Used to correct (x, y, n) (Equations (3) to (5)). Thereby, the integrated value A (x, y, n) based on the future video data is obtained, and the corrected gradation data O (x, y, n) can be obtained as a complete solution.

In the present embodiment, the control circuit 2 includes an integrated value A (x + 1, indicating integration of a voltage applied to the source line SL (x + 1) adjacent to the pixel 3 to be displayed in a period Tp for one future frame. The gradation data D (x, y, n) is corrected using y, n) (see f4 in equation (3)). Thereby, the influence of the Csd parasitic capacitance due to the source lines SL (x) and SL (x + 1) in the vicinity of the pixel 3 can be suppressed.

In this embodiment, the frame cycle T1 includes a predetermined vertical blanking period T3. Based on the effective value A (x, y, n) / (Y−1) of the integrated value in the period Tp for one frame including the vertical blanking period T3, the control circuit 2 performs gradation data D (x, y, n) is corrected (formula (3)). Thereby, Csd correction can be appropriately performed according to the setting of the vertical blanking period T3.

(Embodiment 2)
In the first embodiment, the integrated value based on future video data is obtained and Csd correction is performed. In the second embodiment, a display device that performs Csd correction by approximately obtaining the integrated value using past video data will be described.

1. Outline An outline of a display device according to the present embodiment will be described with reference to FIG. FIG. 8 is a diagram for explaining the outline of the data correction unit 24A of the display device 1 according to the second embodiment.

FIG. 8A shows an implementation example of the data correction unit 24 of the first embodiment. FIG. 8B shows an example of the data correction unit 24A (including the overdrive conversion unit 23) in the second embodiment.

As shown in FIG. 8A, the data correction unit 24 according to the first embodiment is mounted, for example, at the subsequent stage of the overdrive conversion unit 23. The overdrive conversion unit 23 includes a frame memory 60 that stores one frame of video data D (n−1), and an overdrive conversion circuit 6 that performs overdrive conversion. In the overdrive conversion unit 23, overdrive conversion for the video data D (n) of the current frame is executed with reference to the past video data D (n-1) for one frame via the frame memory 60. .

On the other hand, the Csd correction in the data correction unit 24 of the first embodiment treats the video data D (n−1) that has passed through the frame memory 40 as the current video data, and the future video for one frame that does not pass through the frame memory 40. It is executed with reference to data D (n). For this reason, in the data correction unit 24 and the overdrive conversion unit 23 of the first embodiment, the video data to be referenced is a separate frame, and

separate frame memories

40 and 60 are required. Further, since the data correction unit 24 of the first embodiment handles the video data D (n−1) that has passed through the frame memory 40 as the current video data, a frame delay of video display occurs.

Therefore, in the Csd correction circuit 4A of the data correction unit 24A in the present embodiment, the Csd correction similar to that in the first embodiment is performed approximately using the past video data D (n−1). As a result, as shown in FIG. 8B, the frame memory 60 can be shared by the Csd correction circuit 4A and the overdrive conversion circuit 6, and the circuit scale can be reduced. Further, it is possible to avoid frame delay in the video display of the display device 1. The data correction unit 24A in the present embodiment includes an overdrive conversion unit 23 together with the Csd correction circuit 4A. Details of the data correction unit 24A in the present embodiment will be described below.

2. Details FIG. 9 is a block diagram illustrating a configuration example of the data correction unit 24A in the present embodiment. In this example, the data correction unit 24A includes a Csd correction circuit 4A, an overdrive conversion circuit 6 corresponding to the above-described overdrive conversion unit 23, a frame memory 60,

compressors

61 and 63, and

decompressors

62 and 64. including. In the data correction unit 24A in the present embodiment, as described above, in the data correction unit 24A in the present embodiment, the Csd correction circuit 4A and the overdrive conversion circuit 6 share the frame memory 60. In the example of FIG. 9, the video data D (n) is compressed and expanded as a more practical example.

Specifically, the compressor 61 compresses the video data D (n) with a predetermined calculation formula and records it in the frame memory 60. The decompressor 62 reads out the video data compressed and recorded in the frame memory 60, expands it with a calculation formula corresponding to the above calculation formula, and exceeds the obtained past video data D ′ (n−1). Output to the drive conversion circuit 6. Thereby, the circuit scale of the frame memory 60 can be reduced.

Further, the compressor 63 compresses the video data D (n) of the current frame with the same calculation formula as the compressor 61, for example. The decompressor 64 expands the compressed video data D (n) of the current frame, for example, with the same calculation formula as the decompressor 62, and converts the obtained current video data D ′ (n) to the overdrive conversion circuit 6. Output to.

The overdrive conversion circuit 6 refers to the video data D ′ (n) and D ′ (n−1) after compression and decompression of each frame, and the video data D (n) of the current frame that is not particularly compressed. Perform overdrive conversion for. Thereby, in overdrive conversion, it is possible to suppress deterioration in display quality due to data compression.

In the present embodiment, the Csd correction circuit 4A refers to the video data D ′ (n) and D ′ (n−1) after compression and decompression of each frame in the same manner as the overdrive conversion circuit 6 described above. Csd correction of the video data D (n) of the frame is executed. Thereby, also in Csd correction | amendment, the fall of the display quality by data compression can be suppressed.

FIG. 10 is a block diagram showing a configuration example of the Csd correction circuit 4A in the present embodiment.

The Csd correction circuit 4A illustrated in FIG. 10 has the same configuration as that of the Csd correction circuit 4 (FIG. 5) of the first embodiment, and uses the past gradation data D ′ (x, y, n−1) as a coefficient multiplier 41A. And the current gradation data D ′ (x, y, n) is input to the coefficient multiplier 42A. The gradation data D ′ (x, y, n−1) and D ′ (x, y, n) are included in the compressed and decompressed video data D ′ (n−1) and D ′ (n), respectively. .

According to the Csd correction circuit 4A of this example, calculation correction based on the following equations (21) to (23) is realized.

Expression (21) is a calculation expression of the correction amount ΔD (x, y, n) in the present embodiment. Expressions (22) and (23) are recurrence expressions for obtaining the integrated value A ′ (x, y, n−1) in the present embodiment.

The correction amount ΔD (x, y, n) in the first embodiment is obtained by integrating the future gradation data D (x, y, n) after the present time into the arguments of the functions f3 and f4 as shown in the equation (3). The value A (x, y, n) was used. The correction amount ΔD (x, y, n) in the present embodiment is an integrated value from the time point one frame before, instead of the above integrated value A (x, y, n), as shown in equation (21). A ′ (x, y, n−1) is used.

Further, the integrated value A ′ (x, y, n−1) in the present embodiment is the gradation data D ′ (x, y, n−1), D ′ (x, y, n) after compression and decompression. Is obtained by integrating in the same manner as in the first embodiment (see formula (1)). Although the frame number n is shifted in the equations (22) and (23), the recurrence formula of the integrated value A ′ (x, y, n−1) is the same as that in the first embodiment (equation ( 4) and (5)).

Also, when Csd correction is started in the Csd correction circuit 4A based on the equations (22) and (23), for example, the initial display mode can be used as in the first embodiment.

As described above, in this embodiment, the integrated value A ′ (x, y, n−1) from the time point one frame before is used as the voltage applied to the source line SL during the period of one frame in the future. Csd correction of each gradation data D (x, y, n) is performed using it as an approximate value of an integrated value indicating integration. That is, an error may occur that the correction amount ΔD (x, y, n) is delayed by one frame compared to the first embodiment. However, such an error is not particularly problematic from the following viewpoint. it is conceivable that.

That is, for example, when a still image is displayed on the display device 1, the above error does not occur, and Csd correction of each gradation data D (x, y, n) can be appropriately performed. Even in the case of a moving image, it takes time to reflect the gradation output from the control circuit 2 due to the response speed of the liquid crystal capacitance Clc in the pixel 3. Further, in general, the identification accuracy of luminance and chromaticity is rougher in the case of a moving image than in a still image. In general, the influence of the Csd parasitic capacitance is small enough to ignore the error as described above.

From the same viewpoint as described above, it is practically sufficient to use the gradation data D ′ (x, y, n−1) and D ′ (x, y, n) after compression and decompression in the Csd correction. In addition, the influence of the Csd parasitic capacitance can be suppressed with high accuracy.

3. Summary As described above, in the display device 1 according to the present embodiment, the data correction unit 24A of the control circuit 2 performs the gradation data D () indicating the gradation in the video of the (n−1) th frame and the nth frame. x, y + 1, n−1) to D (x, y−1, n) based on the integrated value A (x, y, n−1) are calculated, and the calculated integrated value A (x, y, n−1) is calculated. ) Is used to correct the gradation data D (x, y, n) indicating the gradation in the image of the nth frame (formulas (21) to (23)). As a result, a future integrated value for Csd correction is approximately obtained from past gradation data D (x, y + 1, n) to D (x, y-1, n), and the frame delay due to Csd correction is obtained. Can be avoided.

In the present embodiment, the display device 1 further includes a frame memory 60 that stores the video data D (n−1) of the (n−1) th frame. In the overdrive conversion circuit 6, the control circuit 2 refers to the video data D (n-1) stored in the frame memory 60 and performs predetermined overdrive conversion on the video data D (n) of the nth frame. . In the Csd correction circuit 4A, the control circuit 2 refers to the video data D (n−1) stored in the frame memory 60 to calculate the integrated value A (x, y, n−1), and calculates the calculated integrated value. A (x, y, n-1) is used for correction of the gradation data D (x, y, n). Thereby, the frame memory 60 can be shared by overdrive conversion and Csd correction, and an increase in circuit area for Csd correction can be suppressed.

Further, in the present embodiment, the frame memory 60 stores the compressed video data D (n−1). The control circuit 2 includes data D ′ (n−1) obtained by developing the video data stored in the frame memory 60, and data D ′ (n) obtained by compressing and developing the video data D (n) of the nth frame. The integrated value A ′ (x, y, n−1) is calculated based on the above, and the calculated integrated value A ′ (x, y, n−1) is used for correcting the gradation data D (x, y, n). . Thereby, the influence of the Csd parasitic capacitance can be suppressed with high accuracy while reducing the circuit scale of the frame memory 60.

As described above, specific embodiments and modifications of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. it can. For example, a combination of the contents of the individual embodiments described above may be used as an embodiment of the present invention.

Claims

A plurality of pixels arranged in a matrix;
A plurality of gate lines connected to a pixel group arranged in a row direction of the matrix of pixels, and sequentially selecting the pixel group of each row at a predetermined frame period;
A plurality of source lines connected to a pixel group arranged in a column direction of the pixel matrix and supplying a voltage corresponding to a predetermined gradation to the pixel group of the selected row;
A control unit for controlling the timing for sequentially displaying the gray levels for one row in the video on the pixel group of each row based on the gray level data indicating the gray level included in the video of one frame;
The control unit is configured to integrate a voltage applied to a source line connected to the pixel in a future one frame period with the display target pixel as a reference, or to supply the same source as the pixel in a future one frame period. A display device that corrects gradation data indicating a gradation to be displayed on a pixel based on an integrated value indicating a total sum of gradation data indicating a gradation to be displayed on another pixel connected to a line.
The display device according to claim 1, wherein the control unit calculates the integrated value based on gradation data indicating a gradation to be displayed on another pixel connected to the same source line as the pixel to be displayed.
The control unit uses the calculation result of the integrated value related to the pixel whose grayscale data is corrected to calculate the integrated value related to the pixel in the next row connected to the same source line as the pixel based on a predetermined recurrence formula. The display device according to claim 2 to calculate.
The control unit calculates an integrated value based on gradation data indicating gradation in the video of the nth frame and the (n + 1) th frame, and corrects gradation data indicating gradation in the video of the nth frame. The display device according to claim 2 or 3, which is used for the display.
The control unit calculates an integrated value based on gradation data indicating gradation in the video of the (n-1) th frame and the nth frame, and represents gradation data indicating gradation in the video of the nth frame. The display device according to claim 2, wherein the display device is used to correct the above.
(N-1) further comprising a frame memory for storing the video data of the frame,
The controller is
With reference to the video data stored in the frame memory, a predetermined overdrive conversion is performed on the video data of the nth frame,
By referring to the video data stored in the frame memory, an integrated value is calculated based on gradation data indicating gradation in the video of the nth frame and the (n−1) th frame, and the gradation data The display device according to claim 5, wherein the display device is used for correction of an image.
The frame memory stores compressed video data,
The control unit calculates the integrated value based on data obtained by decompressing the video data stored in the frame memory and data obtained by compressing and decompressing the video data of the nth frame, and corrects the gradation data The display device according to claim 6, which is used for the display.
The control unit corrects the grayscale data using an integrated value indicating an integration of a voltage applied to a source line adjacent to the display target pixel in the future one frame period. 8. The display device according to any one of items 7.
The frame period includes a predetermined vertical blanking period;
The display device according to claim 1, wherein the control unit corrects the gradation data based on an effective value of an integrated value in a period of one frame including the vertical blanking period. .