WO2017028466A1 - 一种mems应变计芯片及其制造工艺 - Google Patents

一种mems应变计芯片及其制造工艺 Download PDF

Info

Publication number
WO2017028466A1
WO2017028466A1 PCT/CN2016/000370 CN2016000370W WO2017028466A1 WO 2017028466 A1 WO2017028466 A1 WO 2017028466A1 CN 2016000370 W CN2016000370 W CN 2016000370W WO 2017028466 A1 WO2017028466 A1 WO 2017028466A1
Authority
WO
WIPO (PCT)
Prior art keywords
strain gauge
silicon
gauge chip
layer
device portion
Prior art date
Application number
PCT/CN2016/000370
Other languages
English (en)
French (fr)
Inventor
王文
周显良
Original Assignee
中国科学院地质与地球物理研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院地质与地球物理研究所 filed Critical 中国科学院地质与地球物理研究所
Priority to US15/753,147 priority Critical patent/US10775248B2/en
Publication of WO2017028466A1 publication Critical patent/WO2017028466A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/18—Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00547—Etching processes not provided for in groups B81C1/00531 - B81C1/00539
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/16—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge
    • G01B7/18—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/16—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge
    • G01B7/18—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance
    • G01B7/20—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge using change in resistance formed by printed-circuit technique
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/26—Auxiliary measures taken, or devices used, in connection with the measurement of force, e.g. for preventing influence of transverse components of force, for preventing overload
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0292—Sensors not provided for in B81B2201/0207 - B81B2201/0285
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/01—Suspended structures, i.e. structures allowing a movement
    • B81B2203/0109—Bridges
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/01—Suspended structures, i.e. structures allowing a movement
    • B81B2203/0118—Cantilevers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0133—Wet etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition

Definitions

  • the present invention relates to a MEMS sensor, and more particularly to a MEMS strain gauge chip for detecting strain in an object.
  • the ratio of the relative change in resistance to the relative change in length is often referred to as the sensitivity coefficient, where the relative change in length is caused by mechanical strain.
  • the resistivity of a class of materials in existing materials varies with mechanical strain. This phenomenon is called a piezoresistive phenomenon.
  • the sensitivity coefficient of a strong piezoresistive material is much greater than the deformation.
  • Sheet-type strain gauges made of metal or alloy usually do not have strong piezoresistive properties, and their sensitivity and precision are relatively low.
  • the flexural strength of metals and alloys is also relatively low, and metal fatigue is likely to occur. After a period of multiple strain changes, metal or alloy strain gages may have problems with detection lag.
  • Another common strain gauge is a semiconductor strain gauge such as a strain gauge made of single crystal silicon as a conductive material. Silicon has strong mechanical strength and perfect elasticity. In addition, single crystal silicon has a strong piezoresistive effect, so that the sensitivity coefficient of a single crystal silicon strain gauge is usually more than ten times that of a metal or alloy strain gauge. Although monocrystalline silicon strain gauges have so many benefits, they are disadvantageous in that they are temperature sensitive. Nonlinear and relatively fragile. In addition, single crystal silicon is an anisotropic material, that is, its piezoresistive effect is directional. For this reason, the resistance of the silicon conductor not only senses the longitudinal direction, that is, the strain in the direction of the current, but also the partial strain in the lateral direction and the trimming direction. This can cause a large amount of crosstalk and measurement errors in the silicon strain gauge.
  • MEMS sensors are Micro-Electro-Mechanical Systems (MEMS) type sensors. Similar to integrated chips, MEMS sensors are typically fabricated by micromachining silicon wafers. In view of the structure of MEMS sensors, there are also some special manufacturing processes for fabricating three-dimensional microstructures, such as double-sided lithography, deep reactive ion etching (Ion Etching Etching), silicon wafer bonding, and the like. Based on the advantages of low cost, small size, high precision, reliability and stability, MEMS sensors are now widely used in automotive, medical, industrial and electronic products. AAS Mohammed, WAMoussa, and E.Lou published an article in the IEEE Sensors Journal (IEEE Sensors Journal, vol. 11, no. 10, pp.
  • a MEMS strain gauge having a plurality of piezoresistive measuring elements is disclosed in Experimental Evaluation. Wherein the strain gauge etches at least one groove near the detecting portion to reduce (but not completely eliminate) the crosstalk, and the strain gauge is provided with a concentrated stress region to improve the sensitivity.
  • the strain gage cannot be used in environments above 150 degrees Celsius.
  • the object of the present invention is to overcome the deficiencies of the prior art and to provide a strain gauge having high accuracy, large detection range, and small environmental impact.
  • a MEMS strain gauge chip includes an interconnected substrate, a device portion, and a cap plate, and a silicon oxide layer is formed between the substrate and the device portion and between the device portion and the cap plate; a recessed portion is formed on the substrate and the cover plate, the substrate recessed portion is connected to the recessed portion of the cover plate and forms a cavity, and the device portion is located in the cavity; the device portion includes a bridge portion and Piezoresistive measurement element The piezoresistive measuring element is disposed on the bridge.
  • the MEMS strain gauge chip of the present invention also has the following subsidiary features:
  • the cavity is a vacuum sealed cavity.
  • Both ends of the bridge are connected to both ends of the cavity.
  • a cantilever beam Also included in the device portion is a cantilever beam, the piezoresistive measurement element being disposed on the cantilever beam.
  • the device portion includes at least one bridge portion and at least one pair of cantilever beams, the bridge portion and the cantilever beam are parallel to each other; two of the piezoresistive measurement elements are formed on each of the bridge portions, each of which One of the piezoresistive measuring elements is formed on the cantilever beam.
  • the piezoresistive measuring elements are electrically connected to each other in a Wheatstone bridge manner.
  • the device portion includes at least two bridge portions that are perpendicular to each other, and each of the bridge portions is formed with two of the piezoresistive measurement elements.
  • a cantilever beam Also included in the device portion is a cantilever beam, the piezoresistive measurement element being disposed on the cantilever beam.
  • the piezoresistive measuring elements are electrically connected to each other in a Wheatstone bridge manner.
  • a silicon oxide isolation layer is formed on both the upper and lower sides and the sidewalls of the piezoresistive measurement element.
  • the end of the piezoresistive measuring element is formed with a metal contact.
  • the strain gauge chip is a silicon-on-insulator structure including an upper silicon layer, a lower silicon layer, and a silicon oxide buried layer, wherein a cavity is formed in a predetermined position in the lower silicon layer; wherein the substrate is located under the In the silicon layer, the device portion is located in the upper silicon layer, and the silicon oxide buried layer is disposed between the upper silicon layer and the lower silicon layer.
  • a manufacturing process of a MEMS strain gauge chip comprising the following steps:
  • a silicon oxide layer is grown or deposited on the top and bottom surfaces of the pre-processed silicon-on-silicon wafer on the insulator;
  • the upper silicon layer of the silicon on the insulator is locally doped by photolithography and ion implantation; the resistance value is lowered to form a high conductive region;
  • a plurality of trenches deep into the silicon oxide buried layer are etched on the upper silicon layer by photolithography and etching; and a plurality of piezoresistive measuring elements are formed;
  • a silicon oxide layer is grown or deposited in the trench
  • a plurality of holes deep in the upper silicon layer are etched in the top silicon oxide layer of the high conductive region by photolithography and etching; and a metal is deposited in the hole and the electrode is taken out ;
  • the silicon oxide layer on the top surface, the upper silicon layer and the silicon oxide buried layer are etched by a lithography and etching to form a cavity deep to the cavity of the lower silicon layer; Active bridge and cantilever beam;
  • the cover silicon wafer wafer pre-processed with the depressed portion is bonded to the top surface of the silicon-on-silicon wafer on the insulator;
  • the bonded silicon wafer is thickened and divided by grinding and dicing to form a complete MEMS strain gauge chip.
  • the processing step of the recess of the cap plate includes etching a recess on the cap plate by photolithography and etching.
  • the etching method is one or more of the following methods: dry etching or wet etching, the dry etching includes: deep reactive ions of silicon, reactive ions, and gaseous difluoride Reactive etch and silicon oxide reactive ions, plasma, and gaseous hydrogen fluoride etching.
  • the etchant for wet etching the silicon layer is a combination of one or more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
  • the etchant for wet etching the silicon oxide layer is a combination of one or more of the following etchants: hydrofluoric acid or buffered hydrofluoric acid.
  • the MEMS strain gauge chip of the invention has the following advantages: First, since the piezoresistive measurement elements in the conventional MEMS piezoresistive strain gauge are isolated by the PN junction, the current is cut off. The relationship with temperature is exponential. When the temperature is raised to 150 degrees Celsius, the PN junction isolation will fail.
  • a silicon oxide buried layer is disposed between the piezoresistive measuring element and the substrate, and silicon oxide is also provided between each piezoresistive measuring element for insulation. Further, the top surface of the piezoresistive measuring element is also grown or deposited. There is a silicon oxide layer.
  • each of the piezoresistive measuring elements in the present invention is in a state of being completely insulated at the upper and lower sides, and the electric isolation in the present invention does not fail even if the temperature is raised.
  • the piezoresistive measuring element disposed on the bridge portion is used for detecting one The strain in the radial direction.
  • the cantilever beam is suspended on three sides, and the piezoresistive measuring element placed on the cantilever beam is not deformed by the strain of the chip, so the piezoresistive measuring element disposed on the cantilever beam can be used to eliminate the error.
  • Connecting multiple piezoresistive measurement elements in a Wheatstone bridge eliminates many common mode errors. Therefore, the gage meter chip has higher detection accuracy.
  • the cavity formed by the interconnection of the substrate and the cover is a vacuum sealed cavity.
  • the main measuring elements of the device are placed in the cavity. Therefore, the fluctuation of the external temperature has little influence on the strain gauge chip, and the external foreign matter cannot contact the measuring component. The reliability of the strain gage chip is further increased.
  • the strain gauge chip uses silicon as a raw material as a whole, and on the one hand, it solves the mismatch problem caused by different thermal expansion and contraction coefficients between various materials. On the other hand, the MEMS manufacturing process also makes the cost lower.
  • 1 is a three-dimensional schematic view of a strain gauge chip.
  • FIG. 2 is a three-dimensional schematic view showing the opening of the cover of the strain gauge chip of FIG. 1 and the removal of silicon oxide on the top surface.
  • Fig. 3 is a three-dimensional perspective view taken along line AA' of Fig. 2.
  • FIG 4 is a plan view of the device portion of the first embodiment in the strain gauge chip.
  • Figure 5 is a schematic design of a piezoresistive measuring element in a strain gauge chip.
  • Figure 6 is a plan view of the device portion of the second embodiment of the strain gauge chip.
  • Figure 7 is a schematic diagram showing the circuit connection of the piezoresistive measuring element in the strain gauge chip.
  • FIG. 8 is a schematic diagram of the first step and the second step of the manufacturing process of the strain gauge chip.
  • FIG. 9 is a schematic diagram of the third step and the fourth step of the manufacturing process of the strain gauge chip.
  • FIG. 10 is a schematic diagram of the fifth step and the sixth step of the manufacturing process of the strain gauge chip.
  • FIG. 11 is a schematic diagram of the seventh step and the eighth step of the manufacturing process of the strain gauge chip.
  • a substrate 1 a substrate 1
  • a device portion 2 a cover plate 3
  • a silicon oxide layer 4 a recess portion 5
  • an upper silicon layer 6 a lower silicon layer 7, a metal contact 8, a doped region 9, a trench 10;
  • the bridge portion 21 the cantilever beam 22, the piezoresistive measuring element 23, and the constant current source 24.
  • a MEMS strain gauge chip includes a substrate 1, a device portion 2, and a cover plate 3 that are connected to each other.
  • a silicon oxide layer 4 is formed between the substrate 1 and the device portion 2, and a silicon oxide layer 4 is also formed between the device portion 2 and the cap plate 3.
  • Recessed portions 5 corresponding to each other are also formed in the substrate 1 and the cover plate 3, respectively.
  • the recesses 5 are interconnected to form a sealed cavity in which the device portion 2 is located.
  • the area of the cavity is indicated by a dashed line.
  • the MEMS strain gauge chip employs a silicon-on-insulator structure including an upper silicon layer 6, a lower silicon layer 7, and a silicon oxide layer 4.
  • the substrate 1 is located in the lower silicon layer 7, and a recess 5 is formed in advance, and the device portion 2 is formed in the upper silicon layer 6.
  • a silicon oxide layer 4 is also formed between the upper silicon layer 6 and the lower silicon layer 7, and is also referred to as a silicon oxide buried layer for electrically isolating the upper silicon layer 6 and the lower silicon layer 7.
  • the use of a silicon-on-insulator structure removes errors due to differences in thermal expansion and contraction coefficients of various materials.
  • the cavity formed by the substrate 1 and the recessed portion 5 of the cap plate 3 is a vacuum-tight cavity, thereby preventing external foreign matter and temperature fluctuations from affecting the piezoresistance measuring element 23.
  • a metal contact 8 is provided, which is electrically connected to the piezoresistive measuring element 23 in the device portion 2.
  • the portion of the device portion 2 other than the piezoresistive measuring element 23 also has an electrical contact 8 for grounding, and the external circuit and other electronic components are only electrically connected to the electronic contact 8, further The interference to the piezoresistive measuring element 23 is reduced.
  • FIG. 1 to 4 show a first embodiment of the present strain gage chip, wherein the device portion 2 includes a bridge portion 21 and two cantilever beams 22.
  • Piezoresistive measuring elements R1 to R4 are formed on the bridge portion 21 and the cantilever beam 22.
  • two piezoresistive measuring elements R2 and R4 are formed on the bridge portion 21, and the two cantilever beams 22 are respectively provided with piezoresistive measuring elements R1 and R3, wherein the bridge portion 21 and the two cantilever beams
  • the difference between 22 is that an etched groove 10 is formed between the two cantilever beams 22, thereby disconnecting the two cantilever beams 22 from each other. That is to say, the two cantilever beams 22 are respectively suspended in three sides.
  • a silicon oxide layer 4 is formed around each piezoresistive measuring element, and the top and bottom of each piezoresistive measuring element are respectively separated by a silicon oxide layer 4. Thereby electrical crosstalk between the piezoresistive measuring elements is prevented.
  • the resistance values of the four piezoresistive measuring elements R1 to R4 should be substantially the same without strain gauge chips.
  • the piezoresistive measuring elements R1 to R4 are U-shaped, and doped regions are formed at both ends of each piezoresistive measuring element and at a U-turn.
  • the doping region 9 is determined to be a P+ doped region or an N+ doped region according to the properties of the device portion 2. For example, if the device portion 2 is P-type, the doped region 9 is a P+ doped region. If the device portion 2 is N-type, the doping region 9 is an N+ doping region.
  • the doping region 9 is partially provided at the end of each piezoresistive measuring element and the U-turn.
  • the resistance value of the piezoresistive measuring element is lowered to form a highly conductive region such that the total resistance value of each piezoresistive measuring element is only slightly more than two resistance values laterally located in the undoped region.
  • the change of the partial resistance in the two undoped regions is the largest, and reducing the resistance value of the partial region by setting the doping region 9 improves the detection accuracy of the strain gauge.
  • the geometric design of the piezoresistive measuring element is not limited to the U shape, but may be a ⁇ design in which a plurality of U-shaped portions are combined in series, and FIG. 5 shows that the two U-shaped portions are combined in series.
  • a ⁇ design of a piezoresistive measuring element is not limited to the U shape, but may be a ⁇ design in which a plurality of U-shaped portions are combined in series, and FIG. 5 shows that the two U-shaped portions are combined in series.
  • the strain gauge chip when using the strain gauge chip, the strain gauge chip is bonded to the surface of the object to be strained by an adhesive.
  • the strain gauge chip is usually fixed by using a resin adhesive or an inorganic high-temperature adhesive specially bonded to the strain gauge, and the thickness of the adhesive is thin, so that the strain felt on the surface of the object can be transmitted to the strain gauge.
  • the thickness of the strain gauge chip is also relatively thin to prevent the strain gauge chip from interfering with the strain experienced by the object.
  • the cantilever beam 22 is suspended on three sides, it is less affected by various strains of the strain gauge chip, and the resistance values of the piezoresistive measuring elements R1 and R3 formed on the cantilever beam 22 are not changed much.
  • the bridge portion 21 is directly connected to the side walls of the cavity in the strain gauge chip, and directly senses the positive strain of the strain gauge chip along the bridging portion 21, and the piezoresistance measuring elements R2 and R4. The resistance value will change.
  • the resistance values of R2 and R4 change, the voltages of R2 and R4 also change accordingly.
  • the electronic circuit can calculate the magnitude of the strain based on the voltages of R2 and R4. According to the piezoresistive characteristics of silicon, the resistance values of R2 and R4 are close to a linear relationship with the detected strain. However, factors affecting the resistance value of the piezoresistive measuring element are not limited to strain, and other factors such as changes in ambient temperature may also cause changes in the resistance value of the piezoresistive measuring element. For this reason, in the present scheme, the piezoresistive measuring elements R1 and R3 are mainly used for temperature compensation, thereby reducing measurement errors caused by external temperatures.
  • the piezoresistive measuring elements R1 to R4 are electrically connected in the form of a Wheatstone bridge and are powered by a constant current source 24.
  • the corresponding strain can be calculated by measuring the voltage between the two points of the point V+ and the point V-. In the absence of strain, the resistance values of the piezoresistive measuring elements R1 to R4 are substantially the same, and the voltage between the measuring points V+ and V- is substantially zero.
  • the strain causes a change in the resistance of R2 and R4
  • a certain voltage is also generated between V+ and V-.
  • the connection of the Wheatstone bridge mainly eliminates the common mode error.
  • the resistance changes produced by the four piezoresistive measuring elements R1 to R4 are the same, so in the absence of strain, the voltage between the two points V+ and V- is still zero.
  • the Wheatstone bridge can be driven by a constant voltage power source or a constant current power source, but preferably, the Wheatstone bridge excited by the constant current power source has the following advantages: the negative temperature coefficient of the piezoresistive effect of silicon Part of it is offset by the positive temperature coefficient of the resistor, thereby reducing the overall error ratio factor caused by temperature. By measuring the bridge voltage of the measuring point Vb, the corresponding temperature information can be calculated, and the error caused by the ambient temperature can be further compensated.
  • the gauge chip has dimensions of about 2.5 mm in length, about 1.5 mm in width, and about 0.6 mm in thickness, and the dimensions of the cavity are approximately 1 mm long and 0.5 mm. Width, 0.1 mm high, wherein the thickness of the device portion 2 is approximately 20 microns. This dimension does not interfere with the strain experienced by the object during use.
  • an ordinary 8-inch silicon wafer can produce thousands to 10,000 strain gauge chips, making the cost of manufacturing the strain gauge chip very low.
  • the above size data is only an example of the present invention, and is not intended to limit the scope of the present invention. Those skilled in the art can modify the size according to their specific needs.
  • the device portion 2 is placed in a vacuum cavity formed by the recesses 5 of the substrate 1 and the cap plate 3, and the upper and lower sides of each piezoresistive measuring element 23 are isolated by silicon oxide 4, This makes the detection accuracy and reliability of the strain gage chip improved, and the gage chip can work at high temperatures up to 250 degrees Celsius and can detect strains in the range of plus or minus 0.2%.
  • Fig. 4 shows an embodiment of the present strain gage chip.
  • heave bridge portion 21 is formed in the device portion 2, only the positive strain in the direction of the bridge portion 21 on the uniaxial axis can be detected.
  • Fig. 6 shows a second embodiment of the present strain gage chip.
  • the device portion 2 in this embodiment includes two mutually perpendicular bridge portions 21 and four cantilever beams 22.
  • the piezoresistive measuring element 23 formed on the cantilever beam 22 serves to eliminate the detection error caused by the temperature.
  • the four piezoresistive measuring elements 23 on the bridge 21 are used to measure the positive strain in the two perpendicular directions of the two axes.
  • the effect of the silicon voltage group is that the magnitude of the resistance change is closely related to the type of dopant ions, the concentration of the dopant ions, and the crystal orientation.
  • the type of dopant ions includes P type or N type. Since single crystal silicon is an anisotropic substance, the difference in crystal orientation also causes a difference in the magnitude of the resistance change. The factors that lead to the magnitude of the change in resistance are described in Y. Kanda, IEEE Transactions on Electron Devices, vol. ED-29, no. 1, pp. 64-70, 1982.
  • the diagram of the piezoresistive coefficient is explained in detail in the article.
  • the crystal orientation in the present invention should be a direction that maximizes the piezoresistive properties of silicon.
  • the device portion 2 is P-type silicon
  • the device portion 2 is placed on the ⁇ 100 ⁇ crystal plane while the piezoresistive measurement element 23 is placed in the ⁇ 110> crystal direction.
  • Another P-type silicon wafer is disposed by placing the device portion 2 on the ⁇ 110 ⁇ crystal plane while the piezoresistive measurement element 23 is disposed in the ⁇ 110> or ⁇ 111> direction.
  • the device portion 2 is N-type silicon
  • the device portion 2 is disposed on the ⁇ 100 ⁇ crystal plane while the piezoresistive measurement element 23 is disposed in the ⁇ 100> crystal direction.
  • N-type silicon wafer is disposed by placing the device portion 2 on the ⁇ 110 ⁇ crystal plane while the piezoresistive measurement element 23 is placed in the ⁇ 100> direction. Another advantage of such a placement direction is that all shear piezoresistive coefficients are zero, so that even if the bridge portion 21 and the cantilever beam 22 are subjected to shear strain during the measurement, the piezoresistive measuring element 23 is also sheared. The strain is not sensitive, which reduces the error of the strain gauge. Of course, technicians can also follow Y.Kanda The description of the device portion 2 and the piezoresistive measuring element 23 is separately preferred and set.
  • a silicon-on-insulator structure having a cavity 5 at a specific location including an upper silicon layer 6, a silicon oxide buried layer, is employed. 4 and a lower silicon layer 7, the cavity 5 being located in the lower silicon layer 7.
  • Such a silicon-on-insulator structure with a cavity is generally fabricated by silicon-silicon bonding: a recess of a specific depth is formed at a specific position and pattern of the silicon wafer of the lower silicon layer, and then a surface is formed thereon.
  • the upper silicon layer silicon wafer of the silicon oxide layer is bonded to the upper surface, and finally the upper silicon layer is ground to a specific thickness to form a silicon-on-insulator wafer with a cavity. Therefore, the fabrication process uses a silicon-on-insulator wafer with a cavity as a raw material, and then includes the following processing steps:
  • the silicon-on-silicon wafer on the insulator with a cavity at a specific position is subjected to high-temperature oxidation treatment, and a silicon oxide layer 4 is formed on the top and bottom surfaces thereof, or a chemical vapor deposition method (Chemical Vapor Deposition) is used. A silicon oxide layer 4 is deposited.
  • a photoresist is coated on the top surface of the silicon-on-silicon wafer on the insulator, and then the top surface is exposed in a specific pattern, and the exposed photoresist is removed by a developer, and Unexposed photoresist is baked. The pattern thus exposed will appear. Then using ion implantation technology, and through energy control, the ions have enough energy to pass through the top silicon oxide layer not covered by the photoresist and implanted in the upper silicon layer, and at the same time, the ions are covered by the photoresist. Blocked in the photoresist layer.
  • the upper silicon layer 6 of the silicon on the insulator can be locally doped to form a doped region 9, thereby reducing the resistance value of the region to form a highly conductive region; wherein if the upper silicon layer 6 is P-type, P-type dopant ions, such as boron, are used. If the upper silicon layer 6 is N-type, an N-type dopant ion such as phosphorus is used. Finally will All photoresist is removed. In addition to the ion implantation techniques described above, impurity high temperature diffusion techniques can also be used for local doping.
  • the third step photolithography is performed on the top surface of the silicon-on-silicon wafer on the insulator, followed by reactive ion or plasma dry etching, or hydrofluoric acid etching, and partial etching of the top silicon oxide layer 4, thereby The top surface forms a plurality of grooves 10 deep to the upper silicon layer 6. Thereafter, the upper silicon layer 6 in the trench 10 is further etched into the silicon oxide buried layer 4 by deep reactive ion etching or other dry or wet etching. Thereby, a plurality of piezoresistive measuring elements 23 are formed.
  • a silicon oxide spacer layer 4 is grown or deposited in the trench 10 by high temperature oxidation or chemical vapor deposition. At this point, all the upper and lower sides of the piezoresistive measuring element are wrapped by the silicon oxide insulating layer.
  • the top silicon oxide layer 4 is locally etched to form a plurality of deep tops on the top surface.
  • the silicon layer 6 is doped with holes in the region 9, and metal is deposited in the holes and on the top surface of the entire silicon wafer, and then the metal electrode pattern is extracted by photolithography and metal etching.
  • the top silicon oxide layer 4 is partially etched by photolithography, reactive ion or plasma dry etching, or hydrofluoric acid etching to form a trench deep to the upper silicon layer 6 on the top surface. 10.
  • the upper silicon layer 6 in the trench 10 is further etched into the silicon oxide buried layer 4 by deep reactive ion etching or other dry or wet etching.
  • the silicon oxide buried layer 4 in the trench 10 is further etched by reactive ion or plasma dry etching until the cavity 5 of the lower silicon layer 7.
  • the photoresist is removed by plasma dry etching to form the released bridge and cantilever beam.
  • the cover wafer silicon wafer which has been recessed in advance is vacuum-bonded to the top surface of the silicon-on-silicon wafer on the insulator to form a sealed vacuum cavity.
  • the bonding technique may be silicon-silicon direct bonding, eutectic bonding, solder bonding, or anodic bonding.
  • the bonded silicon wafer is thickened and divided by grinding and dicing to form a complete MEMS strain gauge chip.
  • the etching method is one or more of the following methods: dry etching or wet method Etching, the dry etching includes: deep reactive ions of silicon, reactive ions, and gaseous ruthenium difluoride etching and reactive ions of silicon oxide, plasma, and gaseous hydrogen fluoride etching.
  • the etchant for wet etching the silicon layer is a combination of one or more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
  • the etchant for wet etching the silicon oxide layer is hydrofluoric acid or buffered hydrofluoric acid.
  • the strain gauge chip of the invention adopts the cavity in which the measuring component is placed in a vacuum, which greatly reduces external environmental factors and the influence of foreign matter on the strain gauge chip. The reliability and detection accuracy of the strain gage chip are also enhanced. Further, each of the piezoresistive measurement elements is wrapped in a silicon oxide layer 4 such that each of the piezoresistive measurement elements is isolated from each other, reducing crosstalk and errors between the piezoresistive measurement elements. This isolation also allows the strain gage chip to be tested in high temperature environments. Thirdly, electrically connecting the piezoresistive measuring element in the manner of a Wheatstone bridge can reduce the common mode error caused by external factors and reduce the influence of temperature on the accuracy of the chip detection.
  • the strain gauge chip is fabricated by using a silicon-on-silicon wafer on insulator.
  • the silicon wafer on the insulator is a mature technology and the price is low.
  • it also solves the mismatch problem caused by the difference in thermal expansion and contraction coefficient between various materials.
  • an ordinary 8-inch silicon wafer can produce thousands to 10,000 strain gauge chips, and it can be seen that the strain gauge chip is low in manufacturing cost.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

一种MEMS应变计芯片，包括相互连接的衬底（1）、器件部（2）以及盖板（3），所述衬底（1）与所述器件部（2）之间以及所述器件部（2）与所述盖板（3）之间形成有 氧化硅层（4）；所述衬底（1）以及所述盖板（3）上分别形成有凹陷部（5），衬底凹陷部（5）与盖板凹陷部（5）相连接并形成一空腔，所述器件部（2）位于所述空腔内；所述器件部（2）包括 桥接部（21）以及压阻测量元件（23），所述压阻测量元件（23）设置在所述 桥接部（21）上。该应变计芯片受温度影响较小，可以在高温的环境中使用，而且具有检测精度高、可靠性高、制造成本低等特点。还公开了一种MEMS应变计芯片的制造方法。

Description

一种MEMS应变计芯片及其制造工艺 技术领域
本发明涉及一种MEMS传感器，特别是一种用于检测物体应变的MEMS应变计芯片。
背景技术
众所周知，导体的电阻是根据其尺寸而变化的。例如，如果将导体沿着电流方向拉伸的话，电流路径会增加，而基于泊松比，电流通过的横截面面积则会减少。因此，电阻会增加。这种机理被广泛用于检测应变的仪器中。美国专利US2457616描述了一种薄片类的应变计，其中包括将导电材料，例如金属制成锯齿形的薄条，并将薄条嵌入到热塑塑料片中。所述薄片被固定在应变表面。应变的变化会导致导电材料的形变，而从测量导电材料的电阻就可以计算出应变的幅度。
在应变计中，电阻的相对变化与长度的相对变化之比通常被称为灵敏系数，其中长度的相对变化是由机械应变造成的。现有的材料中有一类材料的电阻率会随着机械应变而改变。该现象被称为压阻现象。强压阻材料的灵敏系数远远大于形变。由金属或者合金制成的薄片式应变计通常不具有强压阻现象，其灵敏度和精准度也相对较低。此外，金属和合金的抗屈强度也比较低，很容易出现金属疲劳等现象。在多次应变的变化周期后，金属或者合金类的应变计可能会出现检测滞后的问题。
另一种常见的应变计是半导体应变计，例如由单晶硅作为导电材料制成的应变计。硅具有很强的机械强度，并且具有完美的弹性。此外，单晶硅具有很强的压阻效应，使得单晶硅类的应变计的灵敏系数通常是金属或者合金类应变计的十倍以上。尽管单晶硅类应变计有如此多的好处，其缺点在于对温度敏感、 非线性以及相对脆弱。此外，单晶硅是一种各向异性材料，即其压阻效应是有方向性的。为此，硅导体的电阻不仅仅会感应到纵向，即电流方向上的应变，也会感应到在横向和剪边方向上的部分应变。而这样会在硅应变计中产生大量的串扰和测量错误。
现如今，大多数传感器均为微机电系统(Micro-Electro-Mechanical Systems，MEMS)类型的传感器。与集成芯片类似，MEMS传感器通常是通过对硅晶圆片进行微加工而制成的。鉴于MEMS传感器的结构，也有一些用来制造三维细微结构的特殊的制造工艺，例如双面光刻，深度反应离子刻蚀(Deep Reactive Ion Etching)，硅晶圆片键合等等。基于MEMS芯片具有成本低，尺寸小，精准性、可靠性、稳定性均比较高的优点，MEMS传感器现在已经被广泛用于汽车、医疗、工业以及电子产品中。A.A.S.Mohammed，W.A.Moussa，and E.Lou在IEEE传感器期刊(IEEE Sensors Journal，vol.11，no.10，pp.2220-2232，2011)中发表了一篇《新型压阻MEMS应变计的研发以及实验评价》中公开了一种具有多个压阻测量元件的MEMS应变计。其中该应变计在检测部附近刻蚀出至少一个槽来减少(但并没有完全消除)串扰，另外该应变计设置了集中应力区域来提高灵敏度。然而，由于PN结隔离的局限性，该应变计并不能在高于150摄氏度的环境中使用。
为此，在应变计领域中，急需一种能够在高温环境中工作，并且能够检测单轴以及双轴的应变却不会被串扰所影响的MEMS应变计。
发明内容
本发明的目的在于克服现有技术的不足，提供一种准确度高、检测范围大、并且受环境影响小的应变计。
一种MEMS应变计芯片，包括相互连接的衬底、器件部以及盖板，所述衬底与所述器件部之间以及所述器件部与所述盖板之间形成有氧化硅层；所述衬底以及所述盖板上分别形成有凹陷部，衬底凹陷部与盖板凹陷部相连接并形成一空腔，所述器件部位于所述空腔内；所述器件部包括桥接部以及压阻测量元 件，所述压阻测量元件设置在所述桥接部上。
本发明中的MEMS应变计芯片还具有以下附属特征：
所述空腔为真空密封空腔。
所述桥接部的两端与所述空腔的两端相连接。
所述器件部中还包括悬臂梁，所述压阻测量元件设置在所述悬臂梁上。
所述器件部中包括至少一根桥接部以及至少一对悬臂梁，所述桥接部与所述悬臂梁相互平行；每根所述桥接部上形成有两个所述压阻测量元件，每根所述悬臂梁上形成有一个所述压阻测量元件。
所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
所述器件部包括至少两根相互垂直的所述桥接部，每根所述桥接部上形成有两个所述压阻测量元件。
所述器件部中还包括悬臂梁，所述压阻测量元件设置在所述悬臂梁上。
所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
所述压阻测量元件的上下方及侧壁均形成有氧化硅隔离层。
所述压阻测量元件的末端形成有金属触点。
所述应变计芯片为绝缘体上硅结构，包括上硅层、下硅层以及氧化硅埋层，所述下硅层中在特定位置预先形成有空腔；其中，所述衬底位于所述下硅层中，所述器件部位于所述上硅层中，所述上硅层与所述下硅层之间设置有所述氧化硅埋层。
一种MEMS应变计芯片的制造工艺，所述制造工艺包括以下步骤：
第一步，在预先加工带有空腔的绝缘体上硅硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
第二步，通过光刻及离子植入，对所述绝缘体上硅的上硅层进行局部掺杂；降低其电阻值，形成高导电区域；
第三步，通过光刻以及刻蚀，在所述上硅层上刻蚀出多个深至氧化硅埋层的槽；形成多个压阻测量元件；
第四步，在所述槽内生长或淀积一层氧化硅层；
第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多个深至所述上硅层的孔；并在所述孔内淀积金属并引出电极；
第六步，利用光刻和刻蚀，对顶面的所述氧化硅层，所述上硅层以及所述氧化硅埋层进行刻蚀出深至下硅层空腔的槽；形成可自由活动的桥接部及悬臂梁；
第七步，将预先加工有凹陷部的盖板硅晶圆片与所述绝缘体上硅硅晶圆片的顶面进行键合；
第八步，通过研磨及划片，将所述已键合的硅晶圆片减厚及分割，形成完整的MEMS应变计芯片。
对所述盖板的凹陷部的加工步骤包括：通过光刻和刻蚀，在所述盖板上刻蚀出凹陷部。所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
所述用于湿法腐蚀氧化硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氟酸或缓冲氢氟酸。
相对于背景技术中所提到的MEMS应变计，本发明的MEMS应变计芯片具有以下优点：首先，由于传统MEMS压阻应变计中压阻测量元件之间是依靠PN结隔离的，其截流电流与温度之间的关系为指数关系，当温度提高至150摄氏度时，PN结隔离将会失效。而本发明中的压阻测量元件与衬底之间设置有氧化硅埋层，每个压阻测量元件之间也设置氧化硅来进行绝缘，此外，压阻测量元件顶部上也生长或淀积有氧化硅层。为此，本发明中的每个压阻测量元件是处于上下四周完全绝缘的状态，即使温度升高，本发明中的电隔离也不会失效。其次，在本应变计芯片中，设置在桥接部上的压阻测量元件是用于检测一 个径向方向上的应变。而悬臂梁三面悬空，安置在悬臂梁上的压阻测量元件并不会因为芯片应变而变形，所以设置在悬臂梁上的压阻测量元件可用于消除误差。而将多个压阻测量元件以惠斯登电桥的方式进行连接可以消除许多的共模误差。因此本应变计芯片的检测精准度更高。再次，优选地，由衬底和盖板相互连接后形成的空腔为真空的密封空腔。而器件部的主要测量元件均设置在该空腔中。所以外界温度的波动对本应变计芯片的影响较小，而且外部异物也无法接触到测量元件。进一步的增加了本应变计芯片的可靠性。此外，应变计芯片整体采用硅作为原料，一方面解决了各种材料之间因热胀冷缩系数不同而导致的失配问题。另一方面通过MEMS制造流程也使得成本较低。
附图说明
图1为应变计芯片的三维立体示意图。
图2为将图1的应变计芯片的盖板打开及顶面的氧化硅移除后的三维立体示意图。
图3为沿图2中AA’线剖视的三维立体图。
图4为应变计芯片中第一实施例的器件部的俯视图。
图5为应变计芯片中的压阻测量元件的一种蜿蜒设计方案。
图6为应变计芯片中第二实施例的器件部的俯视图。
图7为应变计芯片中压阻测量元件电路连接示意图。
图8为应变计芯片制造工艺的第一步、第二步示意图。
图9为应变计芯片制造工艺的第三步、第四步示意图。
图10为应变计芯片制造工艺的第五步、第六步示意图。
图11为应变计芯片制造工艺的第七步、第八步示意图。
衬底1、器件部2、盖板3、氧化硅层4、凹陷部5、上硅层6、下硅层7、金属触点8、掺杂区9、槽10；
桥接部21、悬臂梁22、压阻测量元件23、恒流电源24。
具体实施方式
下面将结合实施例以及附图对本发明加以详细说明，需要指出的是，所描述的实施例仅旨在便于对本发明的理解，而对其不起任何限定作用。
参照图1、图2、以及图3，按照本发明提供的一种MEMS应变计芯片，包括相互连接的衬底1、器件部2、以及盖板3。其中，衬底1与器件部2之间形成有氧化硅层4；器件部2与盖板3之间也形成有氧化硅层4。衬底1以及盖板3中还分别形成有相互对应的凹陷部5。凹陷部5相互连接后形成一密封的空腔，器件部2位于所述空腔内。在图4、图5和图6中，所述空腔的面积由虚线示处。优选地，所述MEMS应变计芯片采用绝缘体上硅结构，其中包括上硅层6、下硅层7和氧化硅层4。其中衬底1位于所述下硅层7中，并预先形成有凹陷部5，器件部2形成于上硅层6中。上硅层6与下硅层7之间形成有氧化硅层4，该氧化硅层4也被称为氧化硅埋层，其用于电隔离上硅层6和下硅层7。采用绝缘体上硅结构去除了因为各种不同材料的热胀冷缩系数不同而产生的误差。此外，优选地，所述衬底1以及盖板3的凹陷部5所形成的空腔为真空密封空腔，从而防止了外界异物以及温度波动对压阻测量元件23的影响。而器件部2与盖板3之间的氧化硅层4上设置有金属触点8，所述金属触点8与器件部2中的压阻测量元件23相电连接。此外，器件部2处于压阻测量元件23以外的其它部分亦有一个用来接地的的电子触点8相电连接，而外部电路以及其它电子元件也只与电子触点8相电连接，进一步地减少了对压阻测量元件23的干扰。
图1至4展示了本应变计芯片的第一种实施例，其中，所述器件部2包括一根桥接部21和两根悬臂梁22。桥接部21和悬臂梁22上均形成有压阻测量元件R1至R4。正如图4所示，桥接部21上形成有两个压阻测量元件R2和R4，而两根悬臂梁22上分别设置有压阻测量元件R1和R3，其中，桥接部21和两根悬臂梁22之间的区别在于两根悬臂梁22之间形成有刻蚀的槽10，从而将两根悬臂梁22相互断开。也就是说，两根悬臂梁22分别为三面悬空状态。 优选地，每个压阻测量元件的四周均形成有氧化硅层4，并且每个压阻测量元件的顶部和底部分别由氧化硅层4进行隔离。从而防止压阻测量元件之间的电串扰。理论上说，在应变计芯片没有应变的情况下，四个压阻测量元件R1至R4的电阻值应当是基本相同的。
参照图2至4，所述压阻测量元件R1至R4为U形，每个压阻测量元件的两端及U形拐弯处均形成有掺杂区。所述掺杂区9是根据器件部2的性质来确定是P+掺杂区还是N+掺杂区的，例如，如果器件部2为P型，则掺杂区9为P+掺杂区。如果器件部2为N型，则掺杂区9为N+掺杂区。由于器件部2的硅电阻率大约为0.1Ω-cm，而掺杂区9的电阻率大约为0.01Ω-cm，在每个压阻测量元件的末端及U形拐弯处设置掺杂区9局部降低了压阻测量元件的电阻值，形成高导电区域，使得每个压阻测量元件的总电阻值只略多于两根横向位于非掺杂区的电阻值。在检测应变的过程中，两根位于非掺杂区中的部分电阻的变化是最大的，通过设置掺杂区9来降低部分区域的电阻值提高了本应变计的检测精准度。当然，压阻测量元件的几何设计并不只限于U形，亦可以是由多个U形部分串联组合而成的蜿蜒设计，图5所示的就是采用了由两个U形部分串联组合而成的压阻测量元件的一种蜿蜒设计方案。
参照图1至3，在使用本应变计芯片时，应变计芯片会通过胶黏剂粘结到需要检测应变的物体表面。通常是使用专门为粘结应变计的树脂胶黏剂或者无机高温胶黏剂来固定所述应变计芯片，而且胶黏剂的厚度较薄，从而能够将物体表面所感受到的应变传输到应变计芯片上，并导致应变计芯片产生与被检测物体表面同样的形变。而且应变计芯片的厚度也比较薄，以防止应变计芯片干扰到物体所受到的应变。由于悬臂梁22为三面悬空，受应变计芯片的各种应变影响较少，形成在悬臂梁22上的压阻测量元件R1和R3的电阻值变化则不大。相反，桥接部21因其两端与所述应变计芯片内所述空腔两边的侧壁相连接，直接感受到应变计芯片沿桥接部21方向的正应变，压阻测量元件R2和R4的电阻值则会产生变化。根据欧姆定律V＝IR，当电流通过压阻测量元件R2和R4， 并且R2和R4的电阻值产生变化时，R2和R4的电压也会相应的产生变化。电子电路可以根据检测R2和R4的电压来计算出应变的幅度。根据硅的压阻特性，R2和R4的电阻值变化与检测到的应变接近线性关系。然而，影响压阻测量元件的电阻值的因素不仅限于应变，其他因素，例如周围环境温度的变化也会导致压阻测量元件电阻值的变化。为此，在本方案中，所述压阻测量元件R1和R3主要是用于温度补偿，从而减少由外界温度导致的测量误差。
此外，优选地，参照图7，压阻测量元件R1至R4是以惠斯登电桥的形式来进行电连接，并由一恒流电源24来供电。通过测量点V+和点V-两点之间的电压则可以计算出相应的应变。在没有应变的情况下，压阻测量元件R1至R4的电阻值基本相同，测量点V+和V-之间的电压基本为零。而当应变使得R2和R4的电阻产生变化时，V+和V-之间也会产生一定的电压。惠斯登电桥的连接方式主要消除了共模误差。例如，当温度产生变化时，四个压阻测量元件R1至R4所产生的电阻变化是相同的，所以在没有应变的情况下，V+和V-两点之间的电压依旧为零。所述惠斯登电桥可以由恒压电源或者恒流电源来驱动，但优选地，由恒流电源所激励的惠斯登电桥还有如下优点：硅的压阻效应的负温度系数中的一部分会被电阻的正温度系数所抵消，从而整体降低了由温度造成的误差比例系数。而通过测量测量点Vb的电桥电压可以计算出相应的温度信息，可以进一步对环境温度导致的误差进行补偿。
参照图1及图3，优选地，本应变计芯片的尺寸为：长度大约为2.5毫米，宽度大约为1.5毫米，厚度大约为0.6毫米，而空腔的尺寸大约为：1毫米长，0.5毫米宽，0.1毫米高其中器件部2的厚度大约为20微米。本尺寸一方面在使用过程中不会干扰物体所感受到的应变。另一方面，在制造过程时，一块普通的8英寸硅晶圆片可以制造出数千至一万多个应变计芯片，使得本应变计芯片的制造成本非常的低。然而，以上的尺寸数据仅为本发明的一种示例，而非对本发明保护范围的限制。本领域的技术人员完全可以根据其具体需求来对该尺寸进行修改。
通过采用绝缘体上硅结构、将器件部2设置在由衬底1和盖板3的凹陷部5形成的真空空腔中以及对每一个压阻测量元件23的上下四周用氧化硅4进行隔离，使得本应变计芯片的检测精准度和可靠性得到提高，并且本应变计芯片可以在高达250摄氏度的高温中工作，并且可以检测正负0.2％范围的应变。
图4展示了本应变计芯片的一种实施例，在该实施例中，由于器件部2中只形成有一跟桥接部21，所以只能检测单轴上沿桥接部21方向上的正应变。
图6展示了本应变计芯片的第二种实施例，本实施例中的器件部2中包括两根相互垂直的桥接部21，以及四根悬臂梁22。同样地，形成于悬臂梁22上的压阻测量元件23用于消除温度带来的检测误差。而桥接部21上的四个压阻测量元件23则用于测量双轴两个垂直方向上的正应变。
有关硅压组效应值得注意的是，电阻变化的幅度是与掺杂离子的类型、掺杂离子的浓度以及晶体方向都息息相关，其中，掺杂离子的类型包括P型或者N型。而由于单晶硅为各向异性的物质，晶体方向的不同也会导致电阻变化幅度的不同。导致电阻变化幅度的各项因素在Y.Kanda在IEEE电子器件期刊中(IEEE Transactions on Electron Devices，vol.ED-29，no.1，pp.64-70，1982)所发表的《对硅的压阻系数的图解》一文中有详细的解释。优选地，本发明中的晶体方向应当是使得硅的压阻特性最大化的方向。其中一种做法是：如果器件部2是P型硅，则将器件部2设置在{100}晶体平面上，同时将压阻测量元件23设置在<110>晶体方向上。另外一种P型硅片的设置方法为：将器件部2设置在{110}晶体平面上，同时将压阻测量元件23设置在<110>或<111>方向上。又如器件部2是N型硅，则将器件部2设置在{100}晶体平面上，同时将压阻测量元件23设置在<100>晶体方向上。另外一种N型硅片的设置方法为：将器件部2设置在{110}晶体平面上，同时将压阻测量元件23设置在<100>方向上。如此的摆放方向的另一个优点在于：所有剪切压阻系数均为零，使得即使在测量过程中桥接部21和悬臂梁22上承受有剪切应变，压阻测量元件23也对剪切应变不敏感，从而减少了本应变计的误差。当然，技术人员也可以根据Y.Kanda 的描述另行优选及设置器件部2和压阻测量元件23的方向。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案，而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细地说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。
接下来，参照图8至图11对本应变计芯片的制造工艺进行进一步的描述。本工艺适用于本应变计中第一种和第二种实施例所展示的结构，其中，采用了在特定位置带有空腔5的绝缘体上硅结构，包括上硅层6，氧化硅埋层4以及下硅层7，所述空腔5位于下硅层7中。这种带有空腔的绝缘体上硅结构一般都是通过硅-硅键合制造而成的：先在下硅层硅晶圆片的特定位置和图案形成特定深度的凹陷，再将表面上形成有氧化硅层的上硅层硅晶圆片键合到上面，最后把上硅层研磨减厚到特定的厚度，形成带有空腔的绝缘体上硅硅晶圆片。故此，本制作工艺是采用带有空腔的绝缘体上硅硅晶圆片作为原材料，之后再作包括以下的加工步骤：
第一步，对在特定位置带有空腔的绝缘体上硅硅晶圆片进行高温氧化处理，在其顶面及底面形成一层氧化硅层4，或者利用化学气相淀积法(Chemical Vapor Deposition)淀积一层氧化硅层4。
第二步，在所述绝缘体上硅硅晶圆片的顶面上涂覆光刻胶，之后按照特定图案对所述顶面进行曝光，并用显影剂将已曝光的光刻胶去除，及将未经曝光的光刻胶烘烤。这样被曝光的图案就会显现出来。再用离子注入技术，并通过能量控制，使离子有足够能量穿越未被光刻胶覆盖的顶面氧化硅层而植入上硅层里，同时，在被光刻胶覆盖的地方，离子却被挡于光刻胶层当中。这样就可以对所述绝缘体上硅的上硅层6进行局部掺杂，形成掺杂区9，从而降低该区域的电阻值，形成高导电区域；其中，如果上硅层6为P型，则使用P型掺杂离子，例如硼。如果上硅层6为N型，则使用N型掺杂离子，例如磷。最后将 所有光刻胶去除。除了上述离子注入技术之外，亦可以使用杂质高温扩散技术来进行局部掺杂。
第三步，在所述绝缘体上硅硅片的顶面进行光刻，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀、对顶面氧化硅层4进行局部刻蚀，从而在顶面形成多个深至上硅层6的槽10。之后，利用深度反应离子刻蚀或其它干法或湿法刻蚀，进一步将槽10中的上硅层6刻蚀至氧化硅埋层4。从而形成多个压阻测量元件23。
第四步，利用高温氧化或化学气相淀积法在所述槽10中生长或淀积一层氧化硅隔离层4。至此，压阻测量元件上下四周各方均被氧化硅绝缘层包裹。
第五步，利用光刻技术，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀、对顶面氧化硅层4进行局部刻蚀，从而在顶面形成多个深至所述上硅层6中掺杂区9的孔，并在所述孔中及整个硅晶圆片顶面淀积金属，再利用光刻及金属腐蚀，引出金属电极图案。
第六步，利用光刻技术，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀，对顶面氧化硅层4进行局部刻蚀，从而在顶面形成深至上硅层6的槽10。之后再用深度反应离子刻蚀或其它干法或湿法刻蚀，进一步将槽10中的上硅层6刻蚀至氧化硅埋层4。然后，利用反应离子或等离子干法刻蚀进一步将槽10中的氧化硅埋层4刻穿，直至下硅层7的空腔5。最后再用等离子干法刻蚀将光刻胶去除，从而形成被释放的桥接部及悬臂梁。
第七步，将预先有凹陷加工的盖板硅晶圆片与所述绝缘体上硅硅晶圆片的顶面进行真空键合，形成密封的真空空腔。其中的键合技术可以为硅-硅直接键合、共熔键合、焊烧键合、或阳极键合。
第八步，通过研磨及划片，将所述已键合的硅晶圆片减厚及分割，形成完整的MEMS应变计芯片。
其中，所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法 刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
所述用于湿法腐蚀氧化硅层的腐蚀剂为氢氟酸或缓冲氢氟酸。
本发明的应变计芯片采用了将测量元件设置在真空的空腔中，大大减少了外界环境因素和异物对本应变计芯片的影响。也增强了本应变计芯片的可靠性和检测精准度。此外，将每一个压阻测量元件包裹在一层氧化硅层4中，使得每个压阻测量元件之间相互隔离，减少了压阻测量元件之间的串扰和误差。这种隔离方式也使得本应变计芯片可以在高温环境中进行检测。再次，将压阻测量元件以惠斯登电桥的方式进行电连接能够减少由外界因素导致的共模误差，也降低了温度对应变计芯片检测精准度的影响。而通过采用绝缘体上硅硅晶圆片来制作本应变计芯片，一方面绝缘体上硅硅片为成熟技术，价格低廉。另一方面也解决了各种材料之间因热胀冷缩系数不同而导致的失配问题。而正如上文所提到的，一块普通的8英寸硅晶圆片可以制造数千至一万多个应变计芯片，从此也可以看出本应变计芯片的制造成本低的特点。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案，而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细地说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。

Claims (21)

  1. 一种MEMS应变计芯片，包括相互连接的衬底、器件部以及盖板，其特征在于：所述衬底与所述器件部之间以及所述器件部与所述盖板之间形成有氧化硅层；所述衬底以及所述盖板上分别形成有凹陷部，衬底凹陷部与盖板凹陷部相连接并形成一空腔，所述器件部位于所述空腔内；所述器件部包括桥接部以及压阻测量元件，所述压阻测量元件设置在所述桥接部上。
  2. 如权利要求1所述的应变计芯片，其特征在于：所述桥接部的两端与所述空腔的两端相连接。
  3. 如权利要求1所述的应变计芯片，其特征在于：所述器件部中还包括悬臂梁，所述压阻测量元件设置在所述悬臂梁上。
  4. 如权利要求2或3所述的应变计芯片，其特征在于：所述器件部中包括至少一根桥接部以及至少一对悬臂梁，所述桥接部与所述悬臂梁相互平行；每根所述桥接部上形成有两个所述压阻测量元件，每根所述悬臂梁上形成有一个所述压阻测量元件。
  5. 如权利要求4所述的应变计芯片，其特征在于：所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
  6. 如权利要求1所述的应变计芯片，其特征在于：所述器件部包括至少两根相互垂直的所述桥接部，每根所述桥接部上形成有两个所述压阻测量元件。
  7. 如权利要求6所述的应变计芯片，其特征在于：所述器件部中还包括悬臂梁，所述压阻测量元件设置在所述悬臂梁上。
  8. 如权利要求7所述的应变计芯片，其特征在于：所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
  9. 如权利要求3或7所述的应变计芯片，其特征在于：所述压阻测量元件的上下方及侧壁均形成有氧化硅隔离层。
  10. 如权利要求1所述的应变计芯片，其特征在于：所述压阻测量元件的末端形成有金属触点。
  11. 如权利要求1所述的应变计芯片，其特征在于：所述应变计芯片为绝缘体上硅结构，包括上硅层、下硅层以及氧化硅埋层，所述下硅层中形成有空腔；其中，所述衬底位于所述下硅层中，所述器件部位于所述上硅层中，所述上硅层与所述下硅层之间设置有所述氧化硅埋层。
  12. 如权利要求11所述的应变计芯片，其特征在于：所述器件部是设置在{100}晶体平面上的P型硅，所述压阻测量元件设置在<110>晶体方向上。
  13. 如权利要求11所述的应变计芯片，其特征在于：所述器件部是设置在{100}晶体平面上的N型硅，所述压阻测量元件设置在<100>晶体方向上。
  14. 如权利要求11所述的应变计芯片，其特征在于：所述器件部是设置在{110}晶体平面上的P型硅，所述压阻测量元件设置在<110>或<111>晶体方向上。
  15. 如权利要求11所述的应变计芯片，其特征在于：所述器件部是设置在{110}晶体平面上的N型硅，所述压阻测量元件设置在<100>晶体方向上。
  16. 如权利要求11所述的应变计芯片，其特征在于：所述器件部是设置在{111}晶体平面上的P型硅。
  17. 一种MEMS应变计芯片的制造工艺，其特征在于：所述制造工艺包括以下步骤：
    第一步，在预先加工带有空腔的绝缘体上硅硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
    第二步，通过光刻及离子植入，对所述绝缘体上硅的上硅层进行局部掺杂；形成高导电区域；
    第三步，通过光刻以及刻蚀，在所述上硅层上刻蚀出多个深至氧化硅埋层的槽；形成多个压阻测量元件；
    第四步，在所述槽内生长或淀积一层氧化硅层；
    第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多个深至所述上硅层的孔；并在所述孔内淀积金属并引出电极；
    第六步，利用光刻和刻蚀，对顶面的所述氧化硅层，所述上硅层以及所述氧化硅埋层进行刻蚀出深至下硅层空腔的槽；形成可自由活动的桥接部及悬臂梁；
    第七步，将预先加工有凹陷部的盖板硅晶圆片与所述绝缘体上硅硅晶圆片的顶面进行键合；
    第八步，通过研磨及划片，将所述已键合的硅晶圆片减厚及分割，形成完整的MEMS应变计芯片。
  18. 根据权利要求17所述的MEMS应变计芯片的制造工艺，其特征在于：对所述盖板的凹陷部的加工步骤包括：通过光刻和刻蚀，在所述盖板上刻蚀出凹陷部。
  19. 根据权利要求17所述的MEMS应变计芯片的制造工艺，其特征在于：所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
  20. 根据权利要求17所述的MEMS应变计芯片的制造工艺，其特征在于：所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
  21. 根据权利要求17所述的MEMS应变计芯片的制造工艺，其特征在于：所述用于湿法腐蚀氧化硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氟酸以及缓冲氢氟酸。
PCT/CN2016/000370 2015-08-17 2016-07-08 一种mems应变计芯片及其制造工艺 WO2017028466A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/753,147 US10775248B2 (en) 2015-08-17 2016-07-08 MEMS strain gauge sensor and manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510505712.3A CN105241369B (zh) 2015-08-17 2015-08-17 一种mems应变计芯片及其制造工艺
CN201510505712.3 2015-08-17

Publications (1)

Publication Number Publication Date
WO2017028466A1 true WO2017028466A1 (zh) 2017-02-23

Family

ID=55039103

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/000370 WO2017028466A1 (zh) 2015-08-17 2016-07-08 一种mems应变计芯片及其制造工艺

Country Status (3)

Country Link
US (1) US10775248B2 (zh)
CN (1) CN105241369B (zh)
WO (1) WO2017028466A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3410060A1 (de) * 2017-05-29 2018-12-05 voestalpine Stahl GmbH Dehnungsmessstreifen und metallband mit einer beschichtung für solch einen dehnungsmessstreifen
AT520955A1 (de) * 2018-01-18 2019-09-15 Engel Austria Gmbh Messvorrichtung zur Messung des Abstands zweier ausgewählter Punkte
CN114031032A (zh) * 2021-11-10 2022-02-11 河海大学 一种用于多层键合mems器件的跨层过刻坡度测试结构及测试方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105241600B (zh) * 2015-08-17 2017-12-29 中国科学院地质与地球物理研究所 一种mems压力计芯片及其制造工艺
CN105241369B (zh) * 2015-08-17 2018-02-09 王文 一种mems应变计芯片及其制造工艺
CN105698664A (zh) * 2016-03-28 2016-06-22 上海数久信息科技有限公司 一种适用于混凝土的应变的检测装置及方法
CN106124117B (zh) * 2016-06-14 2019-04-23 中国科学院地质与地球物理研究所 一种双空腔压力计芯片及其制造工艺
US9670061B1 (en) * 2016-09-12 2017-06-06 International Business Machines Corporation Flexible electronics for wearable healthcare sensors
US20190015702A1 (en) * 2017-07-17 2019-01-17 Aurora Flight Sciences Corporation Dynamic Load Sensor for Microgravity
CN108120858B (zh) * 2017-12-20 2020-05-26 中国科学院半导体研究所 自激励自检测探针及其制作方法
CN109211089A (zh) * 2018-11-14 2019-01-15 蚌埠市长达力敏仪器有限责任公司 一种soi耐高温半导体应变计及其制备方法
KR20200109401A (ko) * 2019-03-12 2020-09-23 삼성디스플레이 주식회사 터치 센서 및 표시 장치
CN110002395A (zh) * 2019-04-10 2019-07-12 北京盛通恒瑞科贸有限公司 一种压阻式双轴运动传感器及其制作方法
CN110207586B (zh) * 2019-05-23 2020-09-18 潍坊歌尔微电子有限公司 一种磁传感器芯片中磁阻的布置结构及磁传感器芯片
CN110567619B (zh) * 2019-09-20 2024-11-01 苏州知芯传感技术有限公司 一种高灵敏度压力传感器
CN111298854B (zh) * 2020-02-27 2021-08-06 西人马联合测控（泉州）科技有限公司 芯片的成型方法以及晶圆
US20230144931A1 (en) * 2020-03-19 2023-05-11 Shenzhen New Degree Technology Co., Ltd. Pressure-sensitive structure and electronic device
CN111504526B (zh) * 2020-05-29 2021-05-28 西安交通大学 具有应力集中结构的压阻式压力传感器芯片及其制备方法
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture
CN112034017A (zh) * 2020-09-16 2020-12-04 电子科技大学 一种基于晶圆级封装的微型热导检测器及其制备方法
CN113697757B (zh) * 2021-08-26 2023-12-29 上海交通大学 一种金属复合柔性衬底及其制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101248340A (zh) * 2005-08-24 2008-08-20 通用电气公司 压力传感器及其制造方法
US7861575B2 (en) * 2007-12-17 2011-01-04 Electronics And Telecommunications Research Institute Micro gas sensor and manufacturing method thereof
CN102583232A (zh) * 2010-12-15 2012-07-18 通用电气公司 用于制造传感器的方法
CN103708406A (zh) * 2013-12-12 2014-04-09 中国计量学院 一种可隔离封装应力的谐振式红外探测器结构及制作方法
CN104089642A (zh) * 2014-06-13 2014-10-08 浙江工业大学 一种压阻式加速度、压力集成传感器及其制造方法
CN104819790A (zh) * 2014-01-31 2015-08-05 精工爱普生株式会社 物理量传感器、高度计、电子设备和移动体
CN104817053A (zh) * 2014-01-31 2015-08-05 精工爱普生株式会社 Mems器件、压力传感器、高度计、电子设备和移动体
CN105241369A (zh) * 2015-08-17 2016-01-13 王文 一种mems应变计芯片及其制造工艺
CN105241600A (zh) * 2015-08-17 2016-01-13 中国科学院地质与地球物理研究所 一种mems压力计芯片及其制造工艺

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2457616A (en) 1946-07-16 1948-12-28 Douglas Aircraft Co Inc Metal foil type strain gauge and method of making same
FR2951014B1 (fr) * 2009-10-06 2011-11-25 Commissariat Energie Atomique Structure d'actionnement piezoelectrique comportant une jauge de contrainte piezoresistive integree et son procede de realisation
US8569092B2 (en) * 2009-12-28 2013-10-29 General Electric Company Method for fabricating a microelectromechanical sensor with a piezoresistive type readout
US20110284995A1 (en) * 2010-05-21 2011-11-24 Sand9, Inc. Micromechanical membranes and related structures and methods
US20130130502A1 (en) * 2010-05-21 2013-05-23 Sand 9, Inc. Micromechanical membranes and related structures and methods
US9105492B2 (en) * 2012-05-08 2015-08-11 LuxVue Technology Corporation Compliant micro device transfer head
ITTO20120515A1 (it) * 2012-06-14 2013-12-15 St Microelectronics Nv Assemblaggio di un dispositivo integrato a semiconduttori e relativo procedimento di fabbricazione
JP2015123547A (ja) * 2013-12-26 2015-07-06 株式会社村田製作所 ウエハ、電子部品、ウエハの製造方法及び電子部品の製造方法
CN104062045B (zh) * 2014-06-13 2017-09-15 江苏英特神斯科技有限公司 一种压阻式压力传感器及其制造方法
JP2016095267A (ja) * 2014-11-17 2016-05-26 セイコーエプソン株式会社 電子デバイス、物理量センサー、圧力センサー、高度計、電子機器および移動体

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101248340A (zh) * 2005-08-24 2008-08-20 通用电气公司 压力传感器及其制造方法
US7861575B2 (en) * 2007-12-17 2011-01-04 Electronics And Telecommunications Research Institute Micro gas sensor and manufacturing method thereof
CN102583232A (zh) * 2010-12-15 2012-07-18 通用电气公司 用于制造传感器的方法
CN103708406A (zh) * 2013-12-12 2014-04-09 中国计量学院 一种可隔离封装应力的谐振式红外探测器结构及制作方法
CN104819790A (zh) * 2014-01-31 2015-08-05 精工爱普生株式会社 物理量传感器、高度计、电子设备和移动体
CN104817053A (zh) * 2014-01-31 2015-08-05 精工爱普生株式会社 Mems器件、压力传感器、高度计、电子设备和移动体
CN104089642A (zh) * 2014-06-13 2014-10-08 浙江工业大学 一种压阻式加速度、压力集成传感器及其制造方法
CN105241369A (zh) * 2015-08-17 2016-01-13 王文 一种mems应变计芯片及其制造工艺
CN105241600A (zh) * 2015-08-17 2016-01-13 中国科学院地质与地球物理研究所 一种mems压力计芯片及其制造工艺

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3410060A1 (de) * 2017-05-29 2018-12-05 voestalpine Stahl GmbH Dehnungsmessstreifen und metallband mit einer beschichtung für solch einen dehnungsmessstreifen
WO2018219976A1 (de) * 2017-05-29 2018-12-06 Voestalpine Stahl Gmbh Dehnungsmessstreifen und metallband mit solch einem dehnungsmessstreifen
CN110945314A (zh) * 2017-05-29 2020-03-31 奥钢联钢铁公司 应变测量条和带有该应变测量条的金属带
US11156512B2 (en) 2017-05-29 2021-10-26 Voestalpine Stahl Gmbh Strain gauge and metal strip having a strain gauge of this kind
AT520955A1 (de) * 2018-01-18 2019-09-15 Engel Austria Gmbh Messvorrichtung zur Messung des Abstands zweier ausgewählter Punkte
AT520955B1 (de) * 2018-01-18 2020-08-15 Engel Austria Gmbh Messvorrichtung zur Messung des Abstands zweier ausgewählter Punkte
US11016115B2 (en) 2018-01-18 2021-05-25 Engel Austria Gmbh Measuring device for measuring the space of two selected points on a shaping machine or handling apparatus
CN114031032A (zh) * 2021-11-10 2022-02-11 河海大学 一种用于多层键合mems器件的跨层过刻坡度测试结构及测试方法

Also Published As

Publication number Publication date
US20180299335A1 (en) 2018-10-18
CN105241369B (zh) 2018-02-09
US10775248B2 (en) 2020-09-15
CN105241369A (zh) 2016-01-13

Similar Documents

Publication Publication Date Title
WO2017028466A1 (zh) 一种mems应变计芯片及其制造工艺
US11226251B2 (en) Method of making a dual-cavity pressure sensor die
WO2017028465A1 (zh) 一种mems压力计芯片及其制造工艺
US11255740B2 (en) Pressure gauge chip and manufacturing process thereof
Kumar et al. Effect of piezoresistor configuration on output characteristics of piezoresistive pressure sensor: an experimental study
CN112284607B (zh) 一种十字岛耐高温耐腐蚀压力传感器芯片及制备方法
KR101652369B1 (ko) 습식 및 건식 식각공정을 이용한 압저항형 압력센서 제조방법
CN109342836B (zh) 基于压电压阻式宽频高场强微型电场传感器的生产工艺
CN105668500B (zh) 一种高灵敏度宽量程力传感器及其制造方法
US6763719B2 (en) Acceleration sensor
KR20030026872A (ko) 가속도 센서
WO2013020275A1 (zh) 一种mems压阻式拉压力芯片及传感器的制作方法
CN112284605B (zh) 一种十字岛梁膜高温微压传感器芯片及制备方法
KR100904994B1 (ko) 압력센서 제조방법 및 그 구조
CN113465794B (zh) 一种双空腔压力计芯片及其制造工艺
CN1182587C (zh) 耐高温固态压阻式平膜力敏芯片及其制作方法
CN112284606B (zh) 一种t型交叉梁十字岛膜压力传感器芯片及制备方法
CN113447171B (zh) 一种压力计芯片及其制造工艺
CN116839771B (zh) 一种单轴敏感的集成应力传感器及其设计方法
Basov et al. Investigation of High Sensitivity Piezoresistive Pressure Sensors for-0.5…+ 0.5 kPa
CN117760486A (zh) 一种soi基压力温度集成微纳传感器及其制备方法
CN113063529A (zh) 一种微机械谐振式压力传感器及制造方法
CN117804647A (zh) 一种高温高灵敏度压力传感器芯片及加工方法
CN116878702A (zh) 抗电磁干扰的mems压阻式压力传感器及其制备方法
CN113960381A (zh) 一种非接触式电场测量传感器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16836335

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 15753147

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 16836335

Country of ref document: EP

Kind code of ref document: A1