WO2016111142A1

WO2016111142A1 - Washless flux, and method for manufacturing semiconductor package

Info

Publication number: WO2016111142A1
Application number: PCT/JP2015/085518
Authority: WO
Inventors: 有希西迫; 恭夫白井; 鈴木　理
Original assignee: ナミックス株式会社
Priority date: 2015-01-07
Filing date: 2015-12-18
Publication date: 2016-07-14
Also published as: JP2016124021A; JP6513950B2; TW201634168A; TWI699253B

Abstract

The invention of the present application provides a washless flux comprising (A) a solvent having such a property that the temperature at which the mass thereof is reduced to 50% of the original value is 160 to 210ºC as measured by a thermogravimetric analysis and (B) a di- or tri-carboxylic acid having such a property that the temperature at which the mass thereof is reduced to 50% of the original value is 190 to 320°C as measured by a thermogravimetric analysis, wherein the component (B) is contained in an amount of 0.3 to 3.0 parts by mass relative to 100 parts by mass of the washless flux. The washless flux can be used in a semiconductor packaging process comprising: applying the washless flux between a solder bump, which is formed on a semiconductor chip, and a wiring line, which is formed on a substrate and is coated with a solder, at room temperature; soldering the solder bump with the wiring line; cooling the soldered product to 100 to 120°C; filling an underfill material between the semiconductor chip and the substrate while keeping at the same temperature; and curing the underfill material.

Description

No-clean flux and method for manufacturing semiconductor package

The present invention relates to a no-clean flux and a method for manufacturing a semiconductor package. In particular, after solder bumps formed on a semiconductor chip and solder-plated wiring formed on a substrate are soldered, an underfill material is filled at 100 to 120 ° C. without cooling to room temperature, and then cured. The present invention relates to a no-clean flux suitable for a soldering method in a package manufacturing method, and a semiconductor package manufacturing method using the no-clean flux.

In recent years, flip chip bonding has been used as a semiconductor package mounting method that can cope with higher density and higher frequency of wiring of electronic devices. In general, in flip chip bonding, a solder bump formed on a semiconductor chip and a solder-plated wiring formed on a substrate are soldered, and then the gap between the semiconductor chip and the substrate is a material called an underfill material. Seal with.

In the next generation semiconductor package to cope with higher density and higher frequency of wiring, etc., in addition to narrowing the gaps of solder bumps and wiring, it is required to increase the size of the chip by making it multi-core. When the gap is narrowed or the chip is enlarged, a residue of flux used during soldering becomes a problem.

In the case of this narrow gap, since a cleaning defect is likely to occur, a flux residue is likely to be generated. For this reason, a residue-free flux is required.

Also, in the current manufacturing process, solder bumps formed on a semiconductor chip and solder plated wiring formed on a substrate are soldered, cooled to room temperature, and then the gap between the semiconductor chip and the substrate is reduced under Sealed with fill material. Currently, when increasing the size of a chip, when the vicinity of a solder bump is observed with an ultrasonic microscope, a good bonding portion appears gray, whereas a bonding defect called white bump that causes the bonding portion to appear white occurs. It is easy.

This white bump occurs after soldering and before sealing with the underfill material, and it is considered that the stress caused by the difference in thermal expansion between the semiconductor chip and the substrate is promoted by the enlargement of the substrate. .

As a method for suppressing the occurrence of white bumps, after soldering, do not cool to room temperature, cool to 100-120 ° C, fill with underfill material at 100-120 ° C, and undercoat at 130-160 ° C. A manufacturing method for curing a fill material (hereinafter referred to as a manufacturing method using a non-cleaning flux) has been studied (Non-Patent Document 1). This manufacturing method using no-cleaning flux has the advantage that the stress caused by the difference in thermal expansion between the semiconductor chip and the substrate can be reduced after soldering, and the manufacturing process is shortened. On the other hand, in the manufacturing method using the non-cleaning flux, since the flux residue cannot be cleaned after soldering, a non-residual flux is required. FIG. 1 is a diagram illustrating an example of a manufacturing method using no-clean flux. FIG. 1A is an example of a conventional process, and B is an example of a manufacturing method using no-clean flux. As can be seen from FIG. 1, the major difference between A and B is the temperature after reflow (indicated as “Reflow” in FIG. 1). As in A, when cooled to room temperature after reflow, white bumps are likely to occur during cooling. On the other hand, as in B, the occurrence of white bumps can be suppressed by filling the underfill material at 100 to 120 ° C. (110 ° C. in FIG. 1) without cooling to room temperature after reflow.

The residue-free flux for soldering includes pimelic acid and the first and second organic solvents, and the second organic solvent has a higher boiling point than the first solvent, and the pimelic acid and the above A flux composition (Patent Document 1) is disclosed in which the second organic solvent is soluble in the first organic solvent.

However, when a flux composition containing pimelic acid is used in a production method using no-clean flux, there is a problem that a flux residue remains after soldering and the underfill material cannot be injected properly. Currently, no residue-free flux that can be used in methods that do not cool to room temperature is commercially available.

Further, a storage-stable gel containing a specific carboxylic acid component, a specific amine component, and a specific solvent (Patent Document 2) is also disclosed. However, when this gel is used for soldering a flip chip having a size of 10 mm □ or more, a large amount of residue remains, and the carboxylic acid component is not completely dissolved in the gel and the gel is not smooth. There is.

Japanese Patent Application Laid-Open No. 07-323390 JP 2009-514683 A

The present invention is a non-residue that can be used in a manufacturing method in which, after soldering, after cooling to 100-120 ° C. without cooling to room temperature, filling the underfill material at 100-120 ° C. and then curing the underfill material The purpose is to provide flux.

The present invention relates to a non-cleaning flux and a method for manufacturing a semiconductor package that have solved the above problems by having the following configuration.
[1] A non-cleaning flux is applied at room temperature between a solder bump formed on a semiconductor chip and a solder plated wiring formed on a substrate.
After soldering the solder bump formed on the semiconductor chip and the solder plated wiring formed on the substrate at 240 to 270 ° C.,
Cool to 100-120 ° C,
A non-cleaning flux used in a semiconductor package process in which an underfill material is filled between a semiconductor chip and a substrate while being maintained at 100 to 120 ° C., and the underfill material is cured at 130 to 160 ° C.
(A) Solvent whose mass is reduced to 50% when measured at a rate of temperature increase of 10 ° C./min in thermogravimetric analysis, and (B) Temperature increase in thermogravimetric analysis The temperature at which the mass is reduced to 50% when measured at a rate of 10 ° C./min contains a dicarboxylic acid or tricarboxylic acid having a temperature of 190 to 320 ° C., and the component (B) is added to 100 parts by mass of the no-clean flux. And a non-cleaning flux characterized by containing 0.3 to 3.0 parts by mass.
[2] Furthermore, (C) a thermogravimetric analysis contains a tertiary amine having a temperature at which the mass decreases to 50% when measured at a rate of temperature increase of 10 ° C./min, from 130 to 170 ° C .; The non-cleaning flux according to the above [1].
[3] The non-cleaning flux according to the above [1], wherein the component (B) is an aliphatic dicarboxylic acid.
[4] The non-cleaning flux according to the above [1], wherein the component (C) is tributylamine.
[5] The non-cleaning flux according to the above [1], wherein the solder of the solder bump formed on the semiconductor chip is tin-silver based.
[6] The non-cleaning flux according to the above [1], wherein the solder of the solder-plated wiring formed on the substrate is a tin-silver-copper system.
[7] A step of applying the non-cleaning flux according to the above [1] at room temperature between the solder bump formed on the semiconductor chip and the solder plated wiring formed on the substrate.
Soldering solder bumps formed on the semiconductor chip and solder plated wiring formed on the substrate at 240 to 270 ° C .;
A step of cooling to 100 to 120 ° C. and a step of filling the underfill material between the semiconductor chip and the substrate while maintaining the temperature at 100 to 120 ° C. and curing the underfill material at 130 to 160 ° C. in this order are included. And manufacturing method of semiconductor package.
[8] The solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate are heated at a temperature increase rate of 2.5 to 5.0 ° C./second and 30 to 240 to 270 ° C. The method for producing a semiconductor package according to [7] above, comprising a step of soldering for 70 seconds.
[9] After the step of soldering the solder bumps formed on the semiconductor chip and the solder plated wiring formed on the substrate at 240 to 270 ° C., the temperature decreasing rate is 1.0 to 3.0 ° C./second. The method for producing a semiconductor package according to the above [7], comprising a step of cooling to 100 to 120 ° C.
[10] A semiconductor package manufactured by the method for manufacturing a semiconductor package described in [7] above.

According to the present invention [1], there is provided a manufacturing method in which, after soldering, after cooling to 100 to 120 ° C. without cooling to room temperature, filling the underfill material at 100 to 120 ° C. and then curing the underfill material. A usable residue-free flux can be provided.

According to the present invention [7], it is possible to easily manufacture a semiconductor package corresponding to the narrowing of the gap between the solder bumps and the wiring and the enlargement of the chip due to the multicore.

According to the present invention [10], it is possible to provide a semiconductor package that can cope with the narrowing of the gaps of solder bumps and wiring and the enlargement of the chip due to the multicore.

It is a figure explaining an example of the manufacturing method by a no-clean flux. It is a figure for demonstrating the manufacturing method of the semiconductor package of this invention. The upper photo shows the residue after evaluation, and the lower photo shows the connectivity evaluation. It is an ultrasonic microscope (C-SAM) image of 10 mm □ and 20 mm □ chips of Comparative Example 4 produced by a manufacturing method using no-cleaning flux.

[No-clean flux]
The no-clean flux of the present invention is
Applying no-clean flux at room temperature between the solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate,
After soldering the solder bump formed on the semiconductor chip and the solder plated wiring formed on the substrate at 240 to 270 ° C.,
Cool to 100-120 ° C,
A non-cleaning flux used in a semiconductor package process in which an underfill material is filled between a semiconductor chip and a substrate while being maintained at 100 to 120 ° C., and the underfill material is cured at 130 to 160 ° C.
(A) a solvent having a temperature at which the mass decreases to 50% (hereinafter referred to as T ₅₀ ) when measured at 10 ° C./min in a thermogravimetric analysis at a temperature rising rate of 160 to 210 ° C., and (B) The thermogravimetric analysis contains a dicarboxylic acid or tricarboxylic acid whose mass decreases to 50% when measured at a rate of temperature increase of 10 ° C / min. It is characterized by containing 0.3 to 3.0 parts by mass with respect to 100 parts by mass of the cleaning flux. The present inventor has conducted intensive research on the flux composition and reflow conditions in order to obtain a solder bump, appropriate activation power for solder-plated wiring, volatility, and to obtain a flux with very little flux residue after reflow. And found a residue-free flux suitable for the production method using no-clean flux. Here, the appropriate activation force for solder bumps and solder-plated wiring means that the oxide film of the solder bumps and solder-plated wiring can be removed, and no voids are generated and the solder voids are generated. This means that the occurrence of

The component (A) mainly acts as a solvent in the no-clean flux. Component (A) is a solvent having a temperature at which the mass decreases to 50% when measured at a rate of temperature increase of 10 ° C./min by thermogravimetric analysis, at 160 to 210 ° C. As the component (A), ethylene glycol monophenyl ether (EPH, C ₆ H ₅ OCH ₂ CH ₂ OH, T ₅₀ : 181 ° C.), 2-ethyl-1,3-hexanediol (T ₅₀ : 189 ° C.), 2-ethyl-1,3-hexanediol: isobornylhexanol (Telsolve MTPH manufactured by Nippon Terpene Chemical) = 1: 1 mixed solvent (T ₅₀ : 186 ° C.) and the like, ethylene glycol monophenyl ether, 2- A mixed solvent of ethyl-1,3-hexanediol, 2-ethyl-1,3-hexanediol: isobornylhexanol (Telsolve MTPH manufactured by Nippon Terpene Chemical) = 1: 1 is preferable.

In addition, the component (A) is a thermogravimetric analysis, a solvent whose temperature is reduced to 50% when measured at a heating rate of 10 ° C./min, and a solvent whose temperature is from 160 to 190 ° C. A mixed solvent with a certain solvent (for example, isobornyl hexanol (Tg: 234 ° C.)) is preferable from the viewpoint of solder connectivity. In particular, when a large semiconductor chip of 20 mm □ level is used, (A) the mass ratio of the solvent at 160 to 190 ° C. and the solvent mixture at 200 to 240 ° C. is 1: (2 or less) Is preferred, 1: (0.1-2) is more preferred, and 1: (0.5-2) is even more preferred. When the mass ratio of the solvent having a temperature of 160 to 190 ° C. and the solvent mixture of 200 to 240 ° C. is 1: (4 to 5), the rate of temperature rise is 10 ° C./min. In addition, the temperature at which the mass decreases to 50% tends to be higher than 190 ° C. (that is, not easily the component (A)), and the residue tends to remain. Further, the component (A) is preferably 95 to 99.7 parts by mass, more preferably 97 to 99.5 parts by mass with respect to 100 parts by mass of the non-cleaning flux.

The component (B) mainly acts as an activator in the no-clean flux. Component (B) is a dicarboxylic acid or tricarboxylic acid having a temperature at which the mass decreases to 50% when measured at a rate of temperature increase of 10 ° C./minute by thermogravimetric analysis at 190 to 320 ° C. The component (B) mainly functions as an activator. As the component (B), oxalic acid (HOOCCOOH, T ₅₀ : 195 ° C.), succinic acid (HOOC (CH ₂ ) ₂ COOH, T ₅₀ : 230 ° C.), adipic acid (HOOC (CH ₂ ) ₄ COOH, T ₅₀ : 268 ° C.) and 1,2,4-cyclohexanetricarboxylic acid (H-TMA, T ₅₀ : 310 ° C.), and oxalic acid, succinic acid, adipic acid, and 1,2,4-cyclohexanetricarboxylic acid are preferred. Here, the compounds mentioned as the component (B) are solid, but those that dissolve in the component (A) are preferable from the viewpoint of uniform dispersibility in the non-cleaning flux. The component (B) is more preferably an aliphatic dicarboxylic acid.

The component (B) is contained in an amount of 0.3 to 3.0 parts by mass and preferably 0.5 to 3.0 parts by mass with respect to 100 parts by mass of the non-cleaning flux. If it is less than 0.3 part by mass, the connectivity tends to be poor, and if it exceeds 3.0 parts by mass, the residue tends to remain.

The non-cleaning flux further contains (C) a tertiary amine having a temperature at which the mass decreases to 50% when measured at a rate of temperature increase of 10 ° C / min in thermogravimetric analysis at 130 to 170 ° C. Then, it is preferable from a viewpoint of the dissolution stability of (B) component, and it is more preferable in it being tributylamine. The component (C) is preferably used when the component (B) is difficult to dissolve in the component (A). The component (C) mainly acts as an activator.

The component (C) is preferably 10 times or less, more preferably 5 times or less, and even more preferably 2 times or less with respect to the mass of the component (B). If the component (C) is more than 10 times, the solder connectivity may be deteriorated. Moreover, the (C) component tends to exhibit the effect of addition as it is 0.5 times or more with respect to the mass of (B) component.

The non-cleaning flux can be further blended with additives and the like as necessary, as long as the object of the present invention is not impaired.

The no-clean flux is suitable when the solder bump solder formed on the semiconductor chip is tin-silver based. Further, the no-clean flux is suitable when the solder of the solder plated wiring formed on the substrate is a tin-silver-copper system.

[Underfill material]
Although an underfill material is not specifically limited, Hereinafter, the epoxy resin composition which is a preferable underfill material is demonstrated. The underfill material preferably contains at least (UA) epoxy resin and (UB) curing agent.

(UA) component includes bisphenol A type epoxy resin, brominated bisphenol A type epoxy resin, bisphenol F type epoxy resin, naphthalene type epoxy resin, biphenyl type epoxy resin, novolac type epoxy resin, aminophenol type epoxy resin, alicyclic ring Type epoxy resin, ether type or polyether type epoxy resin, oxirane ring-containing epoxy resin, etc., bisphenol F type epoxy resin, aminophenol type epoxy resin, bisphenol A type epoxy resin, naphthalene type epoxy resin are underfill materials From the viewpoint of glass transition point, reflow resistance, and moisture resistance.

Bisphenol F type epoxy resin is preferably represented by the formula (1):

In the formula, n represents an average value, preferably 0 to 6, more preferably 0 to 3. The epoxy equivalent is preferably 150 to 900 g / eq.

The aminophenol-based epoxy resin is preferably a formula (2):

It is more preferable that two functional groups are in the ortho position or the para position.

The bisphenol A type epoxy resin is preferably represented by the formula (3):

In the formula, m represents an average value, and an epoxy resin having 0 to 6 and particularly preferably 0 to 3 is preferable. The epoxy equivalent is preferably 170 to 1000 g / eq.

(UA) component may be used alone or in combination of two or more.

Examples of the (UB) component include amine-based curing agents, acid anhydride-based curing agents, phenol-based curing agents, and the like, and amine-based curing agents are preferable from the viewpoint of reflow resistance and moisture resistance of the underfill material.

Amine curing agents include aliphatic polyamines; aromatic amines; modified polyamines such as polyaminoamides, polyaminoimides, polyaminoesters and polyaminoureas; tertiary amines; imidazoles; hydrazides; dicyanamides; An aromatic amine compound is preferable.

It is more preferable that the aromatic amine compound includes an aromatic amine compound having one aromatic ring and / or an aromatic amine compound having two aromatic rings.

Examples of the aromatic amine compound having one aromatic ring include metaphenylenediamine and the like, and the formula (4) or the formula (5):

What is shown is preferable.

Examples of the aromatic amine compound having two aromatic rings include diaminodiphenylmethane and diaminodiphenylsulfone, and the formula (6) or the formula (7):

(Wherein R represents hydrogen or an alkyl group having 1 to 5 carbon atoms) is preferred, and in formula (8) or formula (9), R is an alkyl group having 2 carbon atoms. Those are more preferred.

(UB) component may be used alone or in combination of two or more.

It is preferable that the underfill material further contains a (UC) filler from the viewpoint of the thermal expansion coefficient of the cured underfill material. Examples of the (UC) component include silica, alumina, silicon nitride, mica, white carbon, and the like, and silica is preferable from the viewpoints of lowering the thermal expansion coefficient of the underfill material after curing and cost. As silica, various silicas used in this technical field such as amorphous silica, crystalline silica, fused silica, pulverized silica, and nano silica can be used, and the thermal expansion coefficient of the underfill material after curing is reduced. To amorphous silica is preferred. The particle size of the component (C) is preferably from 0.1 to 2.0 μm, more preferably from 0.1 to 1.0 μm, from the viewpoint of filling into the gap between the semiconductor chip and the substrate. Here, the average particle diameter is measured by a laser diffraction particle size distribution measuring apparatus. Moreover, the shape of (C) component is not specifically limited, A spherical shape, flake shape, an indeterminate form, etc. are mentioned, From the viewpoint of the fluidity | liquidity of the liquid resin composition for sealing, a spherical shape is preferable.

(UC) component may be used alone or in combination of two or more.

The underfill material contains 20 to 100 parts by mass, more preferably 40 to 60 parts by mass of the component (UB) with respect to 100 parts by mass of the component (UA). And from the viewpoint of moisture resistance.

Further, the component (UC) is contained in an amount of 160 to 400 parts by mass, more preferably 200 to 350 parts by mass with respect to 100 parts by mass of the component (UA), and the fluidity of the underfill material and the cured underfill material From the viewpoint of lowering the thermal expansion coefficient, it is preferable.

In the underfill material, as long as the object of the present invention is not impaired, a pigment such as carbon black, a dye, a silane coupling agent, an antifoaming agent, an antioxidant, other additives, etc. A solvent etc. can be mix | blended.

The underfill material can be obtained, for example, by stirring, melting, mixing, and dispersing the (UA) component to the (UC) component and other additives simultaneously or separately, with heat treatment as necessary. . The mixing, stirring, dispersing and the like devices are not particularly limited, and a raikai machine equipped with a stirring and heating device, a three-roll mill, a ball mill, a planetary mixer, a bead mill and the like can be used. . Moreover, you may use combining these apparatuses suitably.

The underfill material preferably has a viscosity at a temperature of 25 ° C. of 1 to 100 Pa · s. Here, the viscosity is measured with a viscometer manufactured by Brookfield (model number: DV-1).

The underfill material is preferably cured at 130 to 160 ° C. for 90 to 150 minutes.

[Method of manufacturing semiconductor package]
A method for manufacturing a semiconductor package of the present invention includes a step of applying the above-described non-cleaning flux at room temperature between a solder bump formed on a semiconductor chip and a solder-plated wiring formed on a substrate,
Soldering solder bumps formed on the semiconductor chip and solder plated wiring formed on the substrate at 240 to 270 ° C .;
A step of cooling to 100 to 120 ° C. and a step of filling the underfill material between the semiconductor chip and the substrate while maintaining the temperature at 100 to 120 ° C. and curing the underfill material at 130 to 160 ° C. in this order are included. . FIG. 2 is a view for explaining the method for manufacturing a semiconductor package of the present invention. As shown in FIG. 2, the method for manufacturing a semiconductor package of the present invention uses the above-mentioned non-cleaning flux at room temperature between a solder bump formed on a semiconductor chip and a solder-plated wiring formed on a substrate. Applying step,
A process of soldering solder bumps formed on the semiconductor chip and solder plated wiring formed on the substrate at 240 to 270 ° C. ((1) in FIG. 2);
A process of cooling to 100 to 120 ° C. (between (1) and (2) in FIG. 2) and while maintaining the temperature at 100 to 120 ° C. ((2) in FIG. 2) Step of filling the fill material and curing the underfill material at 130 to 160 ° C. ((3) in FIG. 2)
Are included in this order.

The amount of the above-mentioned non-cleaning flux applied between the solder bump formed on the semiconductor chip and the solder-plated wiring formed on the substrate is preferably 0.02 to 0.08 mg / mm ^2. 0.04 mg / mm ² is most preferable.

In the process of soldering solder bumps formed on a semiconductor chip and solder-plated wiring formed on a substrate at 240 to 270 ° C., no-clean flux exists until just before solder wetting occurs, It is preferable to volatilize later. The step of heating at a rate of temperature increase of 2.5 to 5.0 ° C./second and soldering at 240 to 270 ° C. for 30 to 70 seconds is preferable from the viewpoint of volatilization behavior of the non-cleaning flux.

After the process of soldering the solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate at 240 to 270 ° C., the process of cooling to 100 to 120 ° C. is performed at a temperature drop rate of 1.0 to It is preferable that it is 3.0 ° C./second. When the temperature lowering rate is slower than 1.0 ° C./second, the productivity is deteriorated, and when the temperature lowering rate is higher than 3.0 ° C./second, the yield may be deteriorated.

Examples of the substrate include, but are not limited to, epoxy resin, glass-epoxy resin, polyimide resin, and the like. The solder of the solder-plated wiring formed on the substrate is preferably a tin-silver-copper system that is a lead-free solder alloy because of environmental problems. For the bumps formed on the semiconductor chip, a solder alloy made of tin, lead, copper, bismuth, silver, zinc, indium, etc. can be used. preferable.

The present invention will be described with reference to examples, but the present invention is not limited thereto. In the following examples, parts and% represent parts by weight and% by weight unless otherwise specified.

[Examples 1 to 14, Comparative Examples 1 to 4]
With the formulations shown in Tables 1 to 3, mixing was performed using an ultrasonic cleaner to prepare a no-clean flux. In Tables 1 and 3, 2-ethyl-1,3-hexanediol is described as “diol” and isobornylhexanol as “MTPH”. Moreover, the underfill material was prepared as follows. Nippon Steel & Sumikin Chemicals bisphenol F type epoxy resin (product name: YDF8170): 16.3 parts by mass, Mitsubishi Chemical aminophenol type epoxy resin (product name: EP630): 10.9 parts by mass, Nippon Kayaku amine-based curing agent ( Product name: Kayahard AA): 12.5 parts by mass, Admatex silica filler (Product name: SO-E2, average particle size: 0.5 μm): 60.0 parts by mass, and Shin-Etsu Chemical silane coupling agent ( Product name: KBM403) was mixed using a three-roll mill to prepare an underfill material. The dicarboxylic acid methyl ester mixture (DBE) used in Comparative Example 3 was CH ₃ OOC (CH ₂ ) _n COOCH ₃ (n = 2 to 4).

Using the prepared no-clean flux and underfill material, a semiconductor package was produced as follows. Chips manufactured by Waltz (product name: WALTS-TEG FC150JY_LF (PI) □ 10 mm) are used for 10 mm □ semiconductor chips, and chips manufactured by Waltz Co., Ltd. (product name: WALTS-TEG FC150JY_LF ( (PI) □ 20 mm), 10 mm □ substrate is made by Waltz Corporation (product name: WALTS-KIT 01A150P-10 (SAC)), and 20 mm □ substrate is made by Waltz Corporation substrate (product name: WALTS). -KIT FC150-0103JY_2 × 2 (SAC)) was used.

First, the substrate was baked in an N ₂ atmosphere at 130 ° C. for 2 hours. Next, a non-cleaning flux was applied to the mounting portion of the substrate with a brush. The semiconductor chip was plasma-treated at 400 W for 5 minutes in an Ar atmosphere at the mounting portion.

A semiconductor chip was mounted on the substrate. For mounting, a mounting machine (model number: FCB3) manufactured by Panasonic Factory Solutions Co., Ltd. is used, head temperature: 25 ° C., stage temperature: 25 ° C., load: 36.5 N (1 g per bump), load holding time: The test was performed for 5 seconds. Next, reflow was performed in an N ₂ atmosphere. The reflow was performed in a step of heating up to 260 ° C. at a temperature rising rate of 4.0 ° C./second, soldering at 260 ° C. for 45 seconds, and a step of cooling to 200 ° C. at a temperature falling rate of 2.2 ° C./second.

[Evaluation of residue]
After mounting, the semiconductor chip and the substrate were peeled off, and the residue on the semiconductor chip side and the residue on the substrate side were each observed at 200 times using a CCD camera. The photograph after residue evaluation is shown in the upper part of FIG. As shown on the left side of FIG. 3, “◎” indicates that no residue or stain was observed, “XX” indicates that the residue or stain was very large, and “◎” and “XX”. “○”, “△”, and “×” in three stages. Tables 1 to 3 show the results. FIG. 4 shows ultrasonic microscope (C-SAM) images of 10 mm □ and 20 mm □ chips of Comparative Example 4 produced by a manufacturing method using no-cleaning flux. At this time, after soldering was performed under the above-described conditions, the semiconductor chip was cooled to 110 ° C., kept under 110 ° C., filled with an underfill material between the semiconductor chip and the substrate, and cured at 150 ° C. for 120 minutes. . As can be seen from FIG. 4, in the case of the 20 mm □ chip, more residue was observed than in the case of the 10 mm □ chip.

[Evaluation of connectivity]
After mounting, a DAGE X-ray inspection apparatus (model number: XD7600NT) was used to observe whether the bumps of the semiconductor chip and the pads of the substrate were connected. The photograph after residue evaluation is shown in the lower part of FIG. The left side of FIG. 3 is a case where the connection is good (Example 11), and the right side of FIG. 3 is a case where the connection is bad. When the connection was good, the solder was melted and the bump and the pad were integrated. On the other hand, when the connection is poor, the bump and the pad are not melted, and the bump and the pad are in contact with each other at a point. The connectivity (%) was calculated by [(number of connected bumps) / (total number of bumps) × 100]. Tables 1 to 3 show the results.

As can be seen from Tables 1 to 3, all of Examples 1 to 14 had no residue and good connectivity. Separately, the solder bump formed on the semiconductor chip and the solder plated wiring formed on the substrate are soldered at 260 ° C. for 45 seconds, cooled to 110 ° C., and kept at 110 ° C. As a result of continuously testing the process of filling the underfill material between the chip and the substrate and curing the underfill material at 150 ° C., the underfill material was successfully used. On the other hand, in Comparative Example 1 in which the component (B) was too much, many residues and stains were observed on the 20 mm square chip, and in Comparative Example 2 in which the component (B) was too small, the connectivity was poor. Comparative Example 3 using a dicarboxylic acid methyl ester mixture in place of component (A) has poor connectivity, and Comparative Example 4 has a large amount of residue and stain observed at 10 mm □, and residue and stain at 20 mm □. Was observed very often.

Examples 1, 3 to 6 of a storage-stable gel (Patent Document 2) containing a specific carboxylic acid component, a specific amine component, and a specific solvent were conducted as comparative tests of the present invention (Comparative Examples 5 to 9). In addition, the raw material which is described as candy etc. and whose specific product name is unknown was not used. As a result, the total amount may be 97 parts by mass. Moreover, since the compounding of Example 2 of the storage-stable gel was similar to Example 1, it was not performed.

Table 4 shows these results. As can be seen from Table 4, the storage-stable gels containing the specific carboxylic acid component, the specific amine component, and the specific solvent of Comparative Examples 5 to 9 remained as residues.

For reference, Table 5 shows the temperature at which the mass decreases by 1, 50, 99% when the materials used in Examples and Comparative Examples are measured by thermogravimetric analysis at a heating rate of 10 ° C./min. . In Table 5, 2-ethyl-1,3-hexanediol is described as “diol”, and isobornylhexanol is described as “MTPH”.

As described above, since the no-clean flux of the present invention is residue-free, after soldering, it is not cooled to room temperature, cooled to about 110 ° C., and filled with an underfill material at the same temperature. It is possible to cure the material.

Since the no-clean flux of the present invention is residue-free, after soldering, after cooling to about 110 ° C. without cooling to room temperature, the underfill material is filled at the same temperature and then the underfill material is cured. Is possible and very useful.

Claims

Applying no-clean flux at room temperature between the solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate,
After soldering the solder bump formed on the semiconductor chip and the solder plated wiring formed on the substrate at 240 to 270 ° C.,
Cool to 100-120 ° C,
A non-cleaning flux used in a semiconductor package process in which an underfill material is filled between a semiconductor chip and a substrate while being maintained at 100 to 120 ° C., and the underfill material is cured at 130 to 160 ° C.
(A) Solvent whose mass is reduced to 50% when measured at a rate of temperature increase of 10 ° C./min in thermogravimetric analysis, and (B) Temperature increase in thermogravimetric analysis The temperature at which the mass is reduced to 50% when measured at a rate of 10 ° C./min contains a dicarboxylic acid or tricarboxylic acid having a temperature of 190 to 320 ° C., and the component (B) is added to 100 parts by mass of the no-clean flux. And a non-cleaning flux characterized by containing 0.3 to 3.0 parts by mass.
And (C) a tertiary amine having a temperature at which the mass decreases to 50% when measured at a rate of temperature increase of 10 ° C./min in thermogravimetric analysis is 130 to 170 ° C. No-clean flux as described.
The non-cleaning flux according to claim 1, wherein the component (B) is an aliphatic dicarboxylic acid.
The non-cleaning flux according to claim 1, wherein the component (C) is tributylamine.
The non-cleaning flux according to claim 1, wherein the solder of the solder bump formed on the semiconductor chip is tin-silver based.
The non-cleaning flux according to claim 1, wherein the solder of the solder-plated wiring formed on the substrate is a tin-silver-copper system.
Applying a non-cleaning flux according to any one of claims 1 to 6 at room temperature between a solder bump formed on a semiconductor chip and a solder-plated wiring formed on a substrate;
Soldering solder bumps formed on the semiconductor chip and solder plated wiring formed on the substrate at 240 to 270 ° C .;
A step of cooling to 100 to 120 ° C. and a step of filling the underfill material between the semiconductor chip and the substrate while maintaining the temperature at 100 to 120 ° C. and curing the underfill material at 130 to 160 ° C. in this order are included. And manufacturing method of semiconductor package.
The solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate are heated at a temperature increase rate of 2.5 to 5.0 ° C./second, and 240 to 270 ° C. for 30 to 70 seconds. The manufacturing method of the semiconductor package of Claim 7 including the process to solder.
After the step of soldering the solder bumps formed on the semiconductor chip and the solder-plated wiring formed on the substrate at 240 to 270 ° C., the temperature is lowered from 1.0 to 3.0 ° C./sec. The manufacturing method of the semiconductor package of Claim 7 including the process cooled to degreeC.
A semiconductor package manufactured by the method for manufacturing a semiconductor package according to claim 7.