WO2016101555A1

WO2016101555A1 - Cross scheduling method and device, and storage medium

Info

Publication number: WO2016101555A1
Application number: PCT/CN2015/081402
Authority: WO
Inventors: 赖伟
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-12-24
Filing date: 2015-06-12
Publication date: 2016-06-30
Also published as: CN105790875B; CN105790875A

Abstract

Disclosed is a cross scheduling method, comprising: receiving service information; mapping or demapping data corresponding to the service information to a first timeslot frame; mapping the first timeslot frame to a first inbetween based on a first timeslot location of the first timeslot frame, the first timeslot location being capable of indicating a correspondence between the first timeslot frame and the first inbetween; sending the first inbetween based on a first indication location of the first inbetween, the first indication location being capable of indicating an address of a destination end chip corresponding to the first timeslot frame in the first inbetween, and the destination end chip being a destination end chip corresponding to the service information. Further disclosed are a cross scheduling device and a storage medium

Description

Cross scheduling method, device thereof and storage medium

Technical field

The present invention relates to an optical transport network (OTN) technology, and in particular, to a cross scheduling method, a device thereof, and a storage medium.

Background technique

With the rapid growth of network services, especially the rapid development of broadband, interactive network television (IPTV), video and other services, new requirements have been placed on optical transport network (OTN) technology. E.g,

On the one hand, OTN is required to have a clustered crossover function to provide a large amount of bandwidth to adapt to the continuous growth of services; however, the clustered crossover function requires adding a cross chip in the OTN to enable framing processing in the OTN (Framer) The chip and the cross chip cooperate, but when the cross chip is added to the OTN, the rack of the node including the cross chip and the framer chip is large, and the energy consumption of the node is increased, thereby increasing the cost of the node. Therefore, increasing the clustering crossover function of the cross chip is only applicable to the backbone nodes;

On the other hand, it is also required that the OTN can have a small capacity cross function; however, in the prior art, the above requirements are not met, and therefore, a new type of cross scheduling method is needed to meet the above requirements.

Summary of the invention

In order to solve the existing technical problems, the embodiments of the present invention provide a cross scheduling method, a device thereof, and a storage medium, which can achieve cross-scheduling without using a cross chip.

The technical solution of the embodiment of the present invention is implemented as follows: The embodiment of the present invention provides a cross scheduling method, which is applied to a source chip; the method includes:

Receiving business information;

Mapping or demapping data corresponding to the service information to the first slot frame;

Mapping the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position capable of indicating the first slot frame and the first slot a corresponding relationship of intermediate frames;

Transmitting the first intermediate frame according to the first indication position of the first intermediate frame; the first indication position is capable of indicating a destination chip address corresponding to the first time slot frame in the first intermediate frame; The destination end chip is the destination end chip corresponding to the service information.

In the above solution, when N first time slot frames are mapped in the first intermediate frame, the first first time slot frame and the second first time slot in the N first time slot frames The first time slot position corresponding to each of the Nth first time slot frame is corresponding to the first intermediate frame; the first first time slot frame and the second of the N first time slot frames The destination chip addresses corresponding to the first slot frame to the Nth slot frame are the same; wherein N is a positive integer greater than or equal to 2.

In the above solution, when the received service information is K, the K is a positive integer greater than or equal to 2; the method further includes:

Mapping or de-mapping data corresponding to the K service information to the first slot frame, the second slot frame, the i-th slot frame to the K-th slot frame; wherein the i is greater than or equal to 1 and less than or equal to K Positive integer

Mapping the i th slot frame to an i th intermediate frame based on an i th slot position of the i th slot frame; the i th slot position capable of indicating the i th slot frame and the first i corresponding to the intermediate frame;

Transmitting the ith intermediate frame based on an ith indication position of the ith intermediate frame; the ith indication location is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame The ith target chip is a destination chip corresponding to the ith service information of the K service information.

In the foregoing solution, the sending the i-th intermediate frame includes:

Substituting the header information in the ith intermediate frame with the first header information; the first header information is unified in the first intermediate frame, the second intermediate frame, and the ith intermediate frame to the Kth intermediate frame Frame header information;

The transmission frame header information is the ith intermediate frame of the first frame header information.

The embodiment of the invention further provides a cross scheduling method, which is applied to a destination chip; the method includes:

Receiving a first intermediate frame;

De-mapping the first intermediate frame to a first slot frame;

Mapping or de-mapping the first slot frame to traffic information based on a first slot position of the first slot frame; the first slot position capable of indicating the first slot frame and the Correspondence of business information;

Send the service information.

The embodiment of the invention further provides a cross scheduling device, the device comprising:

a first receiving unit, configured to receive service information;

a first mapping unit, configured to map or demap data corresponding to the service information to the first slot frame;

a second mapping unit, configured to map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position capable of indicating the first Corresponding relationship between the slot frame and the first intermediate frame;

The first sending unit is configured to send the first intermediate frame according to the first indication position of the first intermediate frame, where the first indication position can indicate that the first time slot frame in the first intermediate frame corresponds to The destination chip address; the destination chip is the destination chip corresponding to the service information.

In the above solution, when N first time slot frames are mapped in the first intermediate frame, the N The first first slot frame in the first slot frame, the first slot position corresponding to each of the second first slot frame to the Nth first slot frame, and the first intermediate frame Corresponding; the destination address of the first first time slot frame, the second first time slot frame, and the Nth first time slot frame of the N first time slot frames are the same; N is a positive integer greater than or equal to 2.

In the above solution, when the received service information is K, the K is a positive integer greater than or equal to 2; correspondingly,

The first receiving unit is further configured to receive K service information;

The first mapping unit is further configured to map or demap the data corresponding to the K service information to the first slot frame, the second slot frame, the ith slot frame to the Kth slot frame respectively; Said i is a positive integer greater than or equal to 1 and less than or equal to K;

The second mapping unit is further configured to map the ith slot frame to an ith intermediate frame based on an ith slot position of the ith slot frame; the ith slot position can indicate Corresponding relationship between the i-th slot frame and the i-th intermediate frame;

The first sending unit is further configured to: send the i th intermediate frame based on an ith indication position of the i th intermediate frame; the i th indication position can indicate an i th slot in the i th intermediate frame The i-th destination chip address corresponding to the frame; the i-th destination end chip is a destination end chip corresponding to the i-th service information of the K service information.

In the above solution, the first sending unit is further configured to replace the header information in the i-th intermediate frame with the first frame header information; the first frame header information is a first intermediate frame, a second intermediate Uniform frame header information in the frame, the ith intermediate frame to the Kth intermediate frame;

It is further configured to transmit the frame header information as the ith intermediate frame of the first frame header information.

a second receiving unit, configured to receive the first intermediate frame;

a first demapping unit configured to demap the first intermediate frame to a first slot frame;

a second demapping unit configured to be based on a first slot position of the first slot frame The first time slot frame is mapped or demapped to the service information; the first time slot position can indicate a correspondence between the first time slot frame and the service information;

The second sending unit is configured to send the service information.

The cross scheduling method and the device and the storage medium provided by the embodiments of the present invention are capable of mapping or demapping data corresponding to the received service information to a first time slot frame; and based on the first frame of the first time slot frame a slot position, mapping the first slot frame to a first intermediate frame; and further transmitting the first intermediate frame to a destination corresponding to the service information based on the first indication position of the first intermediate frame The end chip, in this way, achieves the purpose of cross scheduling.

In addition, the embodiment of the present invention can achieve the purpose of cross-scheduling without using a cross chip. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce power consumption.

DRAWINGS

1 is a schematic flowchart 1 of an implementation flow of a cross scheduling method according to an embodiment of the present invention;

2 is a schematic structural diagram 1 of a cross-scheduling device according to an embodiment of the present invention;

3 is a schematic flowchart 2 of an implementation process of a cross-scheduling method according to an embodiment of the present invention;

4 is a schematic structural diagram 2 of a cross-scheduling device according to an embodiment of the present invention;

FIG. 5 is a schematic flowchart 1 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention;

6 is a second schematic flowchart of a specific implementation of a cross-scheduling method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of mapping relationship between a slot frame and an intermediate frame in a source-end Framer chip according to an embodiment of the present invention.

detailed description

The embodiments of the present invention are described in detail with reference to the accompanying drawings.

Embodiment 1

1 is a schematic flowchart 1 of an implementation process of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a source chip, and the method includes:

Step 101: Receive service information.

In this embodiment, the source chip can use a Framer chip, that is, a source framer chip; further, the source framer chip can receive various types of service information on its client side, for example, OTN service information, Ethernet Network business information, etc.

Step 102: Map or demap data corresponding to the service information to the first slot frame.

In this embodiment, after the source-side Framer chip receives various types of service information on its client side, the source-side Framer chip maps or demaps the data corresponding to the service information to the optical channel data unit ( In the ODUK), the data corresponding to the service information mapped or demapping to the ODUK is further mapped or demapped into the ODUK slot frame according to the requirements of the slot frame, that is, in the first slot frame described in this embodiment.

Here, because the service type of the service information is different, the service rate corresponding to the service information is different. Therefore, when the data corresponding to the service information is mapped or demapped into the ODUK slot frame, that is, in the first slot frame, A different number of padding regions are set according to the structure of the ODUK slot frame.

Step 103: Map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position can indicate the first slot frame and Corresponding relationship of the first intermediate frame;

In this embodiment, the source-side Framer chip performs cross-scheduling on the transmitting side of the backplane to the ODUK slot frame, that is, the first slot frame by slot position, that is, the source-side Framer chip is on its back. The transmitting side of the board maps the first slot frame to the first intermediate frame according to the first slot position corresponding to the first slot frame; and the first slot position and the first intermediate Corresponding to the frame, and since the first intermediate frame corresponds to the destination chip address corresponding to the service information, the first time slot frame can be sent to the first time slot by using the first intermediate frame. frame The corresponding destination chip is sent to the destination chip corresponding to the service information.

In this embodiment, the structure of the first intermediate frame is similar to the OTN frame structure class, and is a container for carrying ODUK time slot frames; therefore, the source framer chip can divide different ODUK time slot frames. The time slots are mixed into the intermediate frame structure.

In this embodiment, the source-side Framer chip can receive N service information of different service types at the same time or in sequence, and the source-side Framer chip can map or demap the data corresponding to the N service information to N In the first slot frame, when the first slot position corresponding to each first slot frame in the N first slot frames is corresponding to the first intermediate frame, the N first The slot frames are all mapped into the first intermediate frame;

That is, the first intermediate frame can include N first time slot frames, and the first time slot position corresponding to each first time slot frame of the N first time slot frames points to the a first intermediate frame, that is, a first time slot position corresponding to each of the N first time slot frames corresponds to the first intermediate frame, and therefore, the source framer The chip maps the N first slot frames to the first intermediate frame.

In addition, in this embodiment, the source-side Framer chip can also receive K service information of different service types, that is, the first service information, the second service information, and the i-th service information to the K-th service information. At this time, the source-side Framer chip respectively maps or demaps the data corresponding to the K service information into the first slot frame, the second slot frame, the i-slot frame to the K-slot frame. Wherein, the K is a positive integer greater than or equal to 2; and the i is a positive integer greater than or equal to 1 and less than or equal to K;

The corresponding ith slot position corresponds to the ith slot position, and the ith slot position can indicate the correspondence between the ith slot frame and the intermediate frame; The first time slot position corresponds to the first intermediate frame, the second time slot position corresponds to the second intermediate frame, the ith time slot position corresponds to the ith intermediate frame, and the Kth time slot position corresponds to the Kth intermediate frame, so The source-side Framer chip is further capable of using the first slot frame, the second slot frame, and the ith time based on the first slot position, the second slot position, the i-th slot position to the K-th slot position The slot frame to the Kth slot frame are correspondingly mapped into the first intermediate frame, the second intermediate frame, the ith intermediate frame to the Kth intermediate frame.

Step 104: Send the first intermediate frame according to the first indication position of the first intermediate frame, where the first indication position can indicate a destination end chip corresponding to the first time slot frame in the first intermediate frame. The destination chip is the destination chip corresponding to the service information.

In this embodiment, the source framer chip, on the transmitting side of the backplane, can send the first intermediate frame to and the first indicated location based on the first indicated position of the first intermediate frame. In the corresponding destination chip, the source framer chip transmits the first intermediate frame carrying the first slot frame to the first slot position and the first indication position. In the destination chip corresponding to the first slot frame, the purpose of cross scheduling is implemented.

In this embodiment, the source framer chip is unified on the transmitting side of the backplane, and the intermediate frame structure to be sent is unified into the intermediate frame of the first frame header information after the frame header information is aligned and transmitted; The backplane SerDes interface is interconnected with the destination chip corresponding to the intermediate frame to be sent, that is, the source framer chip can be associated with the intermediate frame to be sent through the backplane SerDes interface of the source framer chip. The destination end chip is interconnected to form an MESH structure. Therefore, the source framer chip can send the intermediate frame to the destination end chip, thereby laying a foundation for implementing cross scheduling.

Mapping or demapping the data corresponding to the K service information to the first time slot frame and the second time a slot frame, an ith slot frame to a Kth slot frame; the i is a positive integer greater than or equal to 1 and less than or equal to K;

Specifically, when the received service information is K, the K is a positive integer greater than or equal to 2; the method further includes:

Mapping or demapping the first service information, the second service information, and the data corresponding to the Kth service information to the first time slot frame, the second time slot frame, and the ith time a slot frame to a Kth slot frame; the i is a positive integer greater than or equal to 1 and less than K;

Based on a first slot position of the first slot frame, a second slot position of the second slot frame, an i th slot position of the i th slot frame, and a Kth slot position of the Kth slot frame Mapping the first slot frame, the second slot frame, the i th slot frame to the Kth slot frame to the first intermediate frame, the second intermediate frame, the i th intermediate frame to the Kth intermediate frame, The first time slot position can indicate a correspondence between the first time slot frame and the first intermediate frame; the second time slot position can indicate the second time slot frame and the second intermediate position Corresponding relationship of the frame; the ith slot position can indicate a correspondence between the ith slot frame and the ith intermediate frame; and the Kth slot position can indicate the Kth slot frame and location Corresponding relationship of the Kth intermediate frame;

Transmitting the first intermediate frame based on the first indication position of the first intermediate frame, the second indication position of the second intermediate frame, the ith indication position of the i-th intermediate frame, and the Kth indication position of the Kth intermediate frame a second intermediate frame, an i-th intermediate frame to a K-th intermediate frame; the first indication position can And indicating a first destination chip address corresponding to the first slot frame in the first intermediate frame, where the second indication location is capable of indicating a second destination end corresponding to the second slot frame in the second intermediate frame a chip address; the ith indication position is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame; and the Kth indication location is capable of indicating a Kth in the Kth intermediate frame a K-th destination chip address corresponding to the time slot frame; the first destination end chip is a destination end chip corresponding to the first service information; and the second destination end chip is a destination corresponding to the second service information The end chip; the ith destination chip is the destination chip corresponding to the ith service information; and the Kth destination chip is the destination chip corresponding to the Kth service information.

In the foregoing solution, the sending the i-th intermediate frame includes:

In the above solution, the sending the first intermediate frame, the second intermediate frame, the i-th intermediate frame to the K-th intermediate frame, including:

Unifying the frame header information in the first intermediate frame, the second intermediate frame, the i-th intermediate frame, and the K-th intermediate frame into the first frame header information;

Transmitting the first intermediate frame, the second intermediate frame, the i-th intermediate frame to the K-th intermediate frame after the frame header information is unified.

In this embodiment, the frame header information of all the intermediate frames sent by the source-end Framer chip is a unified frame header information, that is, the first frame header information; further, the source-end Framer chip will send the intermediate frame to be sent. After the frame header information is unified into the first frame header information, the frame header information is sequentially sent to be the intermediate frame of the first frame header information;

Here, when the frame header information of the intermediate frame to be transmitted by the source framer chip is the first frame header information, the frame header information is directly sent as the intermediate frame of the first frame header information;

When the frame header information of the intermediate frame to be sent by the source framer chip is not the first frame header information, the frame header information of the intermediate frame to be sent is replaced with the first frame header information, and then, the frame header is used. The information is transmitted for the intermediate frame of the first frame header information.

The embodiment of the invention further provides a first computer readable storage medium, the storage medium comprising a set of instructions, the instructions being used in the cross scheduling method according to the first embodiment.

To achieve the above method, an embodiment of the present invention further provides a cross scheduling device. As shown in FIG. 2, the device includes:

The first receiving unit 21 is configured to receive service information.

The first mapping unit 22 is configured to map or demap data corresponding to the service information to the first slot frame;

The second mapping unit 23 is configured to map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position can indicate the first a correspondence between a slot frame and the first intermediate frame;

The first sending unit 24 is configured to send the first intermediate frame according to the first indicated position of the first intermediate frame, where the first indicated position can indicate the first time slot frame in the first intermediate frame Corresponding destination chip address; the destination chip is a destination chip corresponding to the service information.

The first receiving unit 21 is further configured to receive K service information.

The first mapping unit 22 is further configured to map or demap data corresponding to the K service information to the first slot frame, the second slot frame, the i th slot frame to the Kth slot frame, respectively; The i is a positive integer greater than or equal to 1 and less than or equal to K;

The second mapping unit 23 is further configured to map the ith slot frame to an ith intermediate frame based on an ith slot position of the ith slot frame; the ith slot position can indicate Corresponding relationship between the ith slot frame and the ith intermediate frame;

The first transmitting unit 24 is further configured to: send the ith intermediate frame based on an ith indication position of the ith intermediate frame; and the ith indication position can indicate an ith time in the ith intermediate frame The ith destination chip address corresponding to the slot frame; the ith destination chip is the destination chip corresponding to the ith service information of the K service information.

In the above solution, the first sending unit 24 is further configured to replace the header information in the i-th intermediate frame with the first frame header information; the first frame header information is a first intermediate frame, and the second Uniform frame header information in the intermediate frame, the ith intermediate frame to the Kth intermediate frame;

In this embodiment, the first receiving unit 21, the first mapping unit 22, the second mapping unit 23, and the first sending unit 24 may all run in a source chip, and may be a central processor located in the source chip ( CPU), or microprocessor (MPU), or digital signal processor (DSP), or programmable gate array (FPGA) implementation.

The cross-scheduling method and the device and the storage medium according to the embodiments of the present invention can realize the low-cost ODUK small-capacity cross-distribution purpose of the Framer chip interconnection through the ODUK cross-scheduling method of the MESH structure. Moreover, the embodiment of the present invention The cross-scheduling method and device thereof are different from the cluster cross-scheduling method and system. That is to say, the embodiment of the present invention does not require a special cross chip, and only needs to interconnect the source framer chip and the destination end framer chip. The cross-scheduling process is implemented. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce energy consumption.

In addition, since the embodiment of the present invention has low cost and low power consumption, it can also be applied to edge connection. Into the process of cross-scheduling of the sink node.

Embodiment 2

3 is a schematic flowchart 2 of an implementation process of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a destination end chip; as shown in FIG. 3, the method includes:

Step 301: Receive a first intermediate frame.

In this embodiment, the destination end chip may be a Framer chip, that is, a destination end Framer chip; further, the destination end Framer chip is connected to the first intermediate frame on its backplane receiving side.

Step 302: Demap the first intermediate frame to a first slot frame.

In this embodiment, after the destination end Framer chip is connected to the first intermediate frame on the receiving side of the backplane, the destination end Framer chip is in accordance with the source end Framer chip corresponding to the first intermediate frame. The first intermediate frame performs a distinguishing process, and after the distinguishing process, the first intermediate frame is demapped to ODUK, and further demapped to a first time slot frame, that is, a first ODUK time slot frame.

In addition, in this embodiment, when the destination-end Framer chip receives a plurality of intermediate frames from a plurality of source-side Framer chips on its backplane side, specifically,

After the destination end Framer chip receives the first intermediate frame, the second intermediate frame, the jth intermediate frame and the Mth intermediate frame on the backplane side thereof, the destination end Framer chip follows the first intermediate frame and the second frame. The source framer chip corresponding to the intermediate frame, the jth intermediate frame, and the Mth intermediate frame respectively distinguishes the first intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame, and the frame header information alignment processing, After the alignment and the frame header information are aligned, the first intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame, which are aligned with the header information, are respectively mapped to the first time slot frame and the second frame, respectively. a slot frame, a jth slot frame to an Mth slot frame; the j is a positive integer greater than or equal to 1 and less than or equal to M; and the M is a positive integer greater than or equal to 2.

Step 303: Map or demap the first slot frame to service information based on a first slot position of the first slot frame; the first slot position can indicate the first slot frame And Corresponding relationship of business information;

In this embodiment, when the destination end Framer chip receives M intermediate frames from multiple source Framer chips on its backplane side, and the destination End Framer chip will be the first of the M intermediate frames. The intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame are respectively mapped to the first slot frame, the second slot frame, the jth slot frame to the Mth slot frame,

The destination end Framer chip is based on a first slot position of the first slot frame, a second slot position of the second slot frame, and a jth slot position of the jth slot frame to Mapping or de-mapping the first slot frame, the second slot frame, the j-th slot frame to the M-th slot frame to the first service information, and the M-th slot position of the M-th slot frame Second, business information, jth business information to Mth business information;

The first slot position can indicate a correspondence between the first slot frame and the first service information; the second slot position can indicate the second slot frame and the second slot Corresponding relationship of the service information; the jth slot position can indicate a correspondence between the jth slot frame and the jth service information; the Mth slot position can indicate the Mth slot frame and Corresponding relationship of the Mth service information; in this manner, the destination end Framer chip demaps the received M intermediate frames from the multiple source Framer chips to the M service information.

Step 304: Send the service information.

In this embodiment, the destination end Framer chip sends the service information on its client sending side. The service information may be OTN service information, or Ethernet service information, and the like.

In this embodiment, when the destination end Framer chip receives M intermediate frames from multiple source Framer chips on its backplane side, and the destination End Framer chip demaps the M intermediate frames to M. After the service information, the destination end Framer chip sends the M service information.

In this embodiment, the destination end Framer chip schedules, on the backplane receiving side, the demapped ODUK slot frame, that is, the first slot frame by slot position, specifically, when the destination The end Framer chip demaps the M intermediate frames from the multiple source Framer chips to the M time slot frames on the receiving side of the backplane, that is, the first time slot frame, the second time slot frame, and the jth time slot. After the frame to the Mth time slot frame, the destination end Framer chip can be based on the first time slot position of the first time slot frame and the second time slot position of the second time slot frame on its backplane receiving side. And scheduling, by the jth slot position of the jth slot frame, to the Mth slot position of the Mth slot frame; further, the slot position and the destination end The client side of the framer chip corresponds to the transmitting side, that is, the time slot position can indicate the corresponding relationship between the time slot frame and the service information, so that the destination framer chip can send the time slot frame based on the time slot position. To the client side corresponding to the slot position;

Specifically, the destination end Framer chip can be based on a first slot position of the first slot frame, a second slot position of the second slot frame, and a jth time of the jth slot frame. And transmitting, by the slot location to the Mth slot position of the Mth slot frame, the first service information, the second service information, and the jth service information to the Mth service information.

The embodiment of the present invention further provides a second computer readable storage medium, where the storage medium includes a set of instructions, and the instructions are used in the cross scheduling method described in Embodiment 2.

In order to implement the foregoing method, the embodiment of the present invention further provides a cross scheduling device. As shown in FIG. 4, the device includes:

The second receiving unit 41 is configured to receive the first intermediate frame;

a first demapping unit 42 configured to demap the first intermediate frame to a first slot frame;

The second demapping unit 43 is configured to map or demap the first slot frame to service information based on a first slot position of the first slot frame; the first slot position can indicate Corresponding relationship between the first slot frame and the service information;

The second sending unit 44 is configured to send the service information.

In this embodiment, the second receiving unit 41, the first demapping unit 42, the second demapping unit 43, and the second sending unit 44 may all run in the destination chip, and may be located at the destination. A central processing unit (CPU), or a microprocessor (MPU), or a digital signal processor (DSP), or a programmable gate array (FPGA) in a terminal chip.

Embodiment 3

FIG. 5 is a schematic flowchart 1 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a source-side Framer chip; as shown in FIG. 5, the method includes:

Step 501: The source framer chip receives K service information on its client side, and maps or demaps the data corresponding to the K service information to K ODUK time slot frames, that is, the first time slot frame and the second frame. a slot frame, an ith slot frame to a Kth slot frame; the K is a positive integer greater than or equal to 2; and the i is a positive integer greater than or equal to 1 and less than or equal to K;

In this embodiment, the service information received by the source-side Framer chip on its client side is OTN service information and/or Ethernet service information;

When the source-side Framer chip receives the OTN service information on its client side, the source-side Framer chip demaps the data corresponding to the OTN service information to the ODUK time slot frame;

When the source-side Framer chip receives the Ethernet service information on its client side, the source-side Framer chip passes the bit synchronization mapping (BMP), the asynchronous mapping (AMP), or according to the rate level of the Ethernet service information. a mechanism such as a universal mapping (GMP), mapping data corresponding to the Ethernet service information to a corresponding ODUK time slot frame;

In this embodiment, for the Ethernet service information with a constant rate, the data corresponding to the Ethernet service information is directly mapped to the ODUK slot frame corresponding to the rate by using the BMP method.

For the Ethernet service information whose rate does not correspond to the rate of the ODUK, that is, the service whose rate of the Ethernet service information has a certain margin relative to the rate of the ODUK, the data corresponding to the Ethernet service information is usually adopted by the AMP method. Mapping into an ODUK slot frame; when mapping, selectively padding data bytes or adjusting bytes in the NJO field and the PJO field of the ODUk slot frame;

When mapping low-rate Ethernet service information to a high-rate ODUK slot frame, a GMP method is generally adopted, and the GMP method adopts a sigma/delta rule, and thus, the mapping party and the mapped party are adopted by the sigma/delta rule. Rate matching, so that the service signal corresponding to the Ethernet information is evenly distributed in the payload of the ODUK slot frame.

In this embodiment, after the source side Framer chip receives the service information on its client side, it is mapped or demapped into the ODUK slot frame; here, a high-speed ODUK slot frame structure may occupy multiple ODUKs. a time slot; the data corresponding to each ODUK time slot can be converted to a unified time slot by a bit width, for example, converted into an 8-bit time slot; then, the buses of the plurality of ODUK time slots are aggregated into an ODUK space-division bus, Each bit of the ODUK space-division bus is one unit, that is, an ODUK time slot; here, the service information with higher rate can occupy multiple 8-bit units.

Step 502: The source framer chip is on the transmitting side of the backplane, based on the first slot position of the first slot frame, the second slot position of the second slot frame, and the i-th slot frame. Mapping the first slot frame, the second slot frame, the ith slot frame to the Kth slot frame to the first intermediate position from the i slot position to the Kth slot position of the Kth slot frame a frame, a second intermediate frame, an i-th intermediate frame to a K-th intermediate frame;

The first slot position can indicate a correspondence between the first slot frame and the first intermediate frame; the second slot position can indicate the second slot frame and the second slot Corresponding relationship of the intermediate frame; the ith slot position can indicate a correspondence between the ith slot frame and the ith intermediate frame; and the Kth slot position can indicate the Kth slot frame and Corresponding relationship of the Kth intermediate frame; as described in FIG. 7, the first time slot frame, based on the first time slot position, the second time slot position, the i th slot position to the Kth slot position, The second slot frame, the i th slot frame to the Kth slot frame are correspondingly mapped to the first intermediate frame, the second intermediate frame, the i th intermediate frame to the Kth intermediate frame.

In this embodiment, the source-side Framer chip maps the ODUK slot frame to the intermediate frame structure according to the location on the transmitting side of the backplane; that is, the source-side Framer chip is on the transmitting side of the backplane, The first time slot position of the first time slot frame, the second time slot position of the second time slot frame, the ith time slot position of the ith time slot frame, and the Kth time slot position of the Kth time slot frame, The first slot frame, the second slot frame, the i th slot frame to the Kth slot frame are correspondingly mapped to the first intermediate frame, the second intermediate frame, the i th intermediate frame to the Kth intermediate frame; Transmitting, according to the ith indication position of the i th intermediate frame, the i th intermediate frame; and the source end framer chip capable of simultaneously selecting the K intermediate frames according to the K intermediate frames The indicated location is sent out. Therefore, the transmitting side of the backplane of the source Framer chip can perform cross scheduling on the OTUK slot frame by slot position.

Here, the intermediate frame structure is similar to the OTU frame structure defined in the G.709 protocol, and is a container for carrying ODUK slot frames. Moreover, the present embodiment can use the GMP mechanism to mix different time slot frames into time slots into an intermediate frame structure.

Step 503: Send the first indication position based on the first indication position of the first intermediate frame, the second indication position of the second intermediate frame, the ith indication position of the i-th intermediate frame, and the Kth indication position of the Kth intermediate frame. An intermediate frame, a second intermediate frame, an i-th intermediate frame to a K-th intermediate frame;

The first indication location can indicate a first destination chip address corresponding to the first slot frame in the first intermediate frame; the second indication location can indicate a second time in the second intermediate frame a second destination chip address corresponding to the slot frame; the ith indication position can indicate an ith destination chip address corresponding to the ith slot frame in the i th intermediate frame; the Kth indication position can indicate a Kth destination chip address corresponding to the Kth time slot frame in the Kth intermediate frame; the first destination end chip is a destination end chip corresponding to the first service information; and the second destination end chip is The destination chip corresponding to the second service information; the ith destination chip is a destination chip corresponding to the ith service information; and the Kth destination chip is a destination corresponding to the Kth service information chip.

In this embodiment, the source framer chip unifies the frame header information in the first intermediate frame, the second intermediate frame, the i-th intermediate frame, and the K-th intermediate frame into the first frame header information on the transmitting side of the backplane, And aligning the header information to send the first intermediate frame, the second intermediate frame, the i-th intermediate frame to the K-th intermediate frame;

In the embodiment of the present invention, unified frame header information is used in the structure of each intermediate frame, and the frame header information is aligned and sent; since the backplane SerDes of the source framer chip is interconnected with the Framer chip of the destination end, therefore, Embodiments are capable of transmitting each intermediate frame to a destination-side Framer chip.

Here, under the MESH networking structure, the number of Framer chips is limited by the number of SerDes links on the backplane side; for example, it is necessary to ensure that one Framer chip has a SerDes link to each of the other Framer chips; and the intersection between the two Framer chips The bandwidth is determined by the number and rate of SerDes between them.

FIG. 6 is a schematic flowchart 2 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a target-end Framer chip; as shown in FIG. 6, the method includes:

Step 601: The destination side Framer chip receives M intermediate frames from multiple source Framer chips on its receiving side of the backplane;

In this embodiment, the destination end Framer chip distinguishes the M intermediate frames according to the source framer chip, and aligns the frame header information in each intermediate frame structure from the same source Framer chip;

Step 602: The destination end Framer chip demaps the M intermediate frames on its receiving side of the backplane, and demaps to M ODUK slot frames, that is, the first slot frame and the second slot frame. , the jth slot frame to the Mth slot frame;

In this embodiment, the destination end Framer chip converts the data corresponding to each ODUK time slot of the demlocated M ODUK time slot frames to a uniform size, for example, into 8 bits, on the receiving side of the backplane. Subsequently, the buses of multiple ODUK time slots are aggregated into ODUK space The sub-bus divides the slot position in units of 8 bits, so that the slot position can correspond to the slot information and the service information, and further corresponds to the client transmitting side of the destination framer.

Step 603: The destination end Framer chip maps or demaps the first slot frame, the second slot frame, the jth slot frame to the Mth slot frame to various M service information on its client transmitting side. And sending the M service information from the client sending side.

Here, the service information includes OTN service information, or Ethernet service information, and the like.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on the computer or other programmable device to produce the computer The implemented processing, such as instructions executed on a computer or other programmable device, provides steps for implementing the functions specified in one or more blocks of the flowchart or in a block or blocks of the flowchart.

The above is only an embodiment of the embodiments of the present invention, and it should be noted that those skilled in the art can make some improvements and refinements without departing from the principles of the embodiments of the present invention. Retouching should also be considered as the scope of protection of the embodiments of the present invention.

Industrial applicability

The embodiment of the present invention can map or demap the data corresponding to the received service information to the first slot frame; and map the first slot frame based on the first slot position of the first slot frame. And the first intermediate frame is sent to the destination end chip corresponding to the service information, so that the purpose of cross scheduling is achieved. In addition, the embodiment of the present invention can achieve the purpose of cross-scheduling without using a cross chip. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce power consumption.

Claims

A cross scheduling method is applied to a source chip; the method includes:

Receiving business information;

Mapping or demapping data corresponding to the service information to the first slot frame;

Mapping the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position capable of indicating the first slot frame and the first slot a corresponding relationship of intermediate frames;

Transmitting the first intermediate frame according to the first indication position of the first intermediate frame; the first indication position is capable of indicating a destination chip address corresponding to the first time slot frame in the first intermediate frame; The destination end chip is the destination end chip corresponding to the service information.
The method according to claim 1, wherein when N first slot frames are mapped in the first intermediate frame, a first one of the N first slot frames, The first slot position corresponding to each of the second first slot frame to the Nth first slot frame is corresponding to the first intermediate frame; the first one of the N first slot frames The destination chip address corresponding to the one slot frame, the second first slot frame to the Nth first slot frame is the same; wherein the N is a positive integer greater than or equal to 2.
The method according to claim 1, wherein when the received service information is K, the K is a positive integer greater than or equal to 2; the method further includes:

Mapping or de-mapping data corresponding to the K service information to the first slot frame, the second slot frame, the i-th slot frame to the K-th slot frame; wherein the i is greater than or equal to 1 and less than or equal to K Positive integer

Mapping the i th slot frame to an i th intermediate frame based on an i th slot position of the i th slot frame; the i th slot position capable of indicating the i th slot frame and the first i corresponding to the intermediate frame;

Transmitting the ith intermediate frame based on an ith indication position of the ith intermediate frame; the ith indication location is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame The ith target chip is a destination chip corresponding to the ith service information of the K service information.
The method of claim 3, wherein the transmitting the ith intermediate frame comprises:

Substituting the header information in the ith intermediate frame with the first header information; the first header information is unified in the first intermediate frame, the second intermediate frame, and the ith intermediate frame to the Kth intermediate frame Frame header information;

The transmission frame header information is the ith intermediate frame of the first frame header information.
A cross scheduling method, the method is applied to a destination chip; the method includes:

Receiving a first intermediate frame;

De-mapping the first intermediate frame to a first slot frame;

Mapping or de-mapping the first slot frame to traffic information based on a first slot position of the first slot frame; the first slot position capable of indicating the first slot frame and the Correspondence of business information;

Send the service information.
A cross-scheduling device, the device comprising:

a first receiving unit, configured to receive service information;

a first mapping unit, configured to map or demap data corresponding to the service information to the first slot frame;

a second mapping unit, configured to map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position capable of indicating the first Corresponding relationship between the slot frame and the first intermediate frame;

a first sending unit, configured to send a location based on the first indicated location of the first intermediate frame The first intermediate frame is configured to indicate a destination chip address corresponding to the first time slot frame in the first intermediate frame; the destination end chip is a destination end chip corresponding to the service information.
The apparatus according to claim 6, wherein when the first first slot frames are mapped in the first intermediate frame, the first one of the N first slot frames, The first slot position corresponding to each of the second first slot frame to the Nth first slot frame is corresponding to the first intermediate frame; the first one of the N first slot frames The destination chip address corresponding to the one slot frame, the second first slot frame to the Nth first slot frame is the same; wherein the N is a positive integer greater than or equal to 2.
The apparatus according to claim 1, wherein when the received service information is K, the K is a positive integer greater than or equal to 2; correspondingly,

The first receiving unit is further configured to receive K service information;

The first mapping unit is further configured to map or demap the data corresponding to the K service information to the first slot frame, the second slot frame, the ith slot frame to the Kth slot frame respectively; Said i is a positive integer greater than or equal to 1 and less than or equal to K;

The second mapping unit is further configured to map the ith slot frame to an ith intermediate frame based on an ith slot position of the ith slot frame; the ith slot position can indicate Corresponding relationship between the i-th slot frame and the i-th intermediate frame;

The first sending unit is further configured to: send the i th intermediate frame based on an ith indication position of the i th intermediate frame; the i th indication position can indicate an i th slot in the i th intermediate frame The i-th destination chip address corresponding to the frame; the i-th destination end chip is a destination end chip corresponding to the i-th service information of the K service information.
The apparatus according to claim 8, wherein the first transmitting unit is further configured to replace the header information in the ith intermediate frame with the first header information; the first header information is Uniform frame header information in an intermediate frame, a second intermediate frame, an i-th intermediate frame to a K-th intermediate frame;

It is further configured to transmit the frame header information as the ith intermediate frame of the first frame header information.
A cross-scheduling device, the device comprising:

a second receiving unit, configured to receive the first intermediate frame;

a first demapping unit configured to demap the first intermediate frame to a first slot frame;

a second demapping unit configured to map or demap the first slot frame to traffic information based on a first slot position of the first slot frame; the first slot position capable of indicating the Corresponding relationship between the first slot frame and the service information;

The second sending unit is configured to send the service information.
A first computer readable storage medium comprising a set of instructions for performing the cross-scheduling method of any one of claims 1 to 4.
A second computer readable storage medium comprising a set of instructions for performing the cross-scheduling method of claim 5.