WO2010131312A1 - Semiconductor device and method of producing same - Google Patents

Semiconductor device and method of producing same Download PDF

Info

Publication number
WO2010131312A1
WO2010131312A1 PCT/JP2009/007030 JP2009007030W WO2010131312A1 WO 2010131312 A1 WO2010131312 A1 WO 2010131312A1 JP 2009007030 W JP2009007030 W JP 2009007030W WO 2010131312 A1 WO2010131312 A1 WO 2010131312A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
semiconductor
semiconductor region
gate electrode
semiconductor device
Prior art date
Application number
PCT/JP2009/007030
Other languages
French (fr)
Japanese (ja)
Inventor
竹岡慎治
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2010131312A1 publication Critical patent/WO2010131312A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present disclosure relates to a P-type field effect transistor (P-type FET) having a channel formed of a SiGe layer, and capable of reducing a substrate leakage current, and a method for manufacturing the same.
  • P-type FET P-type field effect transistor
  • a silicon oxynitride film which is a silicon oxide film or a nitride film thereof, has been used for the gate insulating film.
  • EOT Equivalent Oxide Thickness
  • transistors having a high dielectric constant gate insulating film / metal gate electrode structure have been made.
  • One of the important points in realizing a high dielectric constant gate insulating film / metal gate electrode structure is the threshold voltage control of the transistor.
  • the work function of the silicon electrode is adjusted by impurity ion implantation, and a threshold voltage suitable for each of the N-type FET and the P-type FET has been realized.
  • an N-type impurity such as arsenic or phosphorus is implanted into the silicon electrode to reduce the work function.
  • P or the like such as boron is used for the silicon electrode. Work functions have been increased by implanting type impurities.
  • the channel region of the transistor is replaced with a Si (germanium) containing Si (germanium) instead of a conventional silicon (silicon) layer. It has been proposed to form a layer made of 1-x Ge x (0 ⁇ x ⁇ 1) (Non-patent Document 1). In this specification, Si 1-x Ge x (0 ⁇ x ⁇ 1) may be simply expressed as SiGe.
  • a range of about 50 nm is formed from SiGe with SiGe.
  • the energy band gap of Ge is as small as 0.66 eV, compared to the energy band gap of Si being 1.12 eV.
  • the energy band gap of SiGe which is a mixed crystal of Si and Ge, continuously changes between 0.66 and 1.12 eV depending on the Ge composition ratio x.
  • Si and Ge have almost the same electron affinity. For this reason, the fluctuation of the energy band gap of SiGe accompanying the change of the Ge composition ratio x is mainly caused by the fluctuation of the energy of the valence band. That is, the energy of the valence band of SiGe is higher than the energy of the valence band of Si.
  • the threshold voltage can be reduced by forming the SiGe channel instead of the Si channel.
  • Ge is contained in an amount of more than 10% (0.1 ⁇ x ⁇ 1).
  • Non-Patent Document 1 reports a reduction in threshold voltage of 250 to 300 mV.
  • the diffusion layer (source / drain region, extension region, etc.) of the FET is also formed of SiGe.
  • the substrate leakage current is a leakage current generated when a reverse bias is applied to the PN junction formed by the diffusion layer region and the well region including the channel portion.
  • the size depends on the size of the energy band gap at the PN junction, and increases as the energy band gap decreases.
  • the degree of increase in the substrate leakage current compared with the case of the Si channel depends on the size of the energy band gap at the PN junction, and further depends on the composition ratio x of Ge. It will be.
  • the inventor of the present application reduces the threshold voltage and increases the substrate leakage by increasing the Si concentration (content ratio) in the PN junction portion formed by the diffusion layer region and the well region as compared with the channel portion. It was devised to suppress the increase in current.
  • a semiconductor device includes a first conductive type first semiconductor region containing Ge, a gate electrode formed on the first semiconductor region with a gate insulating film interposed therebetween, A second conductivity type diffusion region formed on both sides of the gate electrode in the semiconductor region; and a first conductivity type second semiconductor region formed between the first semiconductor region and the diffusion region;
  • the second semiconductor region contains a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region.
  • the Si concentration is higher in the PN junction portion than in the channel formation region while the threshold voltage is controlled (reduced) by forming a channel in the first semiconductor region containing Ge.
  • the Ge concentration is low
  • an increase in substrate leakage current can be suppressed.
  • the first semiconductor region is preferably N-type and the diffusion region is preferably P-type.
  • Reduction of the threshold voltage by using a channel containing Ge (SiGe channel) is particularly useful in a P-type FET. Therefore, when the first semiconductor region is N-type by including N-type impurities and the diffusion region is P-type by including P-type impurities, the effect of the semiconductor device of the present disclosure is remarkable. Is obtained.
  • the diffusion region preferably contains at least one of boron and indium as an impurity.
  • the first semiconductor region preferably contains at least one of arsenic and phosphorus as an impurity. Such an element can be used as an impurity contained in each region.
  • the diffusion region is preferably at least one of a source / drain region and an extension region.
  • Examples of locations where substrate leakage current occurs include the PN junctions at the bottom and sides of the source / drain regions and extension regions. Therefore, if the diffusion region is one or both of the source / drain region and the extension region, the substrate leakage current can be suppressed.
  • the second semiconductor region may be formed entirely between the first semiconductor region and the diffusion region.
  • the second semiconductor region may be formed in a part between the first semiconductor region and the diffusion region.
  • the Si concentration may be increased for the entire PN junction where the substrate leakage current is generated, or the Si concentration may be increased particularly for a portion where the substrate leakage current is large.
  • the substrate leakage current can be suppressed by disposing the second semiconductor region at an appropriate location in accordance with the characteristics of each semiconductor device.
  • Each of the second semiconductor region and the channel formation region is made of Si 1-x Ge x (0 ⁇ x ⁇ 1), and x in the second semiconductor region is 0.1 or more than x in the channel region. Small is preferable.
  • a method of manufacturing a semiconductor device includes a step (a) of forming a first semiconductor region of a first conductivity type containing Ge on a substrate, and a first semiconductor region.
  • a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region is a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region.
  • the semiconductor device of the present disclosure can be manufactured. That is, it is possible to manufacture a semiconductor device in which the substrate leakage current is suppressed due to the high Si concentration in the PN junction portion while reducing the threshold voltage by providing the channel formation region containing Ge. .
  • the diffusion region is preferably at least one of a source / drain region and an extension region.
  • the diffusion region is preferably formed by ion implantation of at least one of boron and indium.
  • a specific diffusion region may be as described above.
  • the second semiconductor region may be formed by Si ion implantation.
  • the Si concentration of the PN junction portion where the substrate leakage current is generated is controlled. Increasing the thickness can suppress the substrate leakage current.
  • FIG. 1 is a diagram schematically illustrating a cross-section of a main part of an exemplary semiconductor device according to the first embodiment.
  • FIGS. 2A to 2C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the first embodiment.
  • FIGS. 3A to 3C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the first embodiment, following FIG. 2C.
  • FIG. 4 is a diagram schematically illustrating a cross-section of a main part of an exemplary semiconductor device according to the second embodiment.
  • FIGS. 5A to 5C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the second embodiment.
  • 6 (a) to 6 (c) are diagrams showing respective steps of the exemplary semiconductor device manufacturing method according to the second embodiment, following FIG. 5 (c).
  • the semiconductor device 150 is formed using a semiconductor substrate 100 made of silicon and has a P-type FET structure.
  • a first semiconductor region 101 made of Si 1-x Ge x (0 ⁇ x ⁇ 1) is formed on the semiconductor substrate 100.
  • the first semiconductor region 101 has a film thickness of, for example, 90 nm, and is N-type by including N-type impurities (channel impurities for well formation and threshold voltage control) such as phosphorus and arsenic.
  • a gate electrode 122 is formed on the first semiconductor region 101 with a gate insulating film 121 interposed therebetween.
  • a sidewall spacer 106 made of a silicon oxide film is formed so as to cover both side surfaces of the gate electrode 122 and the gate insulating film 121.
  • the gate insulating film 121 has a structure in which the high dielectric constant insulating film 103 is stacked on the oxide film 102.
  • the gate electrode 122 has a structure in which a silicon film 105 such as polysilicon or amorphous silicon is stacked on a metal gate electrode made of a material containing metal, for example, a titanium nitride film 104.
  • Extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101.
  • the extension region 107 is P-type by including boron, which is a P-type impurity, and has a depth of about 15 nm.
  • a P-type source / drain region 109 (referred to as the source region and the drain region together) is formed with a junction depth of about 60 nm.
  • an N-type second semiconductor region 108 is formed between the extension region 107 and the first semiconductor region 101 so as to cover the extension region 107.
  • the depth of the second semiconductor region 108 is about 20 nm, and is formed outside the extension region 107 by about 5 nm.
  • a channel is formed in the portion of the first semiconductor region 101 below the gate electrode 122. Since the channel formation region contains Ge, the threshold voltage is reduced as compared with the case of the Si channel.
  • the threshold voltage is reduced if even a little Ge is included, but it is preferable that about 10% is included in order to obtain a substantial reduction effect.
  • Si may not be included but only Ge may be sufficient. That is, it is preferable to satisfy 0.1 ⁇ x ⁇ 1.
  • the Si concentration in the second semiconductor region 108 is higher than that in such a channel formation region.
  • the bottom and side PN junctions of the extension region 107 have a higher Si concentration (in other words, a lower Ge concentration) than the channel formation region because the second semiconductor region 108 is formed. It has become.
  • the substrate leakage current generated at the PN junction in the extension region 107 can be reduced by about one digit.
  • the present invention is not limited thereto.
  • the Si concentration in the PN junction portion (second semiconductor region 108) is higher than that in the channel formation region, the substrate leakage current is reduced. be able to.
  • the Si concentration of the second semiconductor region 108 is 25% higher than that of the channel formation region (Ge composition ratio x is 0.25 smaller) has been described, but the present invention is not limited to this.
  • the substrate leakage current is also reduced when the difference in Si concentration is smaller.
  • the second semiconductor region 108 has a Si concentration 10% or more higher than that of the channel formation region (x is a Ge composition smaller than 0.1 or more)
  • the substrate leakage current can be significantly suppressed. ,desirable.
  • the Si concentration in the channel formation region is 50%
  • the substrate leakage current is reduced to about 1/3 to 1/100 by setting the Si concentration in the second semiconductor region 108 to 60% to 100%.
  • the second semiconductor region 108 having a high Si concentration covers the entire extension region 107 (so as to be positioned between the extension region 107 and the first semiconductor region 101). Is formed.
  • this is not restrictive. What is important is to increase the Si concentration at the PN junction where a large amount of substrate leakage current occurs. For this reason, if a large amount of substrate leakage current occurs in the side surface portion (the channel forming region side portion) of the extension region 107, the side surface of the extension region 107 and the channel forming region (the first semiconductor region 101 below the gate electrode 122). ) Between the first semiconductor region 108 and the second semiconductor region 108. Similarly, if a large amount of substrate leakage current occurs at the bottom of the extension region 107, the second semiconductor region 108 is formed in this portion. Thereby, a substrate leakage current can be suppressed.
  • the present invention is not limited to this. If a part of the extension region 107 has a PN junction with the first semiconductor region 101 containing Ge, the substrate leakage current increases at the PN junction. In order to suppress this, the second semiconductor region 108 having a high Si concentration is provided. Therefore, even when the first semiconductor region 101 is thinner than the extension region 107, the effect of reducing the substrate leakage current can be obtained.
  • the oxide film 102 is formed on the first semiconductor region 101 containing Ge.
  • a Si layer can be formed on the first semiconductor region 101, and the oxide film 102 can be formed thereon. Thereby, it can be set as the P-type FET structure which has a SiGe channel with a Si cap.
  • the second semiconductor region 108 is provided to the outside of the extension region 107 by about 5 nm.
  • the present invention is not limited to this value, and the second semiconductor region 108 is provided so as to cover the extension region 107. That is the main point.
  • a first semiconductor region 101 is deposited to a thickness of 90 nm on a semiconductor substrate 100 made of silicon.
  • epitaxial growth may be performed on the semiconductor substrate 100 made of silicon using a CVD (chemical vapor deposition) method.
  • CVD chemical vapor deposition
  • the deposition temperature 500 ° C., the gas pressure and 20 Torr (2666 Pa) As the conditions for using a GeH 4 to SiH 4, Ge-based gas to Si-based gas, the deposition temperature 500 ° C., the gas pressure and 20 Torr (2666 Pa).
  • the first semiconductor region 101 is formed as an N-type layer by containing an N-type impurity such as phosphorus or arsenic.
  • a gate electrode 122 is formed on the first semiconductor region 101 with a gate insulating film 121 interposed therebetween.
  • SiGe on the surface of the first semiconductor region 101 is oxidized with ozone to form an oxide film 102 having a thickness of 1 nm.
  • a titanium nitride film 104 having a thickness of 10 nm is deposited on the high dielectric constant insulating film 103 as a metal gate, and a silicon film 105 having a thickness of 100 nm is further deposited thereon.
  • the structure of the electrode 122 is obtained.
  • Si is implanted which is a feature of the semiconductor device 150 manufacture.
  • Si ions are implanted using the gate electrode 122 as a mask under conditions of an acceleration energy of 15 keV and an implantation dose of 3 ⁇ 10 16 atoms / cm 2 .
  • the Si concentration about 20 nm deep from the surface increased by 25% to 75% (Ge concentration decreased to 25%).
  • the second semiconductor region 108 is formed.
  • Si also goes below the gate electrode 122.
  • the amount of overlap between the wraparound, that is, the lower part of the gate electrode 122 is smaller than the depth and is 10 nm or less.
  • extension injection is performed as shown in FIG. Specifically, boron is used as an impurity to be implanted, and ion implantation is performed using the gate electrode 122 as a mask under conditions of an acceleration energy of 0.3 keV and an implantation dose of 5 ⁇ 10 14 atoms / cm 2 .
  • P-type extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101.
  • the junction depth immediately after the implantation is very shallow at 10 nm or less, but boron is diffused by activation annealing described later, and the final junction depth is about 15 nm. Therefore, the extension region 107 is formed 5 nm shallower than the second semiconductor region 108 having a depth of about 20 nm.
  • sidewall spacers 106 that cover the side surfaces of the gate electrode 122 and the gate insulating film 121 are formed.
  • a silicon oxide film having a thickness of about 70 nm is deposited on the semiconductor substrate 100.
  • the entire surface is etched back by dry etching to form a sidewall spacer 106 made of a silicon oxide film having a width of about 70 nm on the side surface of the gate electrode 122.
  • source / drain regions 109 are formed.
  • boron is used as an impurity, and ion implantation is performed using the gate electrode 122 and the sidewall spacer 106 as a mask under conditions of an acceleration energy of 1.5 keV and an implantation dose of 4 ⁇ 10 15 atoms / cm 2 .
  • a P-type source / drain region 109 is formed on the outer side of the sidewall spacer 106 in the first semiconductor region 101.
  • the impurity in the extension region 107 and the source / drain region 109 is activated by performing spike annealing under the conditions of 1000 ° C. and 0 seconds (the temperature immediately decreases after reaching the target temperature). By this annealing, a source / drain region 109 having a junction depth of 60 nm is formed.
  • the semiconductor device 150 is manufactured.
  • the second semiconductor region 108 having a high Si concentration is formed so as to cover the region where the extension region 107 is formed. This reduces the substrate leakage current generated at the bottom and side PN junctions of the extension region 107.
  • the Si concentration in the PN junction (second semiconductor region 108) is 75% with respect to the Si concentration in the channel formation region (first semiconductor region 101) is 50%, which is a difference of 25%. Therefore, the substrate leakage current is reduced by about an order of magnitude.
  • the second semiconductor region 108 when the second semiconductor region 108 is formed first, an effect of improving short channel characteristics by pre-amorphization by Si implantation can be expected.
  • the second semiconductor region 108 having a high Si concentration is formed so as to cover the entire extension region 107.
  • substrate leak current If a large amount of substrate leakage current is generated in the side surface portion (channel forming region side) of the extension region 107, angle implantation is performed during Si implantation so that the amount of overlap of the second semiconductor region 108 below the gate electrode 122 is reduced. It can also be increased. Thereby, the Si concentration in the side surface portion of the extension region 107 can be increased. If a large amount of substrate leakage current is generated at the bottom of the extension region 107, a region having a high Si concentration may be formed particularly at the bottom of the extension region 107 by increasing the acceleration energy during Si implantation. .
  • an Si cap layer having a thickness of about 2 nm is deposited on the first semiconductor region 101 while the oxide film 102 shown in FIG. 2B is formed. Also good. Thereby, the quality of the oxide film 102 can be improved.
  • FIG. 4 is a diagram schematically showing a cross-section of the main part thereof.
  • parts common to the semiconductor device 150 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted, and differences are mainly described.
  • the semiconductor device 150 includes the N-type second semiconductor region 108 having a higher Si concentration than the channel formation region so as to cover the P-type extension region 107.
  • the N-type second semiconductor region 128 having a higher Si concentration than the channel formation region is formed so as to cover the P-type source / drain region 109. Has been.
  • the depth of the source / drain region 109 is about 60 nm, and the depth of the second semiconductor region 128 is about 70 nm.
  • the Si concentration is 50% in the channel formation region (the first semiconductor region 101 below the gate electrode 122).
  • the Si concentration of the second semiconductor region 128 is 75%.
  • the substrate at the PN junction at the bottom and sides of the source / drain region 109 (PN junction between the source / drain region 109 and the well and channel formation region). Leakage current can be suppressed.
  • the second semiconductor region 128 may cover the entire source / drain region 109, and the second semiconductor region may be provided only at a location where a large substrate leakage current occurs.
  • the source / drain region 109 may be provided only at the bottom or only at the side.
  • the Si concentration of the second semiconductor region 128 is increased by 25% compared to the channel formation region, but this is not essential. Even if the Si concentration is increased by 10% (Si is 50% in the channel formation region, while Si is 60% in the second semiconductor region 128), the substrate leakage current is suppressed to about one third. can do.
  • the thickness of the first semiconductor region 101 is 90 nm
  • the second semiconductor region 128 is formed from the source / drain region 109 to the outside of 10 nm, and the like. It will never be done.
  • FIGS. 5A to 5C and FIGS. 6A to 6C showing the steps.
  • the first semiconductor region 101 made of SiGe (Ge composition 50%) is formed on the semiconductor substrate 100 made of silicon. Further, a gate electrode 122 in which the titanium nitride film 104 and the silicon film 105 are stacked is formed thereon via a gate insulating film 121 in which the oxide film 102 and the high dielectric constant insulating film 103 are stacked.
  • extension regions 107 are formed as shown in FIG.
  • boron is used as an impurity, and ion implantation is performed using the gate electrode 122 as a mask under the conditions of an acceleration energy of 0.3 keV and an implantation dose of 5 ⁇ 10 14 atoms / cm 2 .
  • extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101.
  • the junction depth immediately after the implantation is very shallow at 10 nm or less, but boron is diffused by activation annealing described later, and the final junction depth is about 15 nm.
  • sidewall spacers 106 that cover the side surfaces of the gate electrode 122 and the gate insulating film 121 are formed.
  • a P-type extension region 107 is formed, and then a silicon oxide film having a thickness of about 70 nm is deposited on the semiconductor substrate 100.
  • the entire surface is etched back by dry etching to form a sidewall spacer 106 made of a silicon oxide film having a width of about 70 nm on the side surface of the gate electrode 122.
  • Si also wraps around the side wall spacer 106.
  • the amount of wraparound that is, the amount of overlap below the sidewall spacer 106, is smaller than the vertical direction and is about 20 nm.
  • source / drain regions 109 are formed.
  • boron is used as an impurity, and ion implantation is performed using the gate electrode 122 and the sidewall spacer 106 as a mask under conditions of an acceleration energy of 1.5 keV and an implantation dose of 4 ⁇ 10 15 atoms / cm 2 .
  • a P-type source / drain region 109 is formed on the outer side of the sidewall spacer 106 in the first semiconductor region 101.
  • spike annealing at 1000 ° C. for 0 second, the impurities in the extension region 107 and the source / drain region 109 are activated.
  • a source / drain region 109 having a junction depth of 60 nm is formed. This is 10 nm shallower than the second semiconductor region 128 having a depth of 70 nm.
  • the semiconductor device 151 is manufactured.
  • the second semiconductor region 128 having a high Si concentration is formed so as to cover the region where the source / drain region 109 is formed. .
  • the substrate leakage current generated at the PN junctions at the bottom and side of the source / drain region 109 is reduced.
  • the source / drain region 109 may be formed first, and then the second semiconductor region 128 may be formed.
  • the first semiconductor region 101 formation conditions Si ion implantation conditions, extension region 107 implantation conditions, sidewall spacer 106 formation conditions, source / drain region 109 implantation conditions, activation annealing conditions, etc. All are illustrative and are not limited to the above description.
  • the second semiconductor region 128 it is not essential to form the second semiconductor region 128 so as to cover the entire source / drain region 109.
  • angle implantation may be performed at the time of Si implantation to increase the amount of overlap of the second semiconductor region 128 below the sidewall spacer 106.
  • the Si concentration in the side surface portion of the source / drain region 109 can be increased.
  • a region having a high Si concentration is formed particularly at the bottom of the source / drain region 109 by increasing the acceleration energy during Si implantation. You may do it.
  • a region having a high Si concentration may be provided so as to cover both the extension region 107 and the source / drain region 109.
  • FIG. 6B in the second embodiment is performed.
  • ) And (c) may be performed.
  • an Si cap layer having a thickness of about 2 nm is deposited on the first semiconductor region 101 while the oxide film 102 shown in FIG. 5B is formed. Also good. Thereby, the quality of the oxide film 102 can be improved.
  • boron is exemplified as the P-type impurity used for forming the extension region 107 and the source / drain region 109, indium may be used instead. Furthermore, both boron and indium may be used.
  • the semiconductor device of the present disclosure reduces the threshold voltage by using the first semiconductor region containing Ge as a channel formation region, and reduces the substrate leakage current by increasing the Si concentration at the PN junction. This is useful for reducing the power consumption of the transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device (150) is provided with a first semiconductor region (101) of a first conductivity type including Ge, a gate electrode (122) formed on the first semiconductor region (101) with a gate insulating film (121) interposed between, diffusion regions (107) of a second conductivity type formed at portions of the first semiconductor region (101) that are to the two lateral sides of the gate electrode (122), and second semiconductor regions (108) of a first conductivity type formed between the first semiconductor region (101) and diffusion regions (107). The second semiconductor region (108) contains a concentration of Si higher than the channel forming region at the portion of the first semiconductor region (101) below the gate electrode (122).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本開示は、チャネルがＳｉＧｅ層によって形成されたＰ型電界効果型トランジスタ（Ｐ型ＦＥＴ）であって、基板リーク電流の低減が可能なトランジスタとその製造方法に関するものである。 The present disclosure relates to a P-type field effect transistor (P-type FET) having a channel formed of a SiGe layer, and capable of reducing a substrate leakage current, and a method for manufacturing the same.
　半導体装置のデザインルールの縮小に伴い、回路の集積度は飛躍的に向上し、１チップ上に１億個以上の電界効果型トランジスタ（ＦＥＴ、Feild Effect Transistor ）を搭載することも可能となっている。高性能なトランジスタを実現するためには、ゲート長の縮小に加えて、ゲート絶縁膜の薄膜化も求められている。 As the design rules for semiconductor devices have shrunk, the degree of circuit integration has dramatically improved, and more than 100 million field-effect transistors (FETs, Feild-Effect-Transistors) can be mounted on a single chip. Yes. In order to realize a high-performance transistor, it is required to reduce the gate insulating film in addition to reducing the gate length.
　従来、ゲート絶縁膜には、シリコン酸化膜又はその窒化膜であるシリコン酸窒化膜が用いられてきた。しかし、ＥＯＴ（Equivalent Oxide Thickness、シリコン酸化膜換算膜厚）が２ｎｍ以下である薄膜領域になると、ゲートリーク電流が増大し、回路の消費電力が増大する。このため、ゲートリーク電流を低減しつつ、ＥＯＴ薄膜化を実現するために、高誘電率ゲート絶縁膜に関心が寄せられている。 Conventionally, a silicon oxynitride film, which is a silicon oxide film or a nitride film thereof, has been used for the gate insulating film. However, when the thin film region has an EOT (Equivalent Oxide Thickness) of 2 nm or less, the gate leakage current increases and the power consumption of the circuit increases. For this reason, in order to reduce the gate leakage current and realize the EOT thin film, attention is focused on the high dielectric constant gate insulating film.
　また、更なるＥＯＴ薄膜化のために、高誘電率ゲート絶縁膜／メタルゲート電極構造を有するトランジスタについて多くの研究開発がなされている。これは、ゲート電極として従来のシリコン電極に代えて窒化チタン、窒化タンタル等のメタル材料を用い、高誘電率ゲート絶縁膜と組み合わせた構造である。 Further, in order to further reduce the EOT film thickness, many researches and developments have been made on transistors having a high dielectric constant gate insulating film / metal gate electrode structure. This is a structure in which a metal material such as titanium nitride or tantalum nitride is used in place of a conventional silicon electrode as a gate electrode and combined with a high dielectric constant gate insulating film.
　高誘電率ゲート絶縁膜／メタルゲート電極構造を実現する上での重要となる点の一つに、トランジスタのしきい値電圧制御がある。従来用いられていたシリコン電極の場合、不純物イオン注入によってシリコン電極の仕事関数を調整し、Ｎ型ＦＥＴ、Ｐ型ＦＥＴそれぞれに適したしきい値電圧を実現してきた。具体的に、Ｎ型ＦＥＴに対しては、シリコン電極にヒ素、リン等のＮ型不純物を注入することにより仕事関数の低減を図り、Ｐ型ＦＥＴに対しては、シリコン電極にボロン等のＰ型不純物を注入することによって仕事関数の増大を図ってきた。 One of the important points in realizing a high dielectric constant gate insulating film / metal gate electrode structure is the threshold voltage control of the transistor. In the case of a conventionally used silicon electrode, the work function of the silicon electrode is adjusted by impurity ion implantation, and a threshold voltage suitable for each of the N-type FET and the P-type FET has been realized. Specifically, for N-type FETs, an N-type impurity such as arsenic or phosphorus is implanted into the silicon electrode to reduce the work function. For P-type FETs, P or the like such as boron is used for the silicon electrode. Work functions have been increased by implanting type impurities.
　しかしながら、メタル電極については、不純物注入による仕事関数制御ができない。このため、トランジスタのしきい値電圧制御が重要となっている。 However, work functions cannot be controlled by impurity implantation for metal electrodes. For this reason, the threshold voltage control of the transistor is important.
　Ｐ型ＦＥＴのしきい値電圧制御の手段（特に、低減の手段）として、トランジスタのチャネル領域を、従来はＳｉ（シリコン）からなる層であったのに代えて、Ｇｅ（ゲルマニウム）を含むＳｉ1-x Ｇｅx （０＜ｘ≦１）からなる層として形成することが提案されている（非特許文献１）。尚、本明細書中において、Ｓｉ1-x Ｇｅx （０＜ｘ≦１）の意味で単にＳｉＧｅと表記する場合がある。 As a means for controlling the threshold voltage of the P-type FET (particularly, a means for reducing), the channel region of the transistor is replaced with a Si (germanium) containing Si (germanium) instead of a conventional silicon (silicon) layer. It has been proposed to form a layer made of 1-x Ge x (0 <x ≦ 1) (Non-patent Document 1). In this specification, Si 1-x Ge x (0 <x ≦ 1) may be simply expressed as SiGe.
　このような技術によると、例えば、半導体基板に形成されたＰ型ＦＥＴにおいて、半導体基板の表面から５０ｎｍ程度の範囲（チャネル領域の構成される部分を含む範囲）をＳｉＧｅによって形成する。 According to such a technique, for example, in a P-type FET formed on a semiconductor substrate, a range of about 50 nm (a range including a portion where a channel region is formed) is formed from SiGe with SiGe.
　このようにすると、以下に説明するメカニズムにより、しきい値電圧が低減される。 In this case, the threshold voltage is reduced by the mechanism described below.
　まず、Ｓｉのエネルギーバンドギャップは１．１２ｅＶであるのに比べ、Ｇｅのエネルギーバンドギャップは０．６６ｅＶと小さい。また、ＳｉとＧｅとの混晶であるＳｉＧｅのエネルギーバンドギャップは、Ｇｅの組成比ｘに応じて、０．６６～１．１２ｅＶの間にて連続的に変化する。 First, the energy band gap of Ge is as small as 0.66 eV, compared to the energy band gap of Si being 1.12 eV. The energy band gap of SiGe, which is a mixed crystal of Si and Ge, continuously changes between 0.66 and 1.12 eV depending on the Ge composition ratio x.
　また、Ｓｉ及びＧｅは、ほぼ同じ電子親和力を有する。このため、Ｇｅの組成比ｘの変化に伴うＳｉＧｅのエネルギーバンドギャップの変動は、主に、価電子帯のエネルギーの変動に起因する。つまり、ＳｉＧｅの価電子帯のエネルギーは、Ｓｉの価電子帯のエネルギーに比べて高くなる。 Further, Si and Ge have almost the same electron affinity. For this reason, the fluctuation of the energy band gap of SiGe accompanying the change of the Ge composition ratio x is mainly caused by the fluctuation of the energy of the valence band. That is, the energy of the valence band of SiGe is higher than the energy of the valence band of Si.
　この結果、Ｓｉチャネルに代えてＳｉＧｅチャネルを形成することにより、しきい値電圧を低減することが可能となる。尚、しきい値電圧を有意に低減するためには、Ｇｅを１０％よりも多く含む（０．１＜ｘ≦１）ようにする。また、代表的な組成はＸ＝０．５の場合、つまり、Ｓｉ：Ｇｅ＝１：１となる場合である。非特許文献１には、２５０～３００ｍＶのしきい値電圧の低減が報告されている。 As a result, the threshold voltage can be reduced by forming the SiGe channel instead of the Si channel. In order to significantly reduce the threshold voltage, Ge is contained in an amount of more than 10% (0.1 <x ≦ 1). A typical composition is when X = 0.5, that is, when Si: Ge = 1: 1. Non-Patent Document 1 reports a reduction in threshold voltage of 250 to 300 mV.
　しかしながら、前記のようにチャネル部をＳｉ1-x Ｇｅx （０．１＜ｘ≦１）からなる領域に構成する方法を用いてしきい値電圧制御を行った場合、基板リーク電流が増大するという問題が発生する。よって、その解決が課題となっている。 However, when threshold voltage control is performed using a method in which the channel portion is formed in a region made of Si 1-x Ge x (0.1 <x ≦ 1) as described above, the substrate leakage current increases. The problem occurs. Therefore, the solution is an issue.
　以上に鑑み、ＳｉＧｅチャネル構造を有するＰ型ＦＥＴにおいて、基板リーク電流の増大を抑制することが可能なトランジスタとその製造方法とについて以下に説明する。 In view of the above, a transistor capable of suppressing an increase in substrate leakage current in a P-type FET having a SiGe channel structure and a manufacturing method thereof will be described below.
　前記の目的を達成するため、本願発明者は、非特許文献１の方法によってしきい値電圧を制御する場合に基板リーク電流が増大する理由について検討した。 In order to achieve the above object, the present inventor examined the reason why the substrate leakage current increases when the threshold voltage is controlled by the method of Non-Patent Document 1.
　まず、ＦＥＴにおいて、ゲート電極下方のチャネル部をＳｉＧｅによって構成すると、ＦＥＴが有する拡散層（ソース・ドレイン領域、エクステンション領域等）についてもＳｉＧｅからなるものとして形成されることになる。 First, in the FET, when the channel portion below the gate electrode is made of SiGe, the diffusion layer (source / drain region, extension region, etc.) of the FET is also formed of SiGe.
　また、基板リーク電流は、拡散層領域と、チャネル部を含むウェル領域とによって形成されるＰＮ接合に対し、逆バイアスが加えられた場合に発生するリーク電流である。その大きさは、ＰＮ接合部におけるエネルギーバンドギャップの大きさに依存し、エネルギーバンドギャップが小さいほど増大する。 The substrate leakage current is a leakage current generated when a reverse bias is applied to the PN junction formed by the diffusion layer region and the well region including the channel portion. The size depends on the size of the energy band gap at the PN junction, and increases as the energy band gap decreases.
　よって、ＳｉＧｅチャネルを形成した場合、Ｓｉチャネルの場合に比べた基板リーク電流の増大の程度は、ＰＮ接合部におけるエネルギーバンドギャップの大きさに依存し、更には、Ｇｅの組成比ｘに依存することになる。 Therefore, when the SiGe channel is formed, the degree of increase in the substrate leakage current compared with the case of the Si channel depends on the size of the energy band gap at the PN junction, and further depends on the composition ratio x of Ge. It will be.
　そこで、本願発明者は、拡散層領域とウェル領域とによって形成されるＰＮ接合部におけるＳｉ濃度（含有率）を、チャネル部に比べて高くすることにより、しきい値電圧を低減すると共に基板リーク電流の増大を抑制することを考案した。 Therefore, the inventor of the present application reduces the threshold voltage and increases the substrate leakage by increasing the Si concentration (content ratio) in the PN junction portion formed by the diffusion layer region and the well region as compared with the channel portion. It was devised to suppress the increase in current.
　具体的に、本開示に係る半導体装置は、Ｇｅを含む第１導電型の第１の半導体領域と、第１の半導体領域上にゲート絶縁膜を介して形成されたゲート電極と、第１の半導体領域におけるゲート電極の両側方に形成された第２導電型の拡散領域と、第１の半導体領域と拡散領域との間に形成された第１導電型の第２の半導体領域とを備え、第２の半導体領域は、第１の半導体領域におけるゲート電極下方のチャネル形成領域よりも高い濃度のＳｉを含有する。 Specifically, a semiconductor device according to the present disclosure includes a first conductive type first semiconductor region containing Ge, a gate electrode formed on the first semiconductor region with a gate insulating film interposed therebetween, A second conductivity type diffusion region formed on both sides of the gate electrode in the semiconductor region; and a first conductivity type second semiconductor region formed between the first semiconductor region and the diffusion region; The second semiconductor region contains a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region.
　このような半導体装置によると、Ｇｅを含む第１の半導体領域にチャネルが形成されることによりしきい値電圧を制御（低減）しながら、ＰＮ接合の部分においてチャネル形成領域よりもＳｉ濃度が高くなっている（言い換えると、Ｇｅ濃度が低くなっている）ことにより、基板リーク電流の増大を抑制することができる。 According to such a semiconductor device, the Si concentration is higher in the PN junction portion than in the channel formation region while the threshold voltage is controlled (reduced) by forming a channel in the first semiconductor region containing Ge. As a result (in other words, the Ge concentration is low), an increase in substrate leakage current can be suppressed.
　尚、第１の半導体領域はＮ型であり、拡散領域はＰ型であることが好ましい。 Note that the first semiconductor region is preferably N-type and the diffusion region is preferably P-type.
　Ｇｅを含むチャネル（ＳｉＧｅチャネル）とすることによるしきい値電圧の低減は、Ｐ型ＦＥＴにおいて特に有用である。よって、第１の半導体領域がＮ型不純物を含むことによりＮ型となっており、拡散領域がＰ型不純物を含むことによりＰ型となっている場合に、本開示の半導体装置の効果が顕著に得られる。 Reduction of the threshold voltage by using a channel containing Ge (SiGe channel) is particularly useful in a P-type FET. Therefore, when the first semiconductor region is N-type by including N-type impurities and the diffusion region is P-type by including P-type impurities, the effect of the semiconductor device of the present disclosure is remarkable. Is obtained.
　また、拡散領域は、ボロン及びインジウムの少なくとも一方を不純物として含有することが好ましい。また、第１の半導体領域は、ヒ素及びリンの少なくとも一方を不純物として含有することが好ましい。各領域に含まれる不純物として、このような元素を用いることができる。 The diffusion region preferably contains at least one of boron and indium as an impurity. The first semiconductor region preferably contains at least one of arsenic and phosphorus as an impurity. Such an element can be used as an impurity contained in each region.
　また、拡散領域は、ソース・ドレイン領域及びエクステンション領域の少なくとも一方であることが好ましい。 The diffusion region is preferably at least one of a source / drain region and an extension region.
　基板リーク電流が発生する箇所の例としては、ソース・ドレイン領域及びエクステンション領域の底部及び側部のＰＮ接合が挙げられる。よって、拡散領域がソース・ドレイン領域及びエクステンション領域のいずれか一方又は両方であるようにすると、基板リーク電流を抑制することができる。 Examples of locations where substrate leakage current occurs include the PN junctions at the bottom and sides of the source / drain regions and extension regions. Therefore, if the diffusion region is one or both of the source / drain region and the extension region, the substrate leakage current can be suppressed.
　また、第２の半導体領域は、第１の半導体領域と拡散領域との間の全体に形成されていても良い。また、第２の半導体領域は、前記第１の半導体領域と前記拡散領域との間の一部に形成されていても良い。 Further, the second semiconductor region may be formed entirely between the first semiconductor region and the diffusion region. The second semiconductor region may be formed in a part between the first semiconductor region and the diffusion region.
　つまり、基板リーク電流が発生するＰＮ接合の全体についてＳｉ濃度を高くするのであっても良いし、特に基板リーク電流の多い部分についてＳｉ濃度を高くするのであっても良い。 That is, the Si concentration may be increased for the entire PN junction where the substrate leakage current is generated, or the Si concentration may be increased particularly for a portion where the substrate leakage current is large.
　このように、個々の半導体装置の特性等に合わせて適切な箇所に第２の半導体領域を配置することにより、基板リーク電流を抑制することができる。 Thus, the substrate leakage current can be suppressed by disposing the second semiconductor region at an appropriate location in accordance with the characteristics of each semiconductor device.
　また、第２の半導体領域及びチャネル形成領域は、いずれもＳｉ1-x Ｇｅx （０＜ｘ≦１）からなり、第２の半導体領域におけるｘは、チャネル領域におけるｘよりも０．１以上小さいことが好ましい。 Each of the second semiconductor region and the channel formation region is made of Si 1-x Ge x (0 <x ≦ 1), and x in the second semiconductor region is 0.1 or more than x in the channel region. Small is preferable.
　Ｓｉ1-x Ｇｅx （０＜ｘ≦１）において、Ｇｅの組成比であるｘが小さいほどＳｉの濃度が高いのであるから、第２の半導体領域においてｘが小さいことが求められる。特に、０．１以上小さい場合に、基板リーク電流を抑制する効果がより確実に得られる。 In Si 1-x Ge x (0 <x ≦ 1), the smaller the x, which is the Ge composition ratio, the higher the Si concentration. Therefore, it is required that x is small in the second semiconductor region. In particular, when it is smaller than 0.1, the effect of suppressing the substrate leakage current can be obtained more reliably.
　前記の目的を達成するため、本開示に係る半導体装置の製造方法は、基板上に、Ｇｅを含む第１導電型の第１の半導体領域を形成する工程（ａ）と、第１の半導体領域上に、ゲート絶縁膜を介してゲート電極を形成する工程（ｂ）と、第１の半導体領域におけるゲート電極の両側方に、第２導電型の拡散領域を形成する工程（ｃ）と、第１の半導体領域におけるゲート電極の両側方に、第１導電型の第２の半導体領域を形成する工程（ｄ）とを備え、第２の半導体領域は、少なくとも第１の半導体領域と拡散領域との間に位置していると共に、第１の半導体領域におけるゲート電極下方のチャネル形成領域よりも高い濃度のＳｉを含有する。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the present disclosure includes a step (a) of forming a first semiconductor region of a first conductivity type containing Ge on a substrate, and a first semiconductor region. A step (b) of forming a gate electrode via a gate insulating film, a step (c) of forming a second conductivity type diffusion region on both sides of the gate electrode in the first semiconductor region, A step (d) of forming a second semiconductor region of the first conductivity type on both sides of the gate electrode in the one semiconductor region, wherein the second semiconductor region includes at least the first semiconductor region and the diffusion region. And a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region.
　本開示の半導体装置の製造方法によると、本開示の半導体装置を製造することができる。つまり、Ｇｅを含むチャネル形成領域を備えることによりしきい値電圧を低減しながら、ＰＮ接合の部分においてＳｉ濃度が高くなっていることにより基板リーク電流が抑制された半導体装置を製造することができる。 According to the semiconductor device manufacturing method of the present disclosure, the semiconductor device of the present disclosure can be manufactured. That is, it is possible to manufacture a semiconductor device in which the substrate leakage current is suppressed due to the high Si concentration in the PN junction portion while reducing the threshold voltage by providing the channel formation region containing Ge. .
　尚、拡散領域は、ソース・ドレイン領域及びエクステンション領域の少なくとも一方であることが好ましい。また、拡散領域は、ボロン及びインジウムの少なくとも一方をイオン注入することにより形成されることが好ましい。具体的な拡散領域として、このようになっていても良い。 The diffusion region is preferably at least one of a source / drain region and an extension region. The diffusion region is preferably formed by ion implantation of at least one of boron and indium. A specific diffusion region may be as described above.
　また、第２の半導体領域は、Ｓｉイオンの注入により形成しても良い。 Further, the second semiconductor region may be formed by Si ion implantation.
　チャネル形成領域よりもＳｉ濃度が高い第２の半導体領域を形成するために、このようにしても良い。 This may be done in order to form the second semiconductor region having a higher Si concentration than the channel formation region.
　Ｓｉ1-x Ｇｅx （０．１＜ｘ≦１）からなる領域にチャネルを形成することによりしきい値電圧を制御（低減）しながら、基板リーク電流が発生するＰＮ接合部分のＳｉ濃度を高くすることにより基板リーク電流を抑制することができる。 While controlling (reducing) the threshold voltage by forming a channel in a region composed of Si 1-x Ge x (0.1 <x ≦ 1), the Si concentration of the PN junction portion where the substrate leakage current is generated is controlled. Increasing the thickness can suppress the substrate leakage current.
図１は、第１の実施形態における例示的半導体装置の要部断面を模式的に示す図である。FIG. 1 is a diagram schematically illustrating a cross-section of a main part of an exemplary semiconductor device according to the first embodiment. 図２（ａ）～（ｃ）は、第１の実施形態における例示的半導体装置の製造方法の各工程を示す図である。FIGS. 2A to 2C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the first embodiment. 図３（ａ）～（ｃ）は、図２（ｃ）に続いて、第１の実施形態における例示的半導体装置の製造方法の各工程を示す図である。FIGS. 3A to 3C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the first embodiment, following FIG. 2C. 図４は、第２の実施形態における例示的半導体装置の要部断面を模式的に示す図である。FIG. 4 is a diagram schematically illustrating a cross-section of a main part of an exemplary semiconductor device according to the second embodiment. 図５（ａ）～（ｃ）は、第２の実施形態における例示的半導体装置の製造方法の各工程を示す図である。FIGS. 5A to 5C are views showing respective steps of the exemplary semiconductor device manufacturing method according to the second embodiment. 図６（ａ）～（ｃ）は、図５（ｃ）に続いて、第２の実施形態における例示的半導体装置の製造方法の各工程を示す図である。6 (a) to 6 (c) are diagrams showing respective steps of the exemplary semiconductor device manufacturing method according to the second embodiment, following FIG. 5 (c).
　　（第１の実施形態）
　以下、第１の実施形態における例示的半導体装置１５０について、その要部断面を模式的に示す図である図１を参照しながら説明する。 (First embodiment)
Hereinafter, an exemplary semiconductor device 150 according to the first embodiment will be described with reference to FIG.
　図１に示すように、半導体装置１５０は、シリコンからなる半導体基板１００を用いて形成されており、Ｐ型ＦＥＴ構造を有する。半導体基板１００上には、Ｓｉ1-x Ｇｅx （０＜ｘ≦１）からなる第１の半導体領域１０１が形成されている。第１の半導体領域１０１は、膜厚が例えば９０ｎｍであり、リン、ヒ素等のＮ型不純物（ウェル形成、しきい値電圧制御用のチャネル不純物）を含むことによりＮ型になっている。第１の半導体領域１０１の上には、ゲート絶縁膜１２１を介してゲート電極１２２が形成されている。また、ゲート電極１２２及びゲート絶縁膜１２１の両側面を覆うように、シリコン酸化膜からなるサイドウォールスペーサー１０６が形成されている。尚、ゲート絶縁膜１２１は、酸化膜１０２上に、高誘電率絶縁膜１０３が積層された構造である。また、ゲート電極１２２は、金属を含む材料からなるメタルゲート電極、例えば窒化チタン膜１０４の上に、ポリシリコン、アモルファスシリコン等のシリコン膜１０５が積層された構造である。 As shown in FIG. 1, the semiconductor device 150 is formed using a semiconductor substrate 100 made of silicon and has a P-type FET structure. On the semiconductor substrate 100, a first semiconductor region 101 made of Si 1-x Ge x (0 <x ≦ 1) is formed. The first semiconductor region 101 has a film thickness of, for example, 90 nm, and is N-type by including N-type impurities (channel impurities for well formation and threshold voltage control) such as phosphorus and arsenic. A gate electrode 122 is formed on the first semiconductor region 101 with a gate insulating film 121 interposed therebetween. A sidewall spacer 106 made of a silicon oxide film is formed so as to cover both side surfaces of the gate electrode 122 and the gate insulating film 121. The gate insulating film 121 has a structure in which the high dielectric constant insulating film 103 is stacked on the oxide film 102. In addition, the gate electrode 122 has a structure in which a silicon film 105 such as polysilicon or amorphous silicon is stacked on a metal gate electrode made of a material containing metal, for example, a titanium nitride film 104.
　第１の半導体領域１０１におけるゲート電極１２２の両側方には、エクステンション領域１０７が形成されている。エクステンション領域１０７は、Ｐ型不純物であるボロンを含むことによりＰ型であり、深さは１５ｎｍ程度である。 Extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101. The extension region 107 is P-type by including boron, which is a P-type impurity, and has a depth of about 15 nm.
　更に、エクステンション領域１０７の外側には、Ｐ型のソース・ドレイン領域１０９（ソース領域及びドレイン領域を合わせてこのように呼ぶ）が接合深さ６０ｎｍ程度に形成されている。 Further, outside the extension region 107, a P-type source / drain region 109 (referred to as the source region and the drain region together) is formed with a junction depth of about 60 nm.
　また、エクステンション領域１０７と第１の半導体領域１０１との間に、エクステンション領域１０７を覆うように、Ｎ型の第２の半導体領域１０８が形成されている。第２の半導体領域１０８の深さは２０ｎｍ程度であり、エクステンション領域１０７に対して５ｎｍ程度外側に形成されている。 Further, an N-type second semiconductor region 108 is formed between the extension region 107 and the first semiconductor region 101 so as to cover the extension region 107. The depth of the second semiconductor region 108 is about 20 nm, and is formed outside the extension region 107 by about 5 nm.
　ここで、第１の半導体領域１０１を構成するＳｉ1-x Ｇｅx （０＜ｘ≦１）について、例えば、Ｘ＝０．５（つまり、Ｇｅが５０％）であってもよい。 Here, for Si 1-x Ge x (0 <x ≦ 1) constituting the first semiconductor region 101, for example, X = 0.5 (that is, Ge is 50%) may be used.
　半導体装置１５０に構成されたＰ型ＦＥＴが動作する際には、ゲート電極１２２下方における第１の半導体領域１０１の部分にチャネルが形成される。チャネル形成領域がＧｅを含むことにより、Ｓｉチャネルの場合に比べてしきい値電圧が低減している。 When the P-type FET configured in the semiconductor device 150 operates, a channel is formed in the portion of the first semiconductor region 101 below the gate electrode 122. Since the channel formation region contains Ge, the threshold voltage is reduced as compared with the case of the Si channel.
　尚、少しでもＧｅが含まれていればしきい値電圧は低減されるが、実質的に低減の効果を得るためには、１０％程度は含まれていることが好ましい。また、Ｓｉを含まず、Ｇｅのみとなっていても構わない。つまり、０．１＜ｘ≦１を満たすことが好ましい。 It should be noted that the threshold voltage is reduced if even a little Ge is included, but it is preferable that about 10% is included in order to obtain a substantial reduction effect. Moreover, Si may not be included but only Ge may be sufficient. That is, it is preferable to satisfy 0.1 <x ≦ 1.
　このようなチャネル形成領域に比べて、第２の半導体領域１０８におけるＳｉ濃度が高くなっている。具体的には、例えば、Ｓｉ濃度が５０％（Ｇｅの組成比によって記すとｘ＝０．５）であるチャネル形成領域に対して、第２の半導体領域１０８のＳｉ濃度は７５％（Ｇｅの組成比によって記すとｘ＝０．２５）である。 The Si concentration in the second semiconductor region 108 is higher than that in such a channel formation region. Specifically, for example, the Si concentration of the second semiconductor region 108 is 75% (Ge concentration) with respect to a channel formation region where the Si concentration is 50% (x = 0.5 in terms of the Ge composition ratio). In terms of composition ratio, x = 0.25).
　このように、エクステンション領域１０７の底部及び側部のＰＮ接合部は、第２の半導体領域１０８が形成されていることにより、チャネル形成領域に比べてＳｉ濃度が高く（言い換えると、Ｇｅ濃度が低く）なっている。この結果、エクステンション領域１０７のＰＮ接合部において発生する基板リーク電流を約一桁低減することができる。 Thus, the bottom and side PN junctions of the extension region 107 have a higher Si concentration (in other words, a lower Ge concentration) than the channel formation region because the second semiconductor region 108 is formed. It has become. As a result, the substrate leakage current generated at the PN junction in the extension region 107 can be reduced by about one digit.
　尚、チャネル形成領域（第１の半導体領域１０１）においてｘ＝０．５の場合（Ｓｉ濃度では５０％の場合）を一例として説明したが、これには限らない。０＜ｘ≦１の範囲におけるいずれの値である場合にも、チャネル形成領域に比べてＰＮ接合部分（第２の半導体領域１０８）におけるＳｉ濃度が高くなっていれば、基板リーク電流を低減することができる。 Although the case where x = 0.5 in the channel formation region (first semiconductor region 101) (the Si concentration is 50%) has been described as an example, the present invention is not limited thereto. When any value in the range of 0 <x ≦ 1, if the Si concentration in the PN junction portion (second semiconductor region 108) is higher than that in the channel formation region, the substrate leakage current is reduced. be able to.
　また、第２の半導体領域１０８のＳｉ濃度がチャネル形成領域に比べて２５％高くなっている（Ｇｅ組成比ｘが０．２５小さくなっている）例を説明したが、これには限らない。Ｓｉ濃度の差がより小さい場合にも基板リーク電流は低減される。但し、第２の半導体領域１０８がチャネル形成領域に比べて１０％以上高いＳｉ濃度（ｘが０．１以上小さいＧｅ組成）を有していると、有意に基板リーク電流を抑制することができ、望ましい。チャネル形成領域のＳｉ濃度が５０％である場合、第２の半導体領域１０８のＳｉ濃度を６０％～１００％とすることにより、基板リーク電流は３分の１～１００分の１程度に低減される。 In addition, an example in which the Si concentration of the second semiconductor region 108 is 25% higher than that of the channel formation region (Ge composition ratio x is 0.25 smaller) has been described, but the present invention is not limited to this. The substrate leakage current is also reduced when the difference in Si concentration is smaller. However, if the second semiconductor region 108 has a Si concentration 10% or more higher than that of the channel formation region (x is a Ge composition smaller than 0.1 or more), the substrate leakage current can be significantly suppressed. ,desirable. When the Si concentration in the channel formation region is 50%, the substrate leakage current is reduced to about 1/3 to 1/100 by setting the Si concentration in the second semiconductor region 108 to 60% to 100%. The
　また、以上の例の場合、Ｓｉ濃度の高い第２の半導体領域１０８は、エクステンション領域１０７の全体を覆うように（エクステンション領域１０７と第１の半導体領域１０１の間の全体に位置するように）形成されている。しかしながら、これには限らない。重要なのは、基板リーク電流の多く発生するＰＮ接合部についてＳｉ濃度を高めることである。このため、エクステンション領域１０７の側面部（チャネル形成領域側の部分）において基板リーク電流が多く発生するのであれば、エクステンション領域１０７の側面とチャネル形成領域（ゲート電極１２２下方の第１の半導体領域１０１）との間に第２の半導体領域１０８を形成する。同様に、エクステンション領域１０７の底部において基板リーク電流が多く発生するのであれば、この部分に第２の半導体領域１０８を形成する。これにより、基板リーク電流を抑制することができる。 In the case of the above example, the second semiconductor region 108 having a high Si concentration covers the entire extension region 107 (so as to be positioned between the extension region 107 and the first semiconductor region 101). Is formed. However, this is not restrictive. What is important is to increase the Si concentration at the PN junction where a large amount of substrate leakage current occurs. For this reason, if a large amount of substrate leakage current occurs in the side surface portion (the channel forming region side portion) of the extension region 107, the side surface of the extension region 107 and the channel forming region (the first semiconductor region 101 below the gate electrode 122). ) Between the first semiconductor region 108 and the second semiconductor region 108. Similarly, if a large amount of substrate leakage current occurs at the bottom of the extension region 107, the second semiconductor region 108 is formed in this portion. Thereby, a substrate leakage current can be suppressed.
　また、第１の半導体領域１０１の厚さが９０ｎｍ程度である場合を説明したが、これには限らない。エクステンション領域１０７の一部分でもＧｅを含む第１の半導体領域１０１とのＰＮ接合を有していると、該ＰＮ接合部において基板リーク電流が増大する。これを抑制するために、Ｓｉ濃度の高い第２の半導体領域１０８を設ける。従って、第１の半導体領域１０１がエクステンション領域１０７よりも薄い場合にも、基板リーク電流を低減する効果を得ることはできる。 Further, although the case where the thickness of the first semiconductor region 101 is about 90 nm has been described, the present invention is not limited to this. If a part of the extension region 107 has a PN junction with the first semiconductor region 101 containing Ge, the substrate leakage current increases at the PN junction. In order to suppress this, the second semiconductor region 108 having a high Si concentration is provided. Therefore, even when the first semiconductor region 101 is thinner than the extension region 107, the effect of reducing the substrate leakage current can be obtained.
　また、以上では、Ｇｅを含む第１の半導体領域１０１上に酸化膜１０２が形成されている例を説明した。しかし、これには限らない。例えば、第１の半導体領域１０１上にＳｉ層を形成し、その上に酸化膜１０２を形成することもできる。これにより、Ｓｉキャップ付きのＳｉＧｅチャネルを有するＰ型ＦＥＴ構造とすることができる。 In the above description, the example in which the oxide film 102 is formed on the first semiconductor region 101 containing Ge has been described. However, it is not limited to this. For example, a Si layer can be formed on the first semiconductor region 101, and the oxide film 102 can be formed thereon. Thereby, it can be set as the P-type FET structure which has a SiGe channel with a Si cap.
　また、以上では、エクステンション領域１０７に対して５ｎｍ程度外側まで第２の半導体領域１０８が設けられているが、この値には限らず、エクステンション領域１０７を覆うように第２の半導体領域１０８を設けることが要点である。 In the above description, the second semiconductor region 108 is provided to the outside of the extension region 107 by about 5 nm. However, the present invention is not limited to this value, and the second semiconductor region 108 is provided so as to cover the extension region 107. That is the main point.
　次に、本実施形態における例示的半導体装置１５０の製造方法について、その工程を示す図２（ａ）～（ｃ）及び図３（ａ）～（ｃ）を参照して説明する。 Next, a method for manufacturing the exemplary semiconductor device 150 in this embodiment will be described with reference to FIGS. 2A to 2C and FIGS. 3A to 3C showing the steps.
　まず、図２（ａ）に示すように、シリコンからなる半導体基板１００上に、第１の半導体領域１０１を膜厚９０ｎｍに堆積する。第１の半導体領域１０１は、Ｓｉ1-x Ｇｅx においてＧｅ組成比ｘ＝０．５（Ｓｉ濃度として記せば５０％）であるＳｉＧｅ層とする。このためには、ＣＶＤ（chemical vapor deposition）法を用いてシリコンからなる半導体基板１００上にエピタキシャル成長しても良い。この際の条件としては、Ｓｉ系ガスにＳｉＨ4 、Ｇｅ系ガスにＧｅＨ4 を用い、堆積温度を５００℃、ガス圧を２０Torr（２６６６Ｐａ）とする。また、ウェル形成及びしきい値電圧制御のため、第１の半導体領域１０１は、リン、ヒ素等のＮ型不純物を含有させてＮ型の層として形成する。 First, as shown in FIG. 2A, a first semiconductor region 101 is deposited to a thickness of 90 nm on a semiconductor substrate 100 made of silicon. The first semiconductor region 101 is a SiGe layer having a Ge composition ratio x = 0.5 (50% in terms of Si concentration) in Si 1-x Ge x . For this purpose, epitaxial growth may be performed on the semiconductor substrate 100 made of silicon using a CVD (chemical vapor deposition) method. As the conditions for using a GeH 4 to SiH 4, Ge-based gas to Si-based gas, the deposition temperature 500 ° C., the gas pressure and 20 Torr (2666 Pa). Further, for well formation and threshold voltage control, the first semiconductor region 101 is formed as an N-type layer by containing an N-type impurity such as phosphorus or arsenic.
　次に、図２（ｂ）に示すように、第１の半導体領域１０１上に、ゲート絶縁膜１２１を介してゲート電極１２２を形成する。このためには、まず、第１の半導体領域１０１表面のＳｉＧｅをオゾンにより酸化させることにより、膜厚１ｎｍの酸化膜１０２を形成する。次に、該酸化膜１０２上に、例えばハフニウムを含む膜厚２ｎｍの高誘電率絶縁膜１０３を堆積する。続いて、高誘電率絶縁膜１０３上に、メタルゲートとして膜厚１０ｎｍの窒化チタン膜１０４を堆積し、更にその上に、膜厚１００ｎｍのシリコン膜１０５を堆積する。この後、レジストパターニング、ゲートドライエッチング等を行なうことにより、図２（ｂ）に示す酸化膜１０２と高誘電率絶縁膜１０３からなるゲート絶縁膜１２１及び窒化チタン膜１０４とシリコン膜１０５からなるゲート電極１２２の構造を得る。 Next, as shown in FIG. 2B, a gate electrode 122 is formed on the first semiconductor region 101 with a gate insulating film 121 interposed therebetween. For this purpose, first, SiGe on the surface of the first semiconductor region 101 is oxidized with ozone to form an oxide film 102 having a thickness of 1 nm. Next, a high dielectric constant insulating film 103 having a thickness of 2 nm containing hafnium, for example, is deposited on the oxide film 102. Subsequently, a titanium nitride film 104 having a thickness of 10 nm is deposited on the high dielectric constant insulating film 103 as a metal gate, and a silicon film 105 having a thickness of 100 nm is further deposited thereon. Thereafter, by performing resist patterning, gate dry etching, etc., the gate insulating film 121 made of the oxide film 102 and the high dielectric constant insulating film 103 and the gate made of the titanium nitride film 104 and the silicon film 105 shown in FIG. The structure of the electrode 122 is obtained.
　次に、図２（ｃ）に示すように、半導体装置１５０製造における特徴となるＳｉの注入を行なう。具体的には、加速エネルギー１５ｋｅＶ、注入ドーズ量３×１０16atoms／cm2の条件により、ゲート電極１２２をマスクとしてＳｉのイオン注入を行なう。これにより、第１の半導体領域１０１におけるゲート電極１２２の両側方に、表面から深さ２０ｎｍ程度のＳｉ濃度が２５％増加して７５％となった（Ｇｅ濃度が２５％に低減した）Ｎ型の第２の半導体領域１０８が形成される。 Next, as shown in FIG. 2C, Si is implanted which is a feature of the semiconductor device 150 manufacture. Specifically, Si ions are implanted using the gate electrode 122 as a mask under conditions of an acceleration energy of 15 keV and an implantation dose of 3 × 10 16 atoms / cm 2 . As a result, on both sides of the gate electrode 122 in the first semiconductor region 101, the Si concentration about 20 nm deep from the surface increased by 25% to 75% (Ge concentration decreased to 25%). The second semiconductor region 108 is formed.
　尚、イオン注入の際、Ｓｉはゲート電極１２２の下方にも回り込む。但し、回り込み両、つまりゲート電極１２２下方へのオーバーラップ量は、深さに比べて小さく、１０ｎｍ以下である。 In addition, during ion implantation, Si also goes below the gate electrode 122. However, the amount of overlap between the wraparound, that is, the lower part of the gate electrode 122 is smaller than the depth and is 10 nm or less.
　次に、図３（ａ）に示すように、エクステンション注入を行なう。具体的には、注入する不純物としてボロンを用い、加速エネルギー０．３ｋｅＶ、注入ドーズ量５×１０14atoms／cm2の条件によりゲート電極１２２をマスクとしてイオン注入を行なう。これにより、第１の半導体領域１０１におけるゲート電極１２２の両側方にＰ型のエクステンション領域１０７を形成する。注入直後の接合深さは１０ｎｍ以下と非常に浅いが、後述する活性化アニールによりボロンが拡散し、最終的な接合深さは１５ｎｍ程度となる。このため、エクステンション領域１０７は、深さが２０ｎｍ程度である第２の半導体領域１０８よりも５ｎｍ浅く形成されることになる。 Next, extension injection is performed as shown in FIG. Specifically, boron is used as an impurity to be implanted, and ion implantation is performed using the gate electrode 122 as a mask under conditions of an acceleration energy of 0.3 keV and an implantation dose of 5 × 10 14 atoms / cm 2 . Thus, P-type extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101. The junction depth immediately after the implantation is very shallow at 10 nm or less, but boron is diffused by activation annealing described later, and the final junction depth is about 15 nm. Therefore, the extension region 107 is formed 5 nm shallower than the second semiconductor region 108 having a depth of about 20 nm.
　次に、図３（ｂ）に示すように、ゲート電極１２２及びゲート絶縁膜１２１の側面を覆うサイドウォールスペーサー１０６を形成する。このためには、エクステンション領域１０７を形成した後、半導体基板１００上に膜厚７０ｎｍ程度のシリコン酸化膜を堆積する。続いて、ドライエッチングにより全面エッチバックを行なうことにより、ゲート電極１２２の側面上に幅７０ｎｍ程度のシリコン酸化膜からなるサイドウォールスペーサー１０６を形成する。 Next, as shown in FIG. 3B, sidewall spacers 106 that cover the side surfaces of the gate electrode 122 and the gate insulating film 121 are formed. For this purpose, after the extension region 107 is formed, a silicon oxide film having a thickness of about 70 nm is deposited on the semiconductor substrate 100. Subsequently, the entire surface is etched back by dry etching to form a sidewall spacer 106 made of a silicon oxide film having a width of about 70 nm on the side surface of the gate electrode 122.
　次に、図３（ｃ）に示すように、ソース・ドレイン領域１０９を形成する。このために、不純物としてボロンを用い、加速エネルギー１．５ｋｅＶ、注入ドーズ量４×１０15atoms／cm2の条件により、ゲート電極１２２及びサイドウォールスペーサー１０６をマスクとしてイオン注入を行なう。これにより、第１の半導体領域１０１におけるサイドウォールスペーサー１０６の外側方の部分にＰ型のソース・ドレイン領域１０９が形成される。続いて、１０００℃、０秒（目標到達温度に達した後、直ちに降温する）の条件のスパイクアニールを行なうことにより、エクステンション領域１０７及びソース・ドレイン領域１０９の不純物を活性化させる。このアニールにより、接合深さ６０ｎｍのソース・ドレイン領域１０９が形成される。 Next, as shown in FIG. 3C, source / drain regions 109 are formed. For this purpose, boron is used as an impurity, and ion implantation is performed using the gate electrode 122 and the sidewall spacer 106 as a mask under conditions of an acceleration energy of 1.5 keV and an implantation dose of 4 × 10 15 atoms / cm 2 . As a result, a P-type source / drain region 109 is formed on the outer side of the sidewall spacer 106 in the first semiconductor region 101. Subsequently, the impurity in the extension region 107 and the source / drain region 109 is activated by performing spike annealing under the conditions of 1000 ° C. and 0 seconds (the temperature immediately decreases after reaching the target temperature). By this annealing, a source / drain region 109 having a junction depth of 60 nm is formed.
　以上により、半導体装置１５０が製造される。本実施形態の場合、エクステンション領域１０７を形成する前に、エクステンション領域１０７が形成される領域を覆うように、Ｓｉ濃度が高い第２の半導体領域１０８を形成することを特徴としている。これにより、エクステンション領域１０７の底部及び側部のＰＮ接合部において発生する基板リーク電流を低減している。本実施形態の例では、チャネル形成領域（第１の半導体領域１０１）におけるＳｉ濃度５０％に対してＰＮ接合部（第２の半導体領域１０８）におけるＳｉ濃度は７５％であり、２５％の差があることから、基板リーク電流は一桁程度低減している。 Thus, the semiconductor device 150 is manufactured. In the present embodiment, before the extension region 107 is formed, the second semiconductor region 108 having a high Si concentration is formed so as to cover the region where the extension region 107 is formed. This reduces the substrate leakage current generated at the bottom and side PN junctions of the extension region 107. In the example of the present embodiment, the Si concentration in the PN junction (second semiconductor region 108) is 75% with respect to the Si concentration in the channel formation region (first semiconductor region 101) is 50%, which is a difference of 25%. Therefore, the substrate leakage current is reduced by about an order of magnitude.
　尚、以上に説明したように先に第２の半導体領域１０８を形成すると、Ｓｉ注入によるプリアモルファス化によって短チャネル特性を改善する効果が期待できる。しかしながら、以上とは異なる工程順として、先にエクステンション領域１０７を形成し、その後に第２の半導体領域１０８を形成することもできる。この場合にも、基板リーク電流を低減する効果は得られる。 As described above, when the second semiconductor region 108 is formed first, an effect of improving short channel characteristics by pre-amorphization by Si implantation can be expected. However, it is also possible to form the extension region 107 first and then form the second semiconductor region 108 as a process order different from the above. Also in this case, the effect of reducing the substrate leakage current can be obtained.
　また、Ｓｉ1-x Ｇｅx （０＜ｘ≦１）層である第１の半導体領域１０１の形成条件、Ｓｉイオンの注入条件、エクステンション領域１０７の注入条件、サイドウォールスペーサー１０６の形成条件、ソース・ドレイン領域１０９の注入条件、活性化アニールの条件等について、いずれも例示するものであって、上記の記載には限定されない。 Also, the formation conditions of the first semiconductor region 101 that is the Si 1-x Ge x (0 <x ≦ 1) layer, the Si ion implantation conditions, the extension region 107 implantation conditions, the sidewall spacer 106 formation conditions, and the source -The drain region 109 implantation conditions, activation annealing conditions, etc. are all illustrated, and are not limited to the above description.
　また、以上の説明では、Ｓｉ濃度の高い第２の半導体領域１０８は、エクステンション領域１０７の全体を覆うように形成している。しかし、基板リーク電流の発生箇所に合わせて配置しても良い。エクステンション領域１０７の側面部（チャネル形成領域の側）において基板リーク電流が多く発生するのであれば、Ｓｉ注入時に角度注入を行なってゲート電極１２２の下方に対する第２の半導体領域１０８のオーバーラップ量を増加させることもできる。これにより、エクステンション領域１０７の側面部におけるＳｉ濃度を増大させることができる。また、エクステンション領域１０７の底部において基板リーク電流が多く発生するのであれば、Ｓｉ注入時の加速エネルギーをより大きくすることにより、特にエクステンション領域１０７の底部にＳｉ濃度の高い領域を形成しても良い。 In the above description, the second semiconductor region 108 having a high Si concentration is formed so as to cover the entire extension region 107. However, you may arrange | position according to the generation | occurrence | production location of a board | substrate leak current. If a large amount of substrate leakage current is generated in the side surface portion (channel forming region side) of the extension region 107, angle implantation is performed during Si implantation so that the amount of overlap of the second semiconductor region 108 below the gate electrode 122 is reduced. It can also be increased. Thereby, the Si concentration in the side surface portion of the extension region 107 can be increased. If a large amount of substrate leakage current is generated at the bottom of the extension region 107, a region having a high Si concentration may be formed particularly at the bottom of the extension region 107 by increasing the acceleration energy during Si implantation. .
　また、図２（ａ）の工程の後、図２（ｂ）に示す酸化膜１０２を形成する間に、第１の半導体領域１０１上に膜厚２ｎｍ程度のＳｉキャップ層を堆積するようにしても良い。これにより、酸化膜１０２の品質を向上することができる。 Further, after the step of FIG. 2A, an Si cap layer having a thickness of about 2 nm is deposited on the first semiconductor region 101 while the oxide film 102 shown in FIG. 2B is formed. Also good. Thereby, the quality of the oxide film 102 can be improved.
　　（第２の実施形態）
　以下、第２の実施形態における例示的半導体装置１５１について、その要部断面を模式的に示す図である図４を参照しながら説明する。ここで、半導体装置１５１の構成のうち、第１の実施形態の半導体装置１５０と共通の部分については同じ符号を用いることにより詳しい説明を省略し、相違点を主に説明する。 (Second Embodiment)
Hereinafter, an exemplary semiconductor device 151 according to the second embodiment will be described with reference to FIG. 4 which is a diagram schematically showing a cross-section of the main part thereof. Here, in the configuration of the semiconductor device 151, parts common to the semiconductor device 150 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted, and differences are mainly described.
　第１の実施形態の半導体装置１５０の場合、Ｐ型のエクステンション領域１０７を覆うように、Ｓｉ濃度がチャネル形成領域に比べて高いＮ型の第２の半導体領域１０８を有している。これに対し、本実施形態の半導体装置１５１の場合には、Ｐ型のソース・ドレイン領域１０９を覆うように、Ｓｉ濃度がチャネル形成領域に比べて高いＮ型の第２の半導体領域１２８が形成されている。 The semiconductor device 150 according to the first embodiment includes the N-type second semiconductor region 108 having a higher Si concentration than the channel formation region so as to cover the P-type extension region 107. In contrast, in the case of the semiconductor device 151 of the present embodiment, the N-type second semiconductor region 128 having a higher Si concentration than the channel formation region is formed so as to cover the P-type source / drain region 109. Has been.
　ここで、ソース・ドレイン領域１０９の深さは６０ｎｍ程度、第２の半導体領域１２８の深さは７０ｎｍ程度である。また、第１の実施形態と同様、チャネル形成領域（ゲート電極１２２下方の第１の半導体領域１０１）においてＳｉ濃度は５０％である。第２の半導体領域１２８のＳｉ濃度は７５％である。 Here, the depth of the source / drain region 109 is about 60 nm, and the depth of the second semiconductor region 128 is about 70 nm. Further, similarly to the first embodiment, the Si concentration is 50% in the channel formation region (the first semiconductor region 101 below the gate electrode 122). The Si concentration of the second semiconductor region 128 is 75%.
　このような構成により、本実施形態の半導体装置１５１において、ソース・ドレイン領域１０９の底部及び側部のＰＮ接合部（ソース・ドレイン領域１０９と、ウェル及びチャネル形成領域とのＰＮ接合部）における基板リーク電流を抑制することができる。 With such a configuration, in the semiconductor device 151 of the present embodiment, the substrate at the PN junction at the bottom and sides of the source / drain region 109 (PN junction between the source / drain region 109 and the well and channel formation region). Leakage current can be suppressed.
　尚、ソース・ドレイン領域１０９全体を第２の半導体領域１２８が覆うことは必須ではなく、基板リーク電流が多く発生する箇所のみに第２の半導体領域を設けても良い。例えば、ソース・ドレイン領域１０９の底部のみ又は側部のみに設けることもできる。 Note that it is not essential for the second semiconductor region 128 to cover the entire source / drain region 109, and the second semiconductor region may be provided only at a location where a large substrate leakage current occurs. For example, the source / drain region 109 may be provided only at the bottom or only at the side.
　また、エクステンション領域１０７及びソース・ドレイン領域１０９の両方を覆うように、Ｓｉ濃度の高い領域を設けても良い。つまり、第１の実施形態における第２の半導体領域１０８と、第２の実施形態における第２の半導体領域１２８とを両方備えるような半導体装置としても良い。この場合、エクステンション領域１０７及びソース・ドレイン領域１０９の両方について、ＰＮ接合部における基板リーク電流を低減することができる。 Further, a region having a high Si concentration may be provided so as to cover both the extension region 107 and the source / drain region 109. In other words, the semiconductor device may include both the second semiconductor region 108 in the first embodiment and the second semiconductor region 128 in the second embodiment. In this case, the substrate leakage current at the PN junction can be reduced for both the extension region 107 and the source / drain region 109.
　また、チャネル形成領域に比べて第２の半導体領域１２８のＳｉ濃度を２５％高くしているが、これは必須ではない。Ｓｉ濃度を１０％高くする（チャネル形成領域においてＳｉが５０％であるのに対し、第２の半導体領域１２８においてＳｉを６０％とする）だけでも、基板リーク電流を３分の１程度に抑制することができる。 Further, the Si concentration of the second semiconductor region 128 is increased by 25% compared to the channel formation region, but this is not essential. Even if the Si concentration is increased by 10% (Si is 50% in the channel formation region, while Si is 60% in the second semiconductor region 128), the substrate leakage current is suppressed to about one third. can do.
　また、第１の半導体領域１０１の厚さが９０ｎｍであること、第２の半導体領域１２８がソース・ドレイン領域１０９から１０ｎｍ外側にまで形成されていること等についても例示であって、これらに限定されることはない。 Further, the thickness of the first semiconductor region 101 is 90 nm, the second semiconductor region 128 is formed from the source / drain region 109 to the outside of 10 nm, and the like. It will never be done.
　次に、本実施形態における例示的半導体装置１５１の製造方法について、その工程を示す図５（ａ）～（ｃ）及び図６（ａ）～（ｃ）を参照して説明する。 Next, a method for manufacturing the exemplary semiconductor device 151 in the present embodiment will be described with reference to FIGS. 5A to 5C and FIGS. 6A to 6C showing the steps.
　図５（ａ）及び（ｂ）の工程は、第１の実施形態において説明した図２（ａ）及び（ｂ）の工程と同様である。これらの工程により、シリコンからなる半導体基板１００上にＳｉＧｅ（Ｇｅ組成５０％）からなる第１の半導体領域１０１が形成される。また、その上に、酸化膜１０２及び高誘電率絶縁膜１０３の積層されたゲート絶縁膜１２１を介して、窒化チタン膜１０４及びシリコン膜１０５の積層されたゲート電極１２２が形成される。 5A and 5B are the same as the steps of FIGS. 2A and 2B described in the first embodiment. By these steps, the first semiconductor region 101 made of SiGe (Ge composition 50%) is formed on the semiconductor substrate 100 made of silicon. Further, a gate electrode 122 in which the titanium nitride film 104 and the silicon film 105 are stacked is formed thereon via a gate insulating film 121 in which the oxide film 102 and the high dielectric constant insulating film 103 are stacked.
　この後、図５（ｃ）のように、エクステンション領域１０７を形成する。このためには、不純物としてボロンを用い、加速エネルギー０．３ｋｅＶ、注入ドーズ量５×１０14atoms／cm2の条件によりゲート電極１２２をマスクとしてイオン注入を行なう。これにより、第１の半導体領域１０１におけるゲート電極１２２の両側方にエクステンション領域１０７が形成される。注入直後の接合深さは１０ｎｍ以下と非常に浅いが、後述する活性化アニールによりボロンが拡散し、最終的な接合深さは１５ｎｍ程度となる。 Thereafter, extension regions 107 are formed as shown in FIG. For this purpose, boron is used as an impurity, and ion implantation is performed using the gate electrode 122 as a mask under the conditions of an acceleration energy of 0.3 keV and an implantation dose of 5 × 10 14 atoms / cm 2 . As a result, extension regions 107 are formed on both sides of the gate electrode 122 in the first semiconductor region 101. The junction depth immediately after the implantation is very shallow at 10 nm or less, but boron is diffused by activation annealing described later, and the final junction depth is about 15 nm.
　次に、図６（ａ）に示すように、ゲート電極１２２及びゲート絶縁膜１２１の側面を覆うサイドウォールスペーサー１０６を形成する。このためには、Ｐ型のエクステンション領域１０７を形成した後、半導体基板１００上に膜厚７０ｎｍ程度のシリコン酸化膜を堆積する。続いて、ドライエッチングにより全面エッチバックを行なうことにより、ゲート電極１２２の側面上に幅７０ｎｍ程度のシリコン酸化膜からなるサイドウォールスペーサー１０６を形成する。 Next, as shown in FIG. 6A, sidewall spacers 106 that cover the side surfaces of the gate electrode 122 and the gate insulating film 121 are formed. For this purpose, a P-type extension region 107 is formed, and then a silicon oxide film having a thickness of about 70 nm is deposited on the semiconductor substrate 100. Subsequently, the entire surface is etched back by dry etching to form a sidewall spacer 106 made of a silicon oxide film having a width of about 70 nm on the side surface of the gate electrode 122.
　次に、図６（ｂ）に示すように、半導体装置１５１製造における特徴となるＳｉの注入を行なう。具体的には、加速エネルギー５５ｋｅＶ、注入ドーズ量７．２×１０16atoms／cm2の条件により、ゲート電極１２２をマスクとしてＳｉのイオン注入を行なう。これにより、第１の半導体領域１０１におけるサイドウォールスペーサー１０６の外側方に、表面から深さ７０ｎｍ程度のＳｉ濃度が７５％に増加した（Ｇｅ濃度が２５％に低減した）第２のＮ型の半導体領域１２８が形成される。 Next, as shown in FIG. 6B, Si implantation, which is a feature in the manufacture of the semiconductor device 151, is performed. Specifically, Si ions are implanted using the gate electrode 122 as a mask under the conditions of an acceleration energy of 55 keV and an implantation dose of 7.2 × 10 16 atoms / cm 2 . As a result, on the outside of the side wall spacer 106 in the first semiconductor region 101, the Si concentration at a depth of about 70 nm from the surface increased to 75% (Ge concentration decreased to 25%). A semiconductor region 128 is formed.
　尚、イオン注入の際、Ｓｉはサイドウォールスペーサー１０６の下方にも回り込む。但し、回り込み量、つまりサイドウォールスペーサー１０６下方へのオーバーラップ量は、垂直方向に比べて小さく、２０ｎｍ程度である。 In addition, during ion implantation, Si also wraps around the side wall spacer 106. However, the amount of wraparound, that is, the amount of overlap below the sidewall spacer 106, is smaller than the vertical direction and is about 20 nm.
　次に、図６（ｃ）に示すように、ソース・ドレイン領域１０９を形成する。このためには、不純物としてボロンを用い、加速エネルギー１．５ｋｅＶ、注入ドーズ量４×１０15atoms／cm2の条件により、ゲート電極１２２及びサイドウォールスペーサー１０６をマスクとしてイオン注入を行なう。これにより、第１の半導体領域１０１におけるサイドウォールスペーサー１０６の外側方の部分にＰ型のソース・ドレイン領域１０９が形成される。続いて、１０００℃、０秒の条件のスパイクアニールを行なうことにより、エクステンション領域１０７及びソース・ドレイン領域１０９の不純物を活性化させる。このアニールにより、接合深さ６０ｎｍのソース・ドレイン領域１０９が形成される。これは、深さが７０ｎｍである第２の半導体領域１２８よりも１０ｎｍ浅いことになる。 Next, as shown in FIG. 6C, source / drain regions 109 are formed. For this purpose, boron is used as an impurity, and ion implantation is performed using the gate electrode 122 and the sidewall spacer 106 as a mask under conditions of an acceleration energy of 1.5 keV and an implantation dose of 4 × 10 15 atoms / cm 2 . As a result, a P-type source / drain region 109 is formed on the outer side of the sidewall spacer 106 in the first semiconductor region 101. Subsequently, by performing spike annealing at 1000 ° C. for 0 second, the impurities in the extension region 107 and the source / drain region 109 are activated. By this annealing, a source / drain region 109 having a junction depth of 60 nm is formed. This is 10 nm shallower than the second semiconductor region 128 having a depth of 70 nm.
　以上により、半導体装置１５１が製造される。本実施形態の場合、ソース・ドレイン領域１０９を形成する前に、ソース・ドレイン領域１０９が形成される領域を覆うように、Ｓｉ濃度が高い第２の半導体領域１２８を形成することを特徴としている。これにより、ソース・ドレイン領域１０９の底部及び側部のＰＮ接合部において発生する基板リーク電流を低減している。 Thus, the semiconductor device 151 is manufactured. In the present embodiment, before the source / drain region 109 is formed, the second semiconductor region 128 having a high Si concentration is formed so as to cover the region where the source / drain region 109 is formed. . As a result, the substrate leakage current generated at the PN junctions at the bottom and side of the source / drain region 109 is reduced.
　尚、以上とは異なる工程順として、先にソース・ドレイン領域１０９を形成し、その後に第２の半導体領域１２８を形成することもできる。 In addition, as a process order different from the above, the source / drain region 109 may be formed first, and then the second semiconductor region 128 may be formed.
　また、第１の半導体領域１０１の形成条件、Ｓｉイオンの注入条件、エクステンション領域１０７の注入条件、サイドウォールスペーサー１０６の形成条件、ソース・ドレイン領域１０９の注入条件、活性化アニールの条件等について、いずれも例示するものであって、上記の記載には限定されない。 The first semiconductor region 101 formation conditions, Si ion implantation conditions, extension region 107 implantation conditions, sidewall spacer 106 formation conditions, source / drain region 109 implantation conditions, activation annealing conditions, etc. All are illustrative and are not limited to the above description.
　また、ソース・ドレイン領域１０９の全体を覆うように第２の半導体領域１２８を形成することは必須ではない。例えば、Ｓｉ注入時に角度注入を行なってサイドウォールスペーサー１０６の下方に対する第２の半導体領域１２８のオーバーラップ量を増加させても良い。これにより、ソース・ドレイン領域１０９の側面部におけるＳｉ濃度を増大させることができる。その結果、側面部が主要なリーク源である場合の基板リーク電流の低減が可能となる。また、ソース・ドレイン領域１０９の底部において基板リーク電流が多く発生するのであれば、Ｓｉ注入時の加速エネルギーをより大きくすることにより、特にソース・ドレイン領域１０９の底部にＳｉ濃度の高い領域を形成しても良い。 Also, it is not essential to form the second semiconductor region 128 so as to cover the entire source / drain region 109. For example, angle implantation may be performed at the time of Si implantation to increase the amount of overlap of the second semiconductor region 128 below the sidewall spacer 106. Thereby, the Si concentration in the side surface portion of the source / drain region 109 can be increased. As a result, it is possible to reduce the substrate leakage current when the side surface portion is the main leakage source. Further, if a large amount of substrate leakage current occurs at the bottom of the source / drain region 109, a region having a high Si concentration is formed particularly at the bottom of the source / drain region 109 by increasing the acceleration energy during Si implantation. You may do it.
　更に、エクステンション領域１０７及びソース・ドレイン領域１０９の両方を覆うように、Ｓｉ濃度の高い領域を設けても良い。このためには、例えば、第１の実施形態における図２（ａ）～（ｃ）と図３（ａ）及び（ｂ）までの工程を終えた後、第２の実施形態における図６（ｂ）及び（ｃ）と同様の工程を行なえばよい。これにより、エクステンション領域１０７及びソース・ドレイン領域１０９の両方について、基板リーク電流を抑制した半導体装置を製造することができる。 Furthermore, a region having a high Si concentration may be provided so as to cover both the extension region 107 and the source / drain region 109. For this purpose, for example, after the steps from FIGS. 2A to 2C and FIGS. 3A and 3B in the first embodiment are completed, FIG. 6B in the second embodiment is performed. ) And (c) may be performed. Thereby, a semiconductor device in which the substrate leakage current is suppressed in both the extension region 107 and the source / drain region 109 can be manufactured.
　また、図５（ａ）の工程の後、図５（ｂ）に示す酸化膜１０２を形成する間に、第１の半導体領域１０１上に膜厚２ｎｍ程度のＳｉキャップ層を堆積するようにしても良い。これにより、酸化膜１０２の品質を向上することができる。 Further, after the step of FIG. 5A, an Si cap layer having a thickness of about 2 nm is deposited on the first semiconductor region 101 while the oxide film 102 shown in FIG. 5B is formed. Also good. Thereby, the quality of the oxide film 102 can be improved.
　また、エクステンション領域１０７、ソース・ドレイン領域１０９の形成等に用いるＰ型不純物としてボロンを例示したが、これに代えてインジウムを用いても良い。更には、ボロン及びインジウムの両方を用いても良い。 Further, although boron is exemplified as the P-type impurity used for forming the extension region 107 and the source / drain region 109, indium may be used instead. Furthermore, both boron and indium may be used.
　本開示の半導体装置は、Ｇｅを含む第１の半導体領域をチャネル形成領域とすることによりしきい値電圧を低減すると共に、ＰＮ接合部においてＳｉ濃度を高くすることにより基板リーク電流を低減することができ、トランジスタの低消費電力化に有用である。 The semiconductor device of the present disclosure reduces the threshold voltage by using the first semiconductor region containing Ge as a channel formation region, and reduces the substrate leakage current by increasing the Si concentration at the PN junction. This is useful for reducing the power consumption of the transistor.
１００　　　　　　半導体基板
１０１　　　　　　第１の半導体領域
１０２　　　　　　酸化膜
１０３　　　　　　高誘電率絶縁膜
１０４　　　　　　窒化チタン膜
１０５　　　　　　シリコン膜
１０６　　　　　　サイドウォールスペーサー
１０７　　　　　　エクステンション領域
１０８、１２８　　第２の半導体領域
１０９　　　　　　ソース・ドレイン領域
１２１　　　　　　ゲート絶縁膜
１２２　　　　　　ゲート電極
１５０、１５１　　半導体装置 100 Semiconductor substrate 101 First semiconductor region 102 Oxide film 103 High dielectric constant insulating film 104 Titanium nitride film 105 Silicon film 106 Side wall spacer 107 Extension region 108, 128 Second semiconductor region 109 Source / drain region 121 Gate insulating film 122 Gate electrode 150, 151 Semiconductor device

Claims (12)

  1. 　Ｇｅを含む第１導電型の第１の半導体領域と、
    　前記第１の半導体領域上にゲート絶縁膜を介して形成されたゲート電極と、
    　前記第１の半導体領域における前記ゲート電極の両側方に形成された第２導電型の拡散領域と、
    　前記第１の半導体領域と前記拡散領域との間に形成された第１導電型の第２の半導体領域とを備え、
    　前記第２の半導体領域は、前記第１の半導体領域における前記ゲート電極下方のチャネル形成領域よりも高い濃度のＳｉを含有することを特徴とする半導体装置。     A first conductivity type first semiconductor region containing Ge;
    A gate electrode formed on the first semiconductor region via a gate insulating film;
    A diffusion region of a second conductivity type formed on both sides of the gate electrode in the first semiconductor region;
    A second semiconductor region of a first conductivity type formed between the first semiconductor region and the diffusion region;
    The semiconductor device, wherein the second semiconductor region contains a higher concentration of Si than a channel formation region below the gate electrode in the first semiconductor region.
  2. 　請求項１において、
    　前記第１の半導体領域はＮ型であり、
    　前記拡散領域はＰ型であることを特徴とする半導体装置。     In claim 1,
    The first semiconductor region is N-type;
    The semiconductor device, wherein the diffusion region is P-type.
  3. 　請求項１において、
    　前記拡散領域は、ボロン及びインジウムの少なくとも一方を不純物として含有することを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the diffusion region contains at least one of boron and indium as an impurity.
  4. 　請求項１において、
    　前記第１の半導体領域は、ヒ素及びリンの少なくとも一方を不純物として含有することを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the first semiconductor region contains at least one of arsenic and phosphorus as an impurity.
  5. 　請求項１において、
    　前記拡散領域は、ソース・ドレイン領域及びエクステンション領域の少なくとも一方であることを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the diffusion region is at least one of a source / drain region and an extension region.
  6. 　請求項１において、
    　前記第２の半導体領域は、前記第１の半導体領域と前記拡散領域との間の全体に形成されていることを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the second semiconductor region is formed entirely between the first semiconductor region and the diffusion region.
  7. 　請求項１において、
    　前記第２の半導体領域は、前記第１の半導体領域と前記拡散領域との間の一部に形成されていることを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the second semiconductor region is formed in a part between the first semiconductor region and the diffusion region.
  8. 　請求項１において、
    　前記第２の半導体領域及び前記チャネル形成領域は、いずれもＳｉ1-x Ｇｅx （０＜ｘ≦１）からなり、
    　前記第２の半導体領域におけるｘは、前記チャネル領域におけるｘよりも０．１以上小さいことを特徴とする半導体装置。     In claim 1,
    Each of the second semiconductor region and the channel formation region is made of Si 1-x Ge x (0 <x ≦ 1).
    X in the second semiconductor region is 0.1 or more smaller than x in the channel region.
  9. 　基板上に、Ｇｅを含む第１導電型の第１の半導体領域を形成する工程（ａ）と、
    　前記第１の半導体領域上に、ゲート絶縁膜を介してゲート電極を形成する工程（ｂ）と、
    　前記第１の半導体領域における前記ゲート電極の両側方に、第２導電型の拡散領域を形成する工程（ｃ）と、
    　前記第１の半導体領域における前記ゲート電極の両側方に、第１導電型の第２の半導体領域を形成する工程（ｄ）とを備え、
    　前記第２の半導体領域は、少なくとも前記第１の半導体領域と前記拡散領域との間に位置していると共に、前記第１の半導体領域における前記ゲート電極下方のチャネル形成領域よりも高い濃度のＳｉを含有することを特徴とする半導体装置の製造方法。     Forming a first semiconductor region of the first conductivity type containing Ge on the substrate;
    Forming a gate electrode on the first semiconductor region via a gate insulating film;
    Forming a second conductivity type diffusion region on both sides of the gate electrode in the first semiconductor region (c);
    Forming a second semiconductor region of the first conductivity type on both sides of the gate electrode in the first semiconductor region;
    The second semiconductor region is located at least between the first semiconductor region and the diffusion region, and has a higher concentration of Si than the channel formation region below the gate electrode in the first semiconductor region. A method for manufacturing a semiconductor device, comprising:
  10. 　請求項９において、
    　前記拡散領域は、ソース・ドレイン領域及びエクステンション領域の少なくとも一方であることを特徴とする半導体装置の製造方法。     In claim 9,
    The method for manufacturing a semiconductor device, wherein the diffusion region is at least one of a source / drain region and an extension region.
  11. 　請求項９において、
    　前記拡散領域は、ボロン及びインジウムの少なくとも一方をイオン注入することにより形成されることを特徴とする半導体装置の製造方法。     In claim 9,
    The diffusion region is formed by ion implantation of at least one of boron and indium.
  12. 　請求項９において、
    　前記第２の半導体領域は、Ｓｉイオンの注入により形成することを特徴とする半導体装置の製造方法。     In claim 9,
    The method of manufacturing a semiconductor device, wherein the second semiconductor region is formed by implanting Si ions.
PCT/JP2009/007030 2009-05-13 2009-12-18 Semiconductor device and method of producing same WO2010131312A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-116577 2009-05-13
JP2009116577A JP2010267713A (en) 2009-05-13 2009-05-13 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2010131312A1 true WO2010131312A1 (en) 2010-11-18

Family

ID=43084704

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/007030 WO2010131312A1 (en) 2009-05-13 2009-12-18 Semiconductor device and method of producing same

Country Status (2)

Country Link
JP (1) JP2010267713A (en)
WO (1) WO2010131312A1 (en)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319348A (en) * 1989-06-16 1991-01-28 Fujitsu Ltd Manufacture of semiconductor device
JPH04280682A (en) * 1991-03-08 1992-10-06 Toshiba Corp Semiconductor device and manufacture thereof
JPH06350086A (en) * 1993-06-08 1994-12-22 Matsushita Electron Corp Manufacture of semiconductor device
JPH10270685A (en) * 1997-03-27 1998-10-09 Sony Corp Field-effect transistor and manufacture thereof, semiconductor device and manufacture thereof and logic circuit containing semiconductor device thereof and semiconductor substrate
JP2000077658A (en) * 1998-08-28 2000-03-14 Toshiba Corp Manufacture of semiconductor device
JP2004039762A (en) * 2002-07-01 2004-02-05 Toshiba Corp Field effect transistor and method of manufacturing the same
JP2004214457A (en) * 2003-01-06 2004-07-29 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2006202951A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Mos-type field effect transistor and manufacturing method thereof
JP2007500433A (en) * 2003-07-28 2007-01-11 インターナショナル・ビジネス・マシーンズ・コーポレーション Method of slowing dopant diffusion in a semiconductor substrate and device manufactured thereby
JP2007019314A (en) * 2005-07-08 2007-01-25 Matsushita Electric Ind Co Ltd Semicondutor device and its manufacturing method
JP2007220809A (en) * 2006-02-15 2007-08-30 Toshiba Corp Semiconductor device and method of manufacturing same
JP2008311678A (en) * 2008-08-22 2008-12-25 Toshiba Corp Field effect transistor, integrated circuit element, and manufacturing method of them
JP2009016866A (en) * 2008-09-12 2009-01-22 Fujitsu Microelectronics Ltd Semiconductor device, and manufacturing method thereof
JP2009181977A (en) * 2008-01-29 2009-08-13 Toshiba Corp Semiconductor device and method of manufacturing semiconductor
JP2009182109A (en) * 2008-01-30 2009-08-13 Toshiba Corp Semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319348A (en) * 1989-06-16 1991-01-28 Fujitsu Ltd Manufacture of semiconductor device
JPH04280682A (en) * 1991-03-08 1992-10-06 Toshiba Corp Semiconductor device and manufacture thereof
JPH06350086A (en) * 1993-06-08 1994-12-22 Matsushita Electron Corp Manufacture of semiconductor device
JPH10270685A (en) * 1997-03-27 1998-10-09 Sony Corp Field-effect transistor and manufacture thereof, semiconductor device and manufacture thereof and logic circuit containing semiconductor device thereof and semiconductor substrate
JP2000077658A (en) * 1998-08-28 2000-03-14 Toshiba Corp Manufacture of semiconductor device
JP2004039762A (en) * 2002-07-01 2004-02-05 Toshiba Corp Field effect transistor and method of manufacturing the same
JP2004214457A (en) * 2003-01-06 2004-07-29 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2007500433A (en) * 2003-07-28 2007-01-11 インターナショナル・ビジネス・マシーンズ・コーポレーション Method of slowing dopant diffusion in a semiconductor substrate and device manufactured thereby
JP2006202951A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Mos-type field effect transistor and manufacturing method thereof
JP2007019314A (en) * 2005-07-08 2007-01-25 Matsushita Electric Ind Co Ltd Semicondutor device and its manufacturing method
JP2007220809A (en) * 2006-02-15 2007-08-30 Toshiba Corp Semiconductor device and method of manufacturing same
JP2009181977A (en) * 2008-01-29 2009-08-13 Toshiba Corp Semiconductor device and method of manufacturing semiconductor
JP2009182109A (en) * 2008-01-30 2009-08-13 Toshiba Corp Semiconductor device
JP2008311678A (en) * 2008-08-22 2008-12-25 Toshiba Corp Field effect transistor, integrated circuit element, and manufacturing method of them
JP2009016866A (en) * 2008-09-12 2009-01-22 Fujitsu Microelectronics Ltd Semiconductor device, and manufacturing method thereof

Also Published As

Publication number Publication date
JP2010267713A (en) 2010-11-25

Similar Documents

Publication Publication Date Title
US8994119B2 (en) Semiconductor device with gate stacks having stress and method of manufacturing the same
JP4938262B2 (en) Semiconductor device and manufacturing method thereof
US8404551B2 (en) Source/drain extension control for advanced transistors
WO2010137093A1 (en) Semiconductor device and method for manufacturing same
WO2012035679A1 (en) Semiconductor device and manufacturing method therefor
KR20020066191A (en) MOS FIELD-EFFECT TRANSISTOR COMPRISING LAYERED STRUCTURE INCLUDING Si LAYER AND SiGe LAYER OR SiGeC LAYER AS CHANNEL REGIONS
KR20130088134A (en) Advanced transistors with punch through suppression
US8497178B2 (en) Semiconductor device and method for making the same
US20110084315A1 (en) Semiconductor device having silicon on stressed liner (sol)
US8362522B2 (en) Semiconductor device and method for manufacturing the same
CN101431101A (en) Method for fabricating a semiconductor device
US8518784B2 (en) Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment
KR100861835B1 (en) Method for fabricating semiconductor for a dual gate cmos
US9331174B2 (en) Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe)
WO2011151945A1 (en) Semiconductor device and process for production thereof
US20140357028A1 (en) Methods for fabricating integrated circuits with the implantation of fluorine
JP2006005056A (en) Semiconductor device and its manufacturing method
WO2011077605A1 (en) Semiconductor device and process for production thereof
JP2014067958A (en) Semiconductor device, and method of manufacturing the same
WO2010131312A1 (en) Semiconductor device and method of producing same
WO2011052108A1 (en) Semiconductor device and method for manufacturing same
KR100539159B1 (en) Transistor in a semiconductor device and a method of manufacturing the same
WO2022133652A1 (en) Field effect-transistor and manufacturing method therefor
JP2006108251A (en) Manufacturing method of semiconductor device
JP2012248561A (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09844586

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09844586

Country of ref document: EP

Kind code of ref document: A1