WO2006105586A1 - A method for producing a multi component electronic module and a module produced by the method - Google Patents

A method for producing a multi component electronic module and a module produced by the method Download PDF

Info

Publication number
WO2006105586A1
WO2006105586A1 PCT/AU2006/000438 AU2006000438W WO2006105586A1 WO 2006105586 A1 WO2006105586 A1 WO 2006105586A1 AU 2006000438 W AU2006000438 W AU 2006000438W WO 2006105586 A1 WO2006105586 A1 WO 2006105586A1
Authority
WO
WIPO (PCT)
Prior art keywords
accordance
framework
components
integrated electronic
electronic module
Prior art date
Application number
PCT/AU2006/000438
Other languages
French (fr)
Inventor
John William Wiggins
Joanna Szymanska
Jeina Lazar
Val Dyadyuk
John William Archer
Oya Sevimli
Original Assignee
Commonwealth Scientific And Industrial Research Organisation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2005901655A external-priority patent/AU2005901655A0/en
Application filed by Commonwealth Scientific And Industrial Research Organisation filed Critical Commonwealth Scientific And Industrial Research Organisation
Publication of WO2006105586A1 publication Critical patent/WO2006105586A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • H01L2223/6633Transition between different waveguide types
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401Structure
    • H01L2224/24011Deposited, e.g. MCM-D type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616Cavity shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1903Structure including wave guides
    • H01L2924/19038Structure including wave guides being a hybrid line type
    • H01L2924/19039Structure including wave guides being a hybrid line type impedance transition between different types of wave guides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018Presence of a frame in a printed circuit or printed circuit assembly
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Definitions

  • the present invention relates to a method for producing a multi-component electronic module, and particularly, but not exclusively, to a method for integrating multiple electronic components into a single module which is particularly suited for applications in the 40GHz and above frequency range.
  • the present invention provides a method of manufacturing an integrated electronic module, comprising the step of providing a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration.
  • the framework may be made from a thermally conductive material, and/or from an electrically conductive material .
  • the method may include the further step of manufacturing the framework by etching openings into a sheet of metal .
  • the method may comprise the further steps of bonding the framework to a temporary carrier to facilitate the positioning of the components.
  • the temporary carrier may be provided with a layer of a thermoplastics material, whereby the framework is bonded to the layer of thermoplastics material. Furthermore, after inserting the components into the openings provided in the framework, the framework and the components may be coated with an electrically conductive material to form a common ground connection for all the components. In one embodiment the total surface area of the openings is minimised to minimise the volume of the electrically conductive material required to avoid unnecessary structural stress.
  • the method may include the further step of processing the module to produce a flat surface .
  • the temporary carrier layer may be removed and a dielectric material may be coated in place of the removed temporary carrier.
  • a pattern may be etched into the dielectric layer, the pattern defining the via hole electrical connections to the components. ' Once the pattern is etched into the dielectric layer, a conductive material may be provided into the etched area and onto the dielectric. The conductive material is patterned to create an electrically conductive interconnection between the components.
  • the method may comprise the further step of inserting at least one sacrificial component in the at least one opening, whereby the sacrificial component is removable to define a waveguide cavity.
  • the at least one sacrificial component may be of a dimension whereby the step of processing the module to provide a flat surface causes the sacrificial component to be exposed to facilitate removal (by etching) of the sacrificial component.
  • the temporary carrier may be made from a Silicon Aluminium alloy that has a thermal coefficient substantially similar to the thermal coefficient of the framework, and the framework may be formed from a material having a thermal coefficient substantially similar to the thermal coefficient of the electronic components.
  • the framework may be made from one of copper or copper molybdenum.
  • the components may be GaAs, SiGe or other devices.
  • the present invention provides an integrated electronic module when manufactured in accordance with a first aspect of the invention.
  • the present invention provides an integrated electronic module comprising a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration .
  • the present invention provides a wafer comprising a plurality of integrated electronic modules in accordance with a third aspect of the invention.
  • the present invention provides an electronic device including an integrated electronic module in accordance with a third aspect of the invention.
  • the present invention provides a method of manufacturing a plurality of integrated electronic modules comprising the steps of providing a wafer capable of containing a plurality of frameworks, each framework being usable to form an integrated electronic module, each framework further comprising openings arranged to receive components and locate the components in a predefined configuration.
  • Figures 1 to 15 are illustrations of the method steps carried out when manufacturing a multi-component module in accordance with an embodiment of the present invention
  • Figure 16 depicts a top view of a multi-component module produced in accordance with an embodiment of the present invention.
  • Figure 17 depicts a top view of a wafer containing a plurality of multi-component modules in accordance with an embodiment of the present invention.
  • a Si/Al temporary carrier 10 that has a matching temperature coefficient to a conductive framework ( Figure 3) .
  • the temporary carrier 10 is coated with approximately 14 ⁇ m (or other thickness) of a thermoplastic material 12 ( Figure 2) .
  • the coating of thermoplastic material 12 serves as a base onto which there is temporarily fixed to a framework.
  • the framework is a copper sheet 14 ( Figure 3) .
  • the framework 14 is sized to hold a number of components which may include active and passive chips, waveguides, antennas, via-holes, air-bridges, thin film capacitors, resistors or any other component which may be formed or placed in a module.
  • the framework 14 is thicker than the thickest chip that will be placed into the multi-component module.
  • the framework is 250 ⁇ m thick.
  • the framework may preferably be made of any electrically and/or thermally conductive material such as copper or copper molybdenum.
  • the framework will preferably have a matching temperature coefficient to GaAs, InP, SiGe or Si, which may be the materials from which most semi-conductor components are manufactured for electronics which operate in the frequency range of 40 GHz and above.
  • the framework should preferably have thermal properties similar to the thermal properties of the components which form part of the module. It will be understood that for high power operation or any other extreme ambient temperature operation such as cryogenic operation, copper molybdenum or similar thermally matched conductive material may be utilised in place of a simple copper framework.
  • openings 16 may be patterned and subsequently etched into the framework, to allow for the insertion of components ( Figure 4) . Openings 18, which may subsequently be used to form waveguide connections, may also be etched into the stencil at this time.
  • components 20 are placed in an "up side down" configuration into the openings using a flip-chip bonder or any other equipment that is suitable for aligning and thermally bonding up-side-down components ( Figure 5) .
  • a sacrificial chip 22 is placed in the opening for the waveguide connection 18.
  • the sacrificial chip is of the same dimensions as the desired waveguide port 42, although it is slightly thicker than the framework 14, such that it protrudes beyond the framework 14.
  • ground metal 24 is sputtered over framework 14, and components 20 and sacrificial chip 22 ( Figure 6) .
  • ground metal 26 is also subsequently plated over sputtered ground metal 24 ( Figure 7) .
  • the sputtering and plating process generally produces a stepped surface 28, due to the varying heights of the modules 20 and chips 22.
  • the stepped surface 28 is turned into a substantially flat surface by filling in the gaps in the stepped surface with a conductive epoxy (such as Epotek TM H20E) 30, and the resulting module is then lapped to produce a flat top surface 32 ( Figure 8) . If a sacrificial chip 22 is fitted, the lapping exposes the upper surface of the sacrificial chip 22, so that the sacrificial chip 22 may be suitably removed, thereby creating a waveguide port.
  • a conductive epoxy such as Epotek TM H20E
  • the module may be turned, and the temporary carrier 10 (including the thermoplastics layer 12) may be removed from the framework 14, thereby exposing the "front" side of the module ( Figure 9) .
  • the exposed surface i.e. the surface which was bonded to the temporary carrier 10) is covered with a 10 ⁇ m (or other thickness) BCB (Benzocyclobutene) or other suitable dielectric 34.
  • BCB Benzocyclobutene
  • the dielectric layer 34 is applied utilising a spinning technique, followed by curing at a temperature of approximately 200 0 C.
  • the dielectric 34 may be applied to any appropriate thickness, which may vary depending on application ( Figure 10) .
  • holes 36 may be patterned and etched into the dielectric 34 ( Figure 11) .
  • 3 ⁇ m (or other thickness) of metal 38 is sputtered over the whole face of the dielectric 34 to form connections to the components ( Figure 12) .
  • the metal 38 can also be patterned and etched to form the inter component connections . It is possible to add additional layers of dielectric 34 and other materials to form additional connections and/or components (such as thin film capacitors, resistors or antennas) 40 ( Figure 14) .
  • the sacrificial chip 22, if fitted, may be etched away to form a waveguide connection 42 with smooth walls ( Figure 15) .
  • Figure 16 depicts an example of a completed multi-chip module, highlighting the positioning of each of the major components, including the provision of connectors 44 which may be utilised to interface and connect to other electronic modules, and the provision of a waveguide probe 46, which is an input/output device from the waveguide to the other components on the multi-chip module.
  • the completed multi-chip module may be incorporated into another device, such as an electronic communications device, via the connectors 44.
  • Figure 17 illustrates a plurality of multi-chip modules when manufactured on a wafer. It will be appreciated that a plurality of multi-chip modules may be produced simultaneously on a single wafer utilising the method described herein.
  • the resulting multi-component module is suitable for high frequency applications (frequencies over 40 GHz) , since the active and passive components are provided with a continuous ground (metallised) connection at the back (bottom) of the module, and a signal (metallised) connection at the front (top) of the module that can be designed using standard printed transmission line techniques.
  • a good electrical connection to the back of each component is desirable for components that are designed for high frequency operation.
  • a good thermal connection is also provided, which in turn provides for better heat transfer and hence an improved lifetime of the module. Furthermore, by providing a framework which is thicker than all components (other than sacrificial chips) , it is possible to create a module which can integrate components that have different thicknesses and that are made from different materials.
  • a framework also provides rigidity to the module as a whole and reduces stress in the module.
  • the total area of openings provided for components will be kept to a minimum, to minimise the structural stress in the conductive filling material and to ensure that a certain level of rigidity is retained in the module.
  • the inter-chip connections can have several layers of metallisation.
  • other components such as via-holes, air-bridges, thin film capacitors, resistors, antennas and other suitable passive components can be made during the module manufacturing process to form a complete high frequency module.
  • a copper framework or a framework made out of other electrically and thermally conductive material such as copper molybdenum, is used.
  • any material that has a temperature coefficient similar to the material of the chips and electronic components that are being integrated may be utilised to surround the components and form part of the final package of the module.
  • a copper or copper molybdenum framework is convenient as a final carrier, as it can support waveguide, coaxial or other connections to the electronic module .
  • Waveguide holes above 40 GHz require smooth walls, which are provided in at least a specific embodiment of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A method of manufacturing an integrated electronic module, comprising the step of providing a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration.

Description

A METHOD FOR PRODUCING A MULTI COMPONENT ELECTRONIC MODULE AND A MODULE PRODUCED BY THE METHOD
FIELD OF THE INVENTION
The present invention relates to a method for producing a multi-component electronic module, and particularly, but not exclusively, to a method for integrating multiple electronic components into a single module which is particularly suited for applications in the 40GHz and above frequency range.
BACKGROUND OF THE INVENTION
Conventional multi-component integration into a single module, particularly for modules which are arranged to operate with signal frequencies of 40GHz and above, is a time consuming and expensive process, since conventional manufacturing techniques require the components (such as chips) to be placed into a metal package and then wire-bonded to each other to form connections. Moreover, the connections formed by wire-bonding do not function as correct transmission lines at high frequencies and may cause loss of the electrical signal. Another method utilised to produce multi-component modules is to "flip-chip" the active chips into a carrier to avoid wire-bonding. This method has disadvantages, as there are inherent difficulties in modelling up-side-down chips for applications in the frequency range above 40 GHz. Structural problems may also arise when the chips are in a vibrating environment, including problems with heat transfer. SUMMARY OF THE INVENTION
In a first aspect, the present invention provides a method of manufacturing an integrated electronic module, comprising the step of providing a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration.
In one form, the framework may be made from a thermally conductive material, and/or from an electrically conductive material .
In one form, the method may include the further step of manufacturing the framework by etching openings into a sheet of metal . The method may comprise the further steps of bonding the framework to a temporary carrier to facilitate the positioning of the components.
The temporary carrier may be provided with a layer of a thermoplastics material, whereby the framework is bonded to the layer of thermoplastics material. Furthermore, after inserting the components into the openings provided in the framework, the framework and the components may be coated with an electrically conductive material to form a common ground connection for all the components. In one embodiment the total surface area of the openings is minimised to minimise the volume of the electrically conductive material required to avoid unnecessary structural stress.
After applying the electrically conductive coating, the method may include the further step of processing the module to produce a flat surface .
The temporary carrier layer may be removed and a dielectric material may be coated in place of the removed temporary carrier. A pattern may be etched into the dielectric layer, the pattern defining the via hole electrical connections to the components. ' Once the pattern is etched into the dielectric layer, a conductive material may be provided into the etched area and onto the dielectric. The conductive material is patterned to create an electrically conductive interconnection between the components.
In one form, the method may comprise the further step of inserting at least one sacrificial component in the at least one opening, whereby the sacrificial component is removable to define a waveguide cavity. In particular, the at least one sacrificial component may be of a dimension whereby the step of processing the module to provide a flat surface causes the sacrificial component to be exposed to facilitate removal (by etching) of the sacrificial component. The temporary carrier may be made from a Silicon Aluminium alloy that has a thermal coefficient substantially similar to the thermal coefficient of the framework, and the framework may be formed from a material having a thermal coefficient substantially similar to the thermal coefficient of the electronic components. In a particular embodiment, the framework may be made from one of copper or copper molybdenum. The components may be GaAs, SiGe or other devices.
In a second aspect, the present invention provides an integrated electronic module when manufactured in accordance with a first aspect of the invention.
In a third aspect, the present invention provides an integrated electronic module comprising a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration .
In a fourth aspect, the present invention provides a wafer comprising a plurality of integrated electronic modules in accordance with a third aspect of the invention. In a fifth aspect, the present invention provides an electronic device including an integrated electronic module in accordance with a third aspect of the invention.
In a sixth aspect, the present invention provides a method of manufacturing a plurality of integrated electronic modules comprising the steps of providing a wafer capable of containing a plurality of frameworks, each framework being usable to form an integrated electronic module, each framework further comprising openings arranged to receive components and locate the components in a predefined configuration.
DETAILED DESCRIPTION OF THE DRAWINGS
Further features of an embodiment of the present invention will now be described, by way of example only, with reference to the following figures in which:
Figures 1 to 15 are illustrations of the method steps carried out when manufacturing a multi-component module in accordance with an embodiment of the present invention;
Figure 16 depicts a top view of a multi-component module produced in accordance with an embodiment of the present invention; and
Figure 17 depicts a top view of a wafer containing a plurality of multi-component modules in accordance with an embodiment of the present invention.
DESCRIPTION OF AN EMBODIMENT
Referring to Figures 1 through 15, there is described a series of method steps for manufacturing a multi-component module in accordance with an embodiment of the present invention.
At Figure 1, there is shown a Si/Al temporary carrier 10 that has a matching temperature coefficient to a conductive framework (Figure 3) . The temporary carrier 10 is coated with approximately 14 μm (or other thickness) of a thermoplastic material 12 (Figure 2) . The coating of thermoplastic material 12 serves as a base onto which there is temporarily fixed to a framework. In the specific embodiment disclosed herein, the framework is a copper sheet 14 (Figure 3) . The framework 14 is sized to hold a number of components which may include active and passive chips, waveguides, antennas, via-holes, air-bridges, thin film capacitors, resistors or any other component which may be formed or placed in a module. In the embodiment described, the framework 14 is thicker than the thickest chip that will be placed into the multi-component module. In the example given, the framework is 250 μm thick. The framework may preferably be made of any electrically and/or thermally conductive material such as copper or copper molybdenum. Moreover, in the embodiment described the framework will preferably have a matching temperature coefficient to GaAs, InP, SiGe or Si, which may be the materials from which most semi-conductor components are manufactured for electronics which operate in the frequency range of 40 GHz and above. In other words, the framework should preferably have thermal properties similar to the thermal properties of the components which form part of the module. It will be understood that for high power operation or any other extreme ambient temperature operation such as cryogenic operation, copper molybdenum or similar thermally matched conductive material may be utilised in place of a simple copper framework.
Once the framework 14 has been fixed to the temporary carrier 10, openings 16 may be patterned and subsequently etched into the framework, to allow for the insertion of components (Figure 4) . Openings 18, which may subsequently be used to form waveguide connections, may also be etched into the stencil at this time. Once the openings 16 and 18 have been etched into the framework 14, components 20 are placed in an "up side down" configuration into the openings using a flip-chip bonder or any other equipment that is suitable for aligning and thermally bonding up-side-down components (Figure 5) .
Where a waveguide connection 18 is required, a sacrificial chip 22 is placed in the opening for the waveguide connection 18. The sacrificial chip is of the same dimensions as the desired waveguide port 42, although it is slightly thicker than the framework 14, such that it protrudes beyond the framework 14.
Once all components 20 and sacrificial chips 22 have been placed into the openings in the framework 14 , ground metal 24 is sputtered over framework 14, and components 20 and sacrificial chip 22 (Figure 6) . In addition, ground metal 26 is also subsequently plated over sputtered ground metal 24 (Figure 7) .
The sputtering and plating process generally produces a stepped surface 28, due to the varying heights of the modules 20 and chips 22. The stepped surface 28 is turned into a substantially flat surface by filling in the gaps in the stepped surface with a conductive epoxy (such as Epotek TM H20E) 30, and the resulting module is then lapped to produce a flat top surface 32 (Figure 8) . If a sacrificial chip 22 is fitted, the lapping exposes the upper surface of the sacrificial chip 22, so that the sacrificial chip 22 may be suitably removed, thereby creating a waveguide port. Once the surface is lapped flat, the module may be turned, and the temporary carrier 10 (including the thermoplastics layer 12) may be removed from the framework 14, thereby exposing the "front" side of the module (Figure 9) . The exposed surface (i.e. the surface which was bonded to the temporary carrier 10) is covered with a 10 μm (or other thickness) BCB (Benzocyclobutene) or other suitable dielectric 34. The dielectric layer 34 is applied utilising a spinning technique, followed by curing at a temperature of approximately 2000C. The dielectric 34 may be applied to any appropriate thickness, which may vary depending on application (Figure 10) .
Once the dielectric 34 is applied, holes 36 may be patterned and etched into the dielectric 34 (Figure 11) . Once the holes 36 are etched, 3 μm (or other thickness) of metal 38 is sputtered over the whole face of the dielectric 34 to form connections to the components (Figure 12) . As can be seen in Figure 13, the metal 38 can also be patterned and etched to form the inter component connections . It is possible to add additional layers of dielectric 34 and other materials to form additional connections and/or components (such as thin film capacitors, resistors or antennas) 40 (Figure 14) .
Furthermore, the sacrificial chip 22, if fitted, may be etched away to form a waveguide connection 42 with smooth walls (Figure 15) .
Figure 16 depicts an example of a completed multi-chip module, highlighting the positioning of each of the major components, including the provision of connectors 44 which may be utilised to interface and connect to other electronic modules, and the provision of a waveguide probe 46, which is an input/output device from the waveguide to the other components on the multi-chip module. The completed multi-chip module may be incorporated into another device, such as an electronic communications device, via the connectors 44.
Figure 17 illustrates a plurality of multi-chip modules when manufactured on a wafer. It will be appreciated that a plurality of multi-chip modules may be produced simultaneously on a single wafer utilising the method described herein. The resulting multi-component module is suitable for high frequency applications (frequencies over 40 GHz) , since the active and passive components are provided with a continuous ground (metallised) connection at the back (bottom) of the module, and a signal (metallised) connection at the front (top) of the module that can be designed using standard printed transmission line techniques. A good electrical connection to the back of each component is desirable for components that are designed for high frequency operation.
A good thermal connection is also provided, which in turn provides for better heat transfer and hence an improved lifetime of the module. Furthermore, by providing a framework which is thicker than all components (other than sacrificial chips) , it is possible to create a module which can integrate components that have different thicknesses and that are made from different materials.
The use of a framework also provides rigidity to the module as a whole and reduces stress in the module. Generally, the total area of openings provided for components will be kept to a minimum, to minimise the structural stress in the conductive filling material and to ensure that a certain level of rigidity is retained in the module. It will 'be understood that the inter-chip connections can have several layers of metallisation. In addition, other components such as via-holes, air-bridges, thin film capacitors, resistors, antennas and other suitable passive components can be made during the module manufacturing process to form a complete high frequency module.
It will be further understood that in a particular embodiment, a copper framework, or a framework made out of other electrically and thermally conductive material such as copper molybdenum, is used. However, any material that has a temperature coefficient similar to the material of the chips and electronic components that are being integrated may be utilised to surround the components and form part of the final package of the module.
In the particular embodiment described herein, a copper or copper molybdenum framework is convenient as a final carrier, as it can support waveguide, coaxial or other connections to the electronic module . Waveguide holes above 40 GHz require smooth walls, which are provided in at least a specific embodiment of the present invention. It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Claims

CLAIMS :
1. A method of manufacturing an integrated electronic module, comprising the step of providing a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration.
2. A method in accordance with Claim 1 comprising the further step of providing a framework made from a thermally conductive material.
3. A method in accordance with Claim 1 or 2 , comprising the further step of providing a framework made from an electrically conductive material .
4. A method in accordance with any one of Claims 1, 2 or 3 , whereby the total surface area of the openings and the total volume of the conductive filler are kept to a minimum to prevent structural stress in the conductive material .
5. A method in accordance with any one of Claims 1 to 4 , comprising the further step of manufacturing the framework by etching openings into a sheet of material.
6. A method in accordance with any one of Claims 1 to 5, comprising the further step of bonding the framework to a temporary carrier to facilitate the positioning of the components.
7. A method in accordance with Claim 6, comprising the further step of providing the temporary carrier with a layer of a thermoplastics material, whereby the framework is bonded to the layer of thermoplastics material.
8. A method in accordance with any one of Claims 1 to 7, comprising the further step of, after inserting the components into the openings provided in the framework, coating the framework and the components with an electrically conductive material to form a common ground connection for all the components .
9. A method in accordance with Claim 8 , wherein the total surface area of the openings is minimised to minimise the volume of the electrically conductive material required to avoid unnecessary structural stress.
10. A method in accordance with Claim 8 or Claim 9, comprising the further step of processing the module to produce a flat surface.
11. A method in accordance with Claim 9 or Claim 10, comprising the further step of removing the temporary carrier layer and depositing a dielectric material in place of the removed temporary carrier.
12. A method in accordance with Claim 11, comprising the further step of etching a pattern into the dielectric layer, the pattern defining the via-hole-connections to the components.
13. A method in accordance with Claim 12, comprising the further step of coating a conducting layer onto the dielectric layer and patterning the conductive layer to create an electric interconnection between the components.
14. A method in accordance with any one of Claims 1 to 13, comprising the further step of providing at least one sacrificial component in the at least one opening, whereby the sacrificial component is removable to define a waveguide cavity.
15. A method in accordance with Claim 14 , whereby the at least one sacrificial component is of a dimension whereby the step of processing the module to provide a flat surface causes the sacrificial component to be exposed to facilitate removal of the sacrificial component.
16. A method in accordance with any one of the preceding claims, whereby the temporary carrier is made from a Silicon Aluminium or other alloy.
17. A method in accordance with any one of the preceding claims, whereby the framework is formed from a material having a thermal coefficient substantially similar to the thermal coefficient of the electronic components.
18. A method in accordance with any one of the preceding claims, whereby the framework is made from one of copper or copper molybdenum.
19. A method in accordance with any one of the preceding claims, whereby the components are one of GaAs or SiGe devices .
20. An integrated electronic module when manufactured in accordance with any one of Claims 1 to 19.
21. An integrated electronic module comprising a framework with openings arranged to receive components, the openings being arranged to locate the components in a predefined configuration.
22. An integrated electronic module in accordance with Claim 21 wherein the framework is made from a thermally conductive material.
23. An integrated electronic module in accordance with Claim 21 or 22, wherein the framework is made from an electrically conductive material.
24. An integrated electronic module in accordance with any one of Claims 21, 22 or 23, wherein the total surface area of the openings and the total volume of the conductive filler are kept to a minimum to prevent structural stress in the conductive material .
25. An integrated electronic module in accordance with any one of Claims 21 to 24, wherein the framework and the components are coated with an electrically conductive material to form a common ground connection for all the components.
26. An integrated electronic module in accordance with Claim 25, wherein the total surface area of the openings and the total volume of the electrically conductive material is minimised to optimise the structural stress in the conductive material.
27. An integrated electronic module in accordance with any one of Claims 21 to 26, comprising at least one sacrificial component in the at least one opening, wherein the sacrificial component is removable to define a waveguide cavity .
28. An integrated electronic module in accordance with any one of Claims 21 to 27, wherein the temporary carrier is made from a Silicon Aluminium or other alloy that has thermal properties substantially similar to the framework.
29. An integrated electronic module in accordance with any one of Claims 21 to 28, wherein the framework is formed from a material having a thermal coefficient substantially similar to the thermal coefficient of the electronic components.
30. An integrated electronic module in accordance with any one of Claims 21 to 29, wherein the framework is made from one of copper or copper molybdenum.
31. An integrated electronic module in accordance with any one of Claims 21 to 30, wherein the components are one of GaAs or SiGe devices.
32. A wafer comprising a plurality of integrated electronic modules in accordance with any one of Claims 21 to 31.
33. An electronic device including an integrated electronic module in accordance with any one of Claims 21 to 31.
34. A method of manufacturing a plurality of integrated electronic modules comprising the steps of providing a wafer capable of containing a plurality of frameworks, each framework being usable to form an integrated electronic module, each framework further comprising openings arranged to receive components and locate the components in a predefined configuration.
PCT/AU2006/000438 2005-04-04 2006-04-04 A method for producing a multi component electronic module and a module produced by the method WO2006105586A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2005901655 2005-04-04
AU2005901655A AU2005901655A0 (en) 2005-04-04 A method for producing a multi component electronic module and a module produced by the method

Publications (1)

Publication Number Publication Date
WO2006105586A1 true WO2006105586A1 (en) 2006-10-12

Family

ID=37073007

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AU2006/000438 WO2006105586A1 (en) 2005-04-04 2006-04-04 A method for producing a multi component electronic module and a module produced by the method

Country Status (1)

Country Link
WO (1) WO2006105586A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008137511A1 (en) * 2007-05-04 2008-11-13 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
WO2010040398A1 (en) * 2008-10-08 2010-04-15 Telefonaktiebolaget L M Ericsson (Publ) Chip interconnection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1087434A2 (en) * 1999-09-22 2001-03-28 Nec Corporation Semiconductor device of the flip-chip type and method for manufacturing same
FR2818804A1 (en) * 2000-12-21 2002-06-28 Thomson Csf Multichip module production involves covering a substrate and mounted components with resin and removing substrate to expose resin surface and surfaces of components with revealed mounting lands
US20040017668A1 (en) * 2002-07-26 2004-01-29 Stmicroelectronics, Inc. Leadframeless package structure and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1087434A2 (en) * 1999-09-22 2001-03-28 Nec Corporation Semiconductor device of the flip-chip type and method for manufacturing same
FR2818804A1 (en) * 2000-12-21 2002-06-28 Thomson Csf Multichip module production involves covering a substrate and mounted components with resin and removing substrate to expose resin surface and surfaces of components with revealed mounting lands
US20040017668A1 (en) * 2002-07-26 2004-01-29 Stmicroelectronics, Inc. Leadframeless package structure and method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008137511A1 (en) * 2007-05-04 2008-11-13 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
US8097526B2 (en) 2007-05-04 2012-01-17 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
US8569879B2 (en) 2007-05-04 2013-10-29 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
TWI473237B (en) * 2007-05-04 2015-02-11 Crossfire Technologies Inc Accessing or interconnecting integrated circuits
US8958227B2 (en) 2007-05-04 2015-02-17 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
US9449952B2 (en) 2007-05-04 2016-09-20 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
US9837129B2 (en) 2007-05-04 2017-12-05 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
WO2010040398A1 (en) * 2008-10-08 2010-04-15 Telefonaktiebolaget L M Ericsson (Publ) Chip interconnection

Similar Documents

Publication Publication Date Title
US6025995A (en) Integrated circuit module and method
US6562660B1 (en) Method of manufacturing the circuit device and circuit device
US5373627A (en) Method of forming multi-chip module with high density interconnections
US8471361B2 (en) Integrated chip package structure using organic substrate and method of manufacturing the same
US7843056B2 (en) Integrated circuit micro-module
US9030029B2 (en) Chip package with die and substrate
US7902661B2 (en) Integrated circuit micro-module
US5571754A (en) Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack
US7135780B2 (en) Semiconductor substrate for build-up packages
US7842544B2 (en) Integrated circuit micro-module
US7901981B2 (en) Integrated circuit micro-module
US9761547B1 (en) Crystalline tile
US20110309473A1 (en) Chip package with die and substrate
US20090065951A1 (en) Stacked die package
US7898068B2 (en) Integrated circuit micro-module
US7901984B2 (en) Integrated circuit micro-module
CN111199957A (en) Three-dimensional packaging structure integrating chip and antenna and preparation method thereof
US5376574A (en) Capped modular microwave integrated circuit and method of making same
WO2006105586A1 (en) A method for producing a multi component electronic module and a module produced by the method
Nieweglowski et al. Interconnect Technology Development for 180GHz Wireless mm-Wave System-in-Foil Transceivers
Carrillo-Ramirez et al. A technique for interconnecting millimeter wave integrated circuits using BCB and bump bonds
US6706624B1 (en) Method for making multichip module substrates by encapsulating electrical conductors
KR100631509B1 (en) Module package of semi-conductor device and method of fabricating the same
US20230178500A1 (en) Waveguide Launcher in Package Based on High Dielectric Constant Carrier
US11862584B2 (en) High dielectric constant carrier based packaging with enhanced WG matching for 5G and 6G applications

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

NENP Non-entry into the national phase

Ref country code: RU

WWW Wipo information: withdrawn in national office

Country of ref document: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06721320

Country of ref document: EP

Kind code of ref document: A1

WWW Wipo information: withdrawn in national office

Ref document number: 6721320

Country of ref document: EP