US20010012672A1 - Method of forming CMOS integrated circuitry - Google Patents

Method of forming CMOS integrated circuitry Download PDF

Info

Publication number
US20010012672A1
US20010012672A1 US09/832,447 US83244701A US2001012672A1 US 20010012672 A1 US20010012672 A1 US 20010012672A1 US 83244701 A US83244701 A US 83244701A US 2001012672 A1 US2001012672 A1 US 2001012672A1
Authority
US
United States
Prior art keywords
substrate area
nmos
conducted
pmos
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/832,447
Other versions
US6358787B2 (en
Inventor
Charles Dennison
Mark Helm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/503,419 external-priority patent/US5534449A/en
Application filed by Individual filed Critical Individual
Priority to US09/832,447 priority Critical patent/US6358787B2/en
Publication of US20010012672A1 publication Critical patent/US20010012672A1/en
Application granted granted Critical
Publication of US6358787B2 publication Critical patent/US6358787B2/en
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components

Definitions

  • This invention relates to methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry, and to methods of forming field effect transistors.
  • CMOS complementary metal oxide semiconductor
  • MOS metal-oxide-semiconductor
  • An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
  • CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
  • NMOS n-type transistor
  • PMOS p-type transistor
  • NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
  • CMOS fabrication does however present a number of challenges to the fabricator as compared to using PMOS or NMOS alone. Specifically, typically independent or separate masking steps are utilized for masking one of the p-type regions while the n-type region is being doped. Also, the n-type regions are separately masked when the p-type regions are being doped. Accordingly, typical transistor flows use one mask each to form the n-channel and p-channel transistor source and drain regions. Higher levels of integration result in denser and denser circuits, leading CMOS fabrication to more difficulties.
  • FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.
  • FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.
  • FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2.
  • FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3.
  • FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 4.
  • a method of forming CMOS memory integrated circuitry comprises the following steps:
  • gate lines comprising memory array gate lines and peripheral circuitry gate lines, a first gate line being positioned relative to a first peripheral area of the substrate for formation of a peripheral NMOS transistor, a second gate line being positioned relative to a second peripheral area of the substrate for formation of a peripheral PMOS transistor, a third gate line being positioned relative to a memory array area of the substrate for formation of a memory array NMOS transistor;
  • a method of forming CMOS integrated circuitry comprises the following steps:
  • FIG. 1 illustrates portions of a semiconductor wafer fragment in process indicated generally with reference numeral 10 .
  • a semiconductor wafer fragment in process indicated generally with reference numeral 10 .
  • Such comprises a bulk silicon substrate 12 which is intrinsically p-doped, with a portion 14 thereof being subsequently n-doped to define an n-well.
  • a series of gate lines are provided over semiconductor substrate 12 .
  • the discussion proceeds with reference to preferred formation of CMOS memory integrated circuitry, with some of the gate lines comprising memory array gate lines and other of the gate lines constituting peripheral circuitry gate lines.
  • a first gate line 16 is positioned relative to a first peripheral area 18 of substrate 12 for formation of a peripheral NMOS transistor.
  • a second gate line 20 is positioned relative to a second peripheral area 22 of substrate 12 and n-well 14 for formation of a peripheral PMOS transistor.
  • a third gate line 24 is positioned relative to a memory array area 26 for formation of a memory array NMOS transistor.
  • Typical preferred present day cross sectional widths for gates 24 , 16 and 20 are 0.40 micron, 0.42 micron, and 0.55 micron, respectively.
  • the desired relationships are that the cross sectional widths of the n-channel periphery gates be greater than or equal to the memory array n-channel gates, with the p-channel peripheral gates being wider than both.
  • the respective gate lines include a gate oxide layer 28 , a conductive polysilicon layer 30 , an overlying WSi x layer 32 , an overlying novellus oxide layer 34 , and a Si 3 N 4 capping layer 36 .
  • a photoresist masking layer 38 is provided over second gate line 20 , second peripheral PMOS substrate area 22 , third gate line 24 , and memory array NMOS substrate area 26 .
  • An n-type LDD implant 42 preferably As, is then provided into the exposed first peripheral NMOS substrate area 18 adjacent first gate line 16 .
  • An example and preferred average concentration of As for regions 42 is 8 ⁇ 10 18 ions/cm 3 .
  • An example depth for the peak concentration is 400 Angstroms.
  • a p-type halo ion implant is subsequently conducted into the exposed first peripheral NMOS substrate area 18 adjacent first gate line 16 , thus producing p-type halo ion implant regions 44 .
  • the p-type halo ion implant is conducted at a first energy level to provide a p-type first impurity concentration at a first depth within first peripheral NMOS substrate area 18 .
  • the depth is preferably conducted to be deeper than the maximum concentration depth of As LDD regions 42 .
  • An example and preferred p-type implant material is boron.
  • An example and preferred implant dose is 7 ⁇ 10 12 ions/cm 2 -1.5 ⁇ 10 13 ions/cm 2 to provide an example average dopant concentration of from 1 ⁇ 10 16 ions/cm 3 to 1 ⁇ 10 18 ions/cm 3 , with about 1 ⁇ 10 17 ions/cm 3 being preferred.
  • An example preferred implant energy is from 60 KeV to 100 KeV (70 KeV preferred) to provide a peak concentration implant depth of 2000 Angstroms.
  • the p-type halo implant is conducted as a series of implants angled from 0°, with an angle of about 30° from vertical (i.e., from 0°) being an example preferred angle.
  • a series of four 30° angled implants at 70 KeV at 90° wafer orientations using respective doses of 1.0 ⁇ 10 12 ions/cm 2 is a preferred implant sequence.
  • Such provides an advantage of desirably driving a portion of the halo implant beneath the gate.
  • masking layer 38 is removed and wafer fragment 10 is subjected to oxidizing conditions to form oxidized sidewalls 46 about the illustrated gate lines, and to form oxide 48 over exposed peripheral NMOS area 18 , peripheral PMOS area 22 , and memory array NMOS area 26 .
  • phosphorous is blanket ion implanted into exposed first peripheral NMOS substrate area 18 , second peripheral PMOS substrate area 22 , and memory array NMOS substrate area 26 adjacent the first, the second, and the third gate lines, respectively.
  • This forms peripheral NMOS transistor LDD regions 50 , peripheral PMOS transistor n-type halo regions 52 , and memory array NMOS transistor source/drain diffusion regions 54 .
  • the phosphorous implant is conducted at a second energy level to provide respective n-type second impurity concentrations at a second depth within the first, the second and the memory array substrate areas.
  • the first energy level and the first depth of implants 44 are chosen to be greater than the second energy level and the second depth, respectively, of the blanket phosphorus implant.
  • the implant energy difference between the p-type halo implant and the n-type blanket implant is greater than or equal to 10 KeV to provide the peak concentration of regions 44 at 1000 Angstroms below that of regions 50 .
  • An example energy level for the phosphorous implant is from 30 Kev to 60 KeV, with 30 KeV being preferred.
  • An example and desired dose is from 7 ⁇ 10 12 ions/cm 2 -1.5 ⁇ 10 13 ions/cm 2 to provide an example average dopant concentration of diffusion regions 50 , 52 and 54 of from 1 ⁇ 10 17 ions/cm 3 to 1 ⁇ 10 19 ions/cm 3 , with about 8 ⁇ 10 17 ions/cm 3 being preferred.
  • the above described sequence is the preferred order by which the respective implants occur.
  • the subject orders could be changed without departing from the principals and scope of the invention which is intended to be limited only by the accompanying claims appropriately interpreted in accordance the Doctrine of Equivalents.
  • the As LDD implant is conducted before the sidewall and substrate oxidations.
  • the p-type halo implant is preferably conducted either before or after such oxidations.
  • the blanket phosphorous implant is conducted after the sidewall and substrate oxidations.
  • oxide or nitride sidewall spacers 60 are provided about the illustrated respective gate lines. Thereafter, a photoresist masking layer 62 is provided and patterned to expose peripheral NMOS transistor area 18 and mask the illustrated array and p-channel periphery areas 22 and 26 . An n-type implant is thereafter conducted to provide n-type diffusion regions 64 for the peripheral NMOS transistors to essentially complete formation thereof.
  • the n-channel transistors are masked with a photoresist layer 66 , and ion implantation is conducted with a p-type material (i.e., boron) into the peripheral PMOS transistor to form desired p-type source/drain diffusion regions 68 .
  • a p-type material i.e., boron
  • P-type halo implant 44 is provided principally for improving/eliminating short channel effects in the peripheral n-channel transistors. Accordingly with respect to the above described preferred embodiment, the single masking step of FIG. 2 provides several advantageous functions.
  • the initial FIG. 2 doping enables provision of desired p-type n-channel halo implants 44 .
  • the subsequent blanket phosphorous implant provides the combination of a p-channel halo, a source/drain diffusion implant for the array, and reduction of n-channel periphery LDD resistance which is much more desirable for the NMOS peripheral transistors than for the NMOS array transistors. All FIGS. 2 and 3 implants are preferably conducted with the single FIG. 2 masking, whereas prior art methods use multiple masks to achieve the same implants.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.

Description

    TECHNICAL FIELD
  • This invention relates to methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry, and to methods of forming field effect transistors. [0001]
    • BACKGROUND OF THE INVENTION
  • An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. [0002]
  • CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons. [0003]
  • NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques. [0004]
  • CMOS fabrication does however present a number of challenges to the fabricator as compared to using PMOS or NMOS alone. Specifically, typically independent or separate masking steps are utilized for masking one of the p-type regions while the n-type region is being doped. Also, the n-type regions are separately masked when the p-type regions are being doped. Accordingly, typical transistor flows use one mask each to form the n-channel and p-channel transistor source and drain regions. Higher levels of integration result in denser and denser circuits, leading CMOS fabrication to more difficulties. [0005]
  • It would be desirable to develop methods which further facilitate formation of complementary source and drain regions within a semiconductor substrate. [0006]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0007]
  • FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention. [0008]
  • FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1. [0009]
  • FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2. [0010]
  • FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3. [0011]
  • FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 4. [0012]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” ([0013] Article 1, Section 8).
  • In accordance with one aspect of the invention, a method of forming CMOS memory integrated circuitry comprises the following steps: [0014]
  • providing a series of gate lines over a semiconductor substrate, the gate lines comprising memory array gate lines and peripheral circuitry gate lines, a first gate line being positioned relative to a first peripheral area of the substrate for formation of a peripheral NMOS transistor, a second gate line being positioned relative to a second peripheral area of the substrate for formation of a peripheral PMOS transistor, a third gate line being positioned relative to a memory array area of the substrate for formation of a memory array NMOS transistor; [0015]
  • masking the second gate line, the second peripheral PMOS substrate area, the third gate line and the memory array NMOS substrate area while conducting a p-type halo ion implant into the first peripheral NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the first peripheral NMOS substrate area; and [0016]
  • in a common step, blanket ion implanting phosphorus into the first peripheral NMOS substrate area, the second peripheral PMOS substrate area and the memory array NMOS substrate area adjacent the first, the second and the third gate lines to form peripheral NMOS transistor LDD regions, peripheral PMOS transistor n-type halo regions and memory array NMOS transistor source/drain diffusion regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within the first, the second and the memory array substrate areas, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. [0017]
  • In accordance with another aspect of the invention, a method of forming CMOS integrated circuitry comprises the following steps: [0018]
  • providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; [0019]
  • masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and [0020]
  • in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. [0021]
  • More particularly, FIG. 1 illustrates portions of a semiconductor wafer fragment in process indicated generally with [0022] reference numeral 10. Such comprises a bulk silicon substrate 12 which is intrinsically p-doped, with a portion 14 thereof being subsequently n-doped to define an n-well. A series of gate lines are provided over semiconductor substrate 12. The discussion proceeds with reference to preferred formation of CMOS memory integrated circuitry, with some of the gate lines comprising memory array gate lines and other of the gate lines constituting peripheral circuitry gate lines.
  • Specifically, a [0023] first gate line 16 is positioned relative to a first peripheral area 18 of substrate 12 for formation of a peripheral NMOS transistor. A second gate line 20 is positioned relative to a second peripheral area 22 of substrate 12 and n-well 14 for formation of a peripheral PMOS transistor. A third gate line 24 is positioned relative to a memory array area 26 for formation of a memory array NMOS transistor. Typical preferred present day cross sectional widths for gates 24, 16 and 20 are 0.40 micron, 0.42 micron, and 0.55 micron, respectively. In otherwords, the desired relationships are that the cross sectional widths of the n-channel periphery gates be greater than or equal to the memory array n-channel gates, with the p-channel peripheral gates being wider than both. The respective gate lines include a gate oxide layer 28, a conductive polysilicon layer 30, an overlying WSix layer 32, an overlying novellus oxide layer 34, and a Si3N4 capping layer 36.
  • Referring to FIG. 2, a [0024] photoresist masking layer 38 is provided over second gate line 20, second peripheral PMOS substrate area 22, third gate line 24, and memory array NMOS substrate area 26. An n-type LDD implant 42, preferably As, is then provided into the exposed first peripheral NMOS substrate area 18 adjacent first gate line 16. An example and preferred average concentration of As for regions 42 is 8×1018 ions/cm3. An example depth for the peak concentration is 400 Angstroms.
  • A p-type halo ion implant is subsequently conducted into the exposed first peripheral [0025] NMOS substrate area 18 adjacent first gate line 16, thus producing p-type halo ion implant regions 44. The p-type halo ion implant is conducted at a first energy level to provide a p-type first impurity concentration at a first depth within first peripheral NMOS substrate area 18. The depth is preferably conducted to be deeper than the maximum concentration depth of As LDD regions 42. An example and preferred p-type implant material is boron. An example and preferred implant dose is 7×1012 ions/cm2-1.5×1013 ions/cm2 to provide an example average dopant concentration of from 1×1016 ions/cm3 to 1×1018 ions/cm3, with about 1×1017 ions/cm3 being preferred. An example preferred implant energy is from 60 KeV to 100 KeV (70 KeV preferred) to provide a peak concentration implant depth of 2000 Angstroms. Most preferably, the p-type halo implant is conducted as a series of implants angled from 0°, with an angle of about 30° from vertical (i.e., from 0°) being an example preferred angle. For example, a series of four 30° angled implants at 70 KeV at 90° wafer orientations using respective doses of 1.0×1012 ions/cm2 is a preferred implant sequence. Such provides an advantage of desirably driving a portion of the halo implant beneath the gate.
  • Referring to FIG. 3, [0026] masking layer 38 is removed and wafer fragment 10 is subjected to oxidizing conditions to form oxidized sidewalls 46 about the illustrated gate lines, and to form oxide 48 over exposed peripheral NMOS area 18, peripheral PMOS area 22, and memory array NMOS area 26.
  • Thereafter and in a common step, phosphorous is blanket ion implanted into exposed first peripheral [0027] NMOS substrate area 18, second peripheral PMOS substrate area 22, and memory array NMOS substrate area 26 adjacent the first, the second, and the third gate lines, respectively. This forms peripheral NMOS transistor LDD regions 50, peripheral PMOS transistor n-type halo regions 52, and memory array NMOS transistor source/drain diffusion regions 54. The phosphorous implant is conducted at a second energy level to provide respective n-type second impurity concentrations at a second depth within the first, the second and the memory array substrate areas. The first energy level and the first depth of implants 44 are chosen to be greater than the second energy level and the second depth, respectively, of the blanket phosphorus implant. Most preferably, the implant energy difference between the p-type halo implant and the n-type blanket implant is greater than or equal to 10 KeV to provide the peak concentration of regions 44 at 1000 Angstroms below that of regions 50. An example energy level for the phosphorous implant is from 30 Kev to 60 KeV, with 30 KeV being preferred. An example and desired dose is from 7×1012 ions/cm2-1.5×1013 ions/cm2 to provide an example average dopant concentration of diffusion regions 50, 52 and 54 of from 1×1017 ions/cm3 to 1×1019 ions/cm3, with about 8×1017 ions/cm3 being preferred.
  • The above described sequence is the preferred order by which the respective implants occur. The subject orders could be changed without departing from the principals and scope of the invention which is intended to be limited only by the accompanying claims appropriately interpreted in accordance the Doctrine of Equivalents. Most preferably, the As LDD implant is conducted before the sidewall and substrate oxidations. The p-type halo implant is preferably conducted either before or after such oxidations. And, the greatest success was achieved where the blanket phosphorous implant is conducted after the sidewall and substrate oxidations. [0028]
  • Referring to FIG. 4, oxide or [0029] nitride sidewall spacers 60 are provided about the illustrated respective gate lines. Thereafter, a photoresist masking layer 62 is provided and patterned to expose peripheral NMOS transistor area 18 and mask the illustrated array and p- channel periphery areas 22 and 26. An n-type implant is thereafter conducted to provide n-type diffusion regions 64 for the peripheral NMOS transistors to essentially complete formation thereof.
  • Referring to FIG. 5, the n-channel transistors are masked with a [0030] photoresist layer 66, and ion implantation is conducted with a p-type material (i.e., boron) into the peripheral PMOS transistor to form desired p-type source/drain diffusion regions 68.
  • Most preferably, additional doping in the memory array area relative to source/[0031] drain diffusion regions 54 is not required or conducted.
  • P-[0032] type halo implant 44 is provided principally for improving/eliminating short channel effects in the peripheral n-channel transistors. Accordingly with respect to the above described preferred embodiment, the single masking step of FIG. 2 provides several advantageous functions. The initial FIG. 2 doping enables provision of desired p-type n-channel halo implants 44. The subsequent blanket phosphorous implant provides the combination of a p-channel halo, a source/drain diffusion implant for the array, and reduction of n-channel periphery LDD resistance which is much more desirable for the NMOS peripheral transistors than for the NMOS array transistors. All FIGS. 2 and 3 implants are preferably conducted with the single FIG. 2 masking, whereas prior art methods use multiple masks to achieve the same implants.
  • The above described embodiment was described principally with reference to formation of memory devices, such as DRAMs, that preferably utilized two different types of NMOS transistors and one type of PMOS transistors. The artisan will as well appreciate that the invention has application to non-memory devices including formation of three different transistor types. Further, the artisan will also appreciate applicability of the invention to formation of CMOS circuitry only incorporating one type of NMOS transistor and one type of PMOS transistor. [0033]
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0034]

Claims (33)

1. A method of forming CMOS integrated circuitry comprising the following steps:
providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor;
masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and
in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively.
2. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implant is conducted as a series of angled implants.
3. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implant is conducted as a series of angled implants, the angled implants being conducted at about 30° from vertical.
4. The method of forming CMOS integrated circuitry of
claim 1
 further comprising oxidizing sidewalls of the first gate line and the second gate line, and oxidizing the NMOS substrate area and the PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate area and PMOS substrate area oxidations.
5. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implanting step is conducted before the blanket ion implanting step.
6. The method of forming CMOS integrated circuitry of
claim 1
 further comprising oxidizing sidewalls of the first gate line and the second gate line, and oxidizing the NMOS substrate area and the PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate area and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
7. The method of forming CMOS integrated circuitry of
claim 1
 further comprising oxidizing sidewalls of the first gate line and the second gate line, and oxidizing the NMOS substrate area and the PMOS substrate area; the p-type halo implanting step being conducted before the sidewall, NMOS substrate area and PMOS substrate area oxidation; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate area and PMOS substrate area oxidations.
8. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implant is conducted as a series of angled implants, and
the p-type halo implanting step is conducted before the blanket ion implanting step.
9. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first gate line and the second gate line, and oxidizing the NMOS substrate area and the PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate area and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
10. The method of forming CMOS integrated circuitry of
claim 1
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first gate line and the second gate line, and oxidizing the NMOS substrate area and the PMOS substrate area; the p-type halo implanting step being conducted before the sidewall, NMOS substrate area and PMOS substrate area oxidation; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate area and PMOS substrate area oxidations.
11. CMOS integrated circuitry produced according to the process of
claim 1
.
12. A method of forming CMOS integrated circuitry comprising the following steps:
providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to a first area of the substrate for formation of a first NMOS transistor, a second gate line being positioned relative to a second area of the substrate for formation of a PMOS transistor, a third gate line being positioned relative to a third area of the substrate for formation of a second NMOS transistor;
masking the second gate line, the second PMOS substrate area, the third gate line and the third NMOS substrate area while conducting a p-type halo ion implant into the first NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the first NMOS substrate area; and
in a common step, blanket ion implanting phosphorus into the first NMOS substrate area, the second PMOS substrate area and the third NMOS substrate area adjacent the first, the second and the third gate lines to form first NMOS transistor LDD regions, second PMOS transistor n-type halo regions and second NMOS transistor source/drain diffusion regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within the first, the second and the third substrate areas, the first energy level and the first depth being greater than the second energy level and the second depth, respectively.
13. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implant is conducted as a series of angled implants.
14. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implant is conducted as a series of angled implants, the angled implants being conducted at about 30° from vertical.
15. The method of forming CMOS integrated circuitry of
claim 12
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first and third NMOS substrate areas and the second PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
16. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implanting step is conducted before the blanket ion implanting step.
17. The method of forming CMOS integrated circuitry of
claim 12
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first and third NMOS substrate areas and the second PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
18. The method of forming CMOS integrated circuitry of
claim 12
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first and third NMOS substrate areas and the second PMOS substrate area; the p-type halo implanting step being conducted before the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
19. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implant is conducted as a series of angled implants, and
the p-type halo implanting step is conducted before the blanket ion implanting step.
20. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first and third NMOS substrate areas and the second PMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
21. The method of forming CMOS integrated circuitry of
claim 12
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first and third NMOS substrate areas and the second PMOS substrate area; the p-type halo implanting step being conducted before the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
22. CMOS integrated circuitry produced according to the process of
claim 12
.
23. A method of forming CMOS memory integrated circuitry comprising the following steps:
providing a series of gate lines over a semiconductor substrate, the gate lines comprising memory array gate lines and peripheral circuitry gate lines, a first gate line being positioned relative to a first peripheral area of the substrate for formation of a peripheral NMOS transistor, a second gate line being positioned relative to a second peripheral area of the substrate for formation of a peripheral PMOS transistor, a third gate line being positioned relative to a memory array area of the substrate for formation of a memory array NMOS transistor;
masking the second gate line, the second peripheral PMOS substrate area, the third gate line and the memory array NMOS substrate area while conducting a p-type halo ion implant into the first peripheral NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the first peripheral NMOS substrate area; and
in a common step, blanket ion implanting phosphorus into the first peripheral NMOS substrate area, the second peripheral PMOS substrate area and the memory array NMOS substrate area adjacent the first, the second and the third gate lines to form peripheral NMOS transistor LDD regions, peripheral PMOS transistor n-type halo regions and memory array NMOS transistor source/drain diffusion regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within the first, the second and the memory array substrate areas, the first energy level and the first depth being greater than the second energy level and the second depth, respectively.
24. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implant is conducted as a series of angled implants.
25. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implant is conducted as a series of angled implants, the angled implants being conducted at about 30° from vertical.
26. The method of forming CMOS memory integrated circuitry of
claim 23
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first peripheral NMOS substrate area, the peripheral PMOS substrate area, and the memory array NMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
27. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implanting step is conducted before the blanket ion implanting step.
28. The method of forming CMOS memory integrated circuitry of
claim 23
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first peripheral NMOS substrate area, the peripheral PMOS substrate area, and the memory array NMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
29. The method of forming CMOS memory integrated circuitry of
claim 23
 further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first peripheral NMOS substrate area, the peripheral PMOS substrate area, and the memory array NMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
30. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implant is conducted as a series of angled implants, and
the p-type halo implanting step is conducted before the blanket ion implanting step.
31. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first peripheral NMOS substrate area, the peripheral PMOS substrate area, and the memory array NMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the p-type halo implanting step being conducted before the blanket ion implanting step.
32. The method of forming CMOS memory integrated circuitry of
claim 23
 wherein the p-type halo implant is conducted as a series of angled implants, and
the method further comprising oxidizing sidewalls of the first, second and third gate lines, and oxidizing the first peripheral NMOS substrate area, the peripheral PMOS substrate area, and the memory array NMOS substrate area; the step of blanket ion implanting being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations; and the blanket ion implanting step being conducted after the sidewall, NMOS substrate areas and PMOS substrate area oxidations.
33. CMOS integrated circuitry produced according to the process of
claim 23
.
US09/832,447 1995-07-17 2001-04-10 Method of forming CMOS integrated circuitry Expired - Lifetime US6358787B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/832,447 US6358787B2 (en) 1995-07-17 2001-04-10 Method of forming CMOS integrated circuitry

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US08/503,419 US5534449A (en) 1995-07-17 1995-07-17 Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US08/631,249 US5683927A (en) 1995-07-17 1996-04-12 Method of forming CMOS integrated circuitry
US08/866,887 US5776806A (en) 1995-07-17 1997-05-30 Method of forming CMOS integrated circuitry having halo regions
US09/097,880 US6004854A (en) 1995-07-17 1998-06-15 Method of forming CMOS integrated circuitry
US09/468,281 US6261888B1 (en) 1995-07-17 1999-12-20 Method of forming CMOS integrated circuitry
US09/832,447 US6358787B2 (en) 1995-07-17 2001-04-10 Method of forming CMOS integrated circuitry

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/468,281 Continuation US6261888B1 (en) 1995-07-17 1999-12-20 Method of forming CMOS integrated circuitry

Publications (2)

Publication Number Publication Date
US20010012672A1 true US20010012672A1 (en) 2001-08-09
US6358787B2 US6358787B2 (en) 2002-03-19

Family

ID=27414231

Family Applications (4)

Application Number Title Priority Date Filing Date
US09/097,880 Expired - Lifetime US6004854A (en) 1995-07-17 1998-06-15 Method of forming CMOS integrated circuitry
US09/404,173 Expired - Lifetime US6074924A (en) 1995-07-17 1999-09-24 Method of forming CMOS integrated circuitry
US09/468,281 Expired - Lifetime US6261888B1 (en) 1995-07-17 1999-12-20 Method of forming CMOS integrated circuitry
US09/832,447 Expired - Lifetime US6358787B2 (en) 1995-07-17 2001-04-10 Method of forming CMOS integrated circuitry

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US09/097,880 Expired - Lifetime US6004854A (en) 1995-07-17 1998-06-15 Method of forming CMOS integrated circuitry
US09/404,173 Expired - Lifetime US6074924A (en) 1995-07-17 1999-09-24 Method of forming CMOS integrated circuitry
US09/468,281 Expired - Lifetime US6261888B1 (en) 1995-07-17 1999-12-20 Method of forming CMOS integrated circuitry

Country Status (1)

Country Link
US (4) US6004854A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042548A1 (en) * 2001-08-24 2003-03-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
US20040157397A1 (en) * 2003-02-10 2004-08-12 Chartered Semiconductor Manufacturing Ltd. Method of forming a pocket implant region after formation of composite insulator spacers
US6878589B1 (en) * 2003-05-06 2005-04-12 Advanced Micro Devices, Inc. Method and system for improving short channel effect on a floating gate device
US7170084B1 (en) * 2002-09-30 2007-01-30 Advanced Micro Devices, Inc. Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication
US20070194373A1 (en) * 2006-02-22 2007-08-23 Anderson Brent A Cmos structure and method including multiple crystallographic planes
CN107112211A (en) * 2015-01-23 2017-08-29 瓦里安半导体设备公司 Multiple-exposure for pattern Processing feature is handled
JP2018526831A (en) * 2015-09-03 2018-09-13 日本テキサス・インスツルメンツ株式会社 Embedded SiGe process for multi-threshold PMOS transistors

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004854A (en) * 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
KR100265227B1 (en) * 1998-06-05 2000-09-15 김영환 Method for fabricating cmos transistor
US6204138B1 (en) * 1999-03-02 2001-03-20 Advanced Micro Devices, Inc. Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects
US6413824B1 (en) * 1999-06-11 2002-07-02 Texas Instruments Incorporated Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors
US6579751B2 (en) * 1999-09-01 2003-06-17 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry
DE60139068D1 (en) * 2000-04-12 2009-08-06 Nxp Bv MANUFACTURING METHOD FOR SEMICONDUCTOR COMPONENT
US6716706B1 (en) * 2000-06-12 2004-04-06 Advanced Micro Devices, Inc. Method and system for forming a long channel device
US6380021B1 (en) * 2000-06-20 2002-04-30 Taiwan Semiconductor Manufacturing Company Ultra-shallow junction formation by novel process sequence for PMOSFET
KR100426441B1 (en) * 2001-11-01 2004-04-14 주식회사 하이닉스반도체 CMOS of semiconductor device and method for manufacturing the same
JP4122167B2 (en) 2002-03-19 2008-07-23 富士通株式会社 Semiconductor device and manufacturing method thereof
US7259053B2 (en) * 2003-09-22 2007-08-21 Dongbu Electronics Co., Ltd. Methods for forming a device isolation structure in a semiconductor device
JP2005209836A (en) * 2004-01-22 2005-08-04 Toshiba Corp Method for manufacturing semiconductor device
US20060020037A1 (en) * 2004-07-22 2006-01-26 Allergan, Inc. Tazarotenic acid and esters thereof for treating autism
JP2007298190A (en) * 2006-04-27 2007-11-15 Noritz Corp Combustion device
US7449386B2 (en) * 2006-11-16 2008-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Manufacturing method for semiconductor device to mitigate short channel effects

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2947350A1 (en) * 1979-11-23 1981-05-27 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING MNOS STORAGE TRANSISTORS WITH A VERY SHORT CHANNEL LENGTH IN SILICON GATE TECHNOLOGY
US5141890A (en) * 1982-02-01 1992-08-25 Texas Instruments Incorporated CMOS sidewall oxide-lightly doped drain process
US4474624A (en) * 1982-07-12 1984-10-02 Intel Corporation Process for forming self-aligned complementary source/drain regions for MOS transistors
JPS5952849A (en) * 1982-09-20 1984-03-27 Fujitsu Ltd Manufacture of semiconductor device
JPS62160754A (en) * 1986-01-09 1987-07-16 Nippon Gakki Seizo Kk Manufacture of integrated circuit device
JPS63119574A (en) * 1986-11-07 1988-05-24 Toshiba Corp Manufacture of semiconductor device
US4745083A (en) * 1986-11-19 1988-05-17 Sprague Electric Company Method of making a fast IGFET
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4933994A (en) * 1987-06-11 1990-06-19 General Electric Company Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide
US5024960A (en) * 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
US4753898A (en) * 1987-07-09 1988-06-28 Motorola, Inc. LDD CMOS process
US4771014A (en) * 1987-09-18 1988-09-13 Sgs-Thomson Microelectronics, Inc. Process for manufacturing LDD CMOS devices
IT1223571B (en) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics PROCEDURE FOR THE MANUFACTURE OF INTEGRATED CMOS DEVICES WITH REDUCED DOOR LENGTHS
IT1225614B (en) * 1988-08-04 1990-11-22 Sgs Thomson Microelectronics PROCESS FOR THE MANUFACTURE OF INTEGRATED CMOS DEVICES WITH REDUCED GATE LENGTHS AND SLIGHTLY DRAINED DRAIN
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
JPH0770727B2 (en) * 1989-06-16 1995-07-31 日本電装株式会社 Method for manufacturing MIS transistor and complementary MIS transistor
US5170232A (en) * 1989-08-24 1992-12-08 Nec Corporation MOS field-effect transistor with sidewall spacers
US5365110A (en) * 1989-11-07 1994-11-15 Kabushiki Kaisha Toshiba Semiconductor device with multi-layered wiring structure
US5172200A (en) * 1990-01-12 1992-12-15 Mitsubishi Denki Kabushiki Kaisha MOS memory device having a LDD structure and a visor-like insulating layer
JPH0423329A (en) * 1990-05-14 1992-01-27 Fujitsu Ltd Manufacture of semiconductor device
US5106768A (en) * 1990-08-31 1992-04-21 United Microelectronics Corporation Method for the manufacture of CMOS FET by P+ maskless technique
KR940004446B1 (en) * 1990-11-05 1994-05-25 미쓰비시뎅끼 가부시끼가이샤 Method of making semiconductor device
US5166087A (en) * 1991-01-16 1992-11-24 Sharp Kabushiki Kaisha Method of fabricating semiconductor element having lightly doped drain (ldd) without using sidewalls
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
EP0549055A3 (en) * 1991-12-23 1996-10-23 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device
US5424571A (en) * 1992-03-30 1995-06-13 Sgs-Thomson Microelectronics, Inc. Sloped spacer for mos field effect devices
US5532176A (en) * 1992-04-17 1996-07-02 Nippondenso Co., Ltd. Process for fabricating a complementary MIS transistor
JP3226053B2 (en) * 1992-06-03 2001-11-05 富士電機株式会社 Method for manufacturing semiconductor device
JPH06260496A (en) * 1993-03-03 1994-09-16 Ricoh Co Ltd Manufacture of semiconductor device
JP2848757B2 (en) * 1993-03-19 1999-01-20 シャープ株式会社 Field effect transistor and method of manufacturing the same
US5500379A (en) * 1993-06-25 1996-03-19 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
US5395787A (en) * 1993-12-01 1995-03-07 At&T Corp. Method of manufacturing shallow junction field effect transistor
US5429969A (en) * 1994-05-31 1995-07-04 Motorola, Inc. Process for forming electrically programmable read-only memory cell with a merged select/control gate
US5413945A (en) * 1994-08-12 1995-05-09 United Micro Electronics Corporation Blanket N-LDD implantation for sub-micron MOS device manufacturing
US5405791A (en) * 1994-10-04 1995-04-11 Micron Semiconductor, Inc. Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6004854A (en) * 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5736440A (en) * 1995-11-27 1998-04-07 Micron Technology, Inc. Semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate
US5670397A (en) * 1997-01-16 1997-09-23 Powerchip Semiconductor Corp. Dual poly-gate deep submicron CMOS with buried contact technology

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176515B2 (en) 2001-08-24 2007-02-13 Renesas Technology Corp. Semiconductor device including insulated gate type transistor and insulated gate type capacitance having protruded portions
US20060006434A1 (en) * 2001-08-24 2006-01-12 Renesas Technology Corp. Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
US20030042548A1 (en) * 2001-08-24 2003-03-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
US7456464B2 (en) 2001-08-24 2008-11-25 Renesas Technology Corp. Semiconductor device including insulated gate type transistor and insulated gate type variable capacitance, and method of manufacturing the same
US20070108494A1 (en) * 2001-08-24 2007-05-17 Renesas Technology Corp. Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
US20060267105A1 (en) * 2001-08-24 2006-11-30 Renesas Technology Corp. Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
US7157765B2 (en) 2001-08-24 2007-01-02 Renesas Technology Corp. Semiconductor device including insulated gate type transistor with pocket regions and insulated gate type capacitor with no region of reverse conductivity type
US7170084B1 (en) * 2002-09-30 2007-01-30 Advanced Micro Devices, Inc. Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication
US20040157397A1 (en) * 2003-02-10 2004-08-12 Chartered Semiconductor Manufacturing Ltd. Method of forming a pocket implant region after formation of composite insulator spacers
US6924180B2 (en) * 2003-02-10 2005-08-02 Chartered Semiconductor Manufacturing Ltd. Method of forming a pocket implant region after formation of composite insulator spacers
US6878589B1 (en) * 2003-05-06 2005-04-12 Advanced Micro Devices, Inc. Method and system for improving short channel effect on a floating gate device
US20070194373A1 (en) * 2006-02-22 2007-08-23 Anderson Brent A Cmos structure and method including multiple crystallographic planes
US7473946B2 (en) * 2006-02-22 2009-01-06 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
US20090111225A1 (en) * 2006-02-22 2009-04-30 International Business Machines Corporation Cmos structure and method including multiple crystallographic planes
US7785955B2 (en) 2006-02-22 2010-08-31 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
CN107112211A (en) * 2015-01-23 2017-08-29 瓦里安半导体设备公司 Multiple-exposure for pattern Processing feature is handled
JP2018526831A (en) * 2015-09-03 2018-09-13 日本テキサス・インスツルメンツ株式会社 Embedded SiGe process for multi-threshold PMOS transistors

Also Published As

Publication number Publication date
US6261888B1 (en) 2001-07-17
US6074924A (en) 2000-06-13
US6004854A (en) 1999-12-21
US6358787B2 (en) 2002-03-19

Similar Documents

Publication Publication Date Title
US5534449A (en) Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6358787B2 (en) Method of forming CMOS integrated circuitry
US4760033A (en) Method for the manufacture of complementary MOS field effect transistors in VLSI technology
US5693505A (en) Method of fabricating a semiconductor device
US6514810B1 (en) Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
US5930615A (en) Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS
US6117716A (en) Methods of forming BICMOS circuitry
JP2003188276A (en) Cmos of semiconductor element and its manufacturing method
JPH0536917A (en) Manufacture of complementary semiconductor device
US7091074B2 (en) Method of forming a gate oxide layer in a semiconductor device and method of forming a gate electrode having the same
EP0657929B1 (en) Method of fabricating MOSFETS with improved short channel effects
US5547894A (en) CMOS processing with low and high-current FETs
US6667206B2 (en) Method of manufacturing semiconductor device
JPH08186179A (en) Complementary semiconductor device
US6791147B1 (en) Semiconductor memory device and method for manufacturing the same
US5946564A (en) Methods of forming integrated circuitry and integrated circuitry
US6448121B1 (en) High threshold PMOS transistor in a surface-channel process
KR100192518B1 (en) Method of manufacturing cmos device
US20020039819A1 (en) Method for manufacturing a field effect transistor
JPH063808B2 (en) Method for manufacturing MOS semiconductor device
JPH07273212A (en) Semiconductor device and its manufacture
JP3216110B2 (en) Method of manufacturing complementary semiconductor device
KR0180785B1 (en) Method for manufacturing cmos field transistor
KR100207547B1 (en) Method of fabricating cmos
JPH06196642A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

FPAY Fee payment

Year of fee payment: 12