TWM641068U - Power module - Google Patents

Abstract

A power module includes a substrate, a first chip, a ceramic layer, a dissipation layer and a molding layer. The substrate has a wiring layer thereon. The first chip is on the wiring layer of the substrate, and is electrically connected to the wiring of the substrate. The first chip includes a source, a gate and a drain. The ceramic layer is over the first chip. The ceramic layer includes a first side and a second side. The first side and the second side are opposite and the first side faces the first chip. The dissipation layer is at the second side. The molding layer covers the substrate and the ceramic layer, and an upper surface of the dissipation layer is exposed in the molding layer. The power module in some embodiments of the present disclosure has good thermal dissipation effect and suitable creepage distance.

Description

power module

Some embodiments of the present disclosure relate to power modules.

A power module is a package including a plurality of power components (such as semiconductor chips). The power element can be arranged on the substrate, and the electrodes on the power element can be connected to a specific terminal by wiring. The application of power modules is common in automotive systems. For example, power modules can be used in components such as motor drives, inverters, converters, and power supplies.

Some embodiments of the present disclosure provide a power module, including a substrate, a first chip, a ceramic layer, a heat dissipation layer, and an encapsulant. The substrate contains wiring layers. The first chip is located on the wiring layer of the substrate and is electrically connected to the wiring layer of the substrate, wherein the first chip includes a source, a gate and a drain. The ceramic layer is located on the first wafer, and the ceramic layer includes a first surface and a second surface, the first surface is opposite to the second surface and the first surface faces the first wafer. The heat dissipation layer is located on the second surface of the ceramic layer. The encapsulation glue covers the substrate and the ceramic layer, and the upper surface of the heat dissipation layer is exposed outside the encapsulation glue.

In some embodiments, the upper surface of the heat dissipation layer is flush with the upper surface of the encapsulant.

In some embodiments, the power module further includes a conductor layer and a connecting body. The conductor layer is located on the first surface of the ceramic layer. The connecting body is located between the conductor layer and the wiring layer of the substrate.

In some implementations, the encapsulant covers the connecting body.

In some embodiments, the wiring layer includes a source pattern, a gate pattern and a drain pattern. The source of the first wafer is electrically connected to the source pattern. The gate pattern is adjacent to and separated from the source pattern, wherein the gate of the first wafer is electrically connected to the gate pattern. The drain pattern is adjacent to and separated from the source pattern, wherein the drain of the first wafer is electrically connected to the drain pattern.

In some embodiments, the power module further includes a second chip electrically connected to the gate pattern.

In some embodiments, the power module further includes a conductor layer and a connecting body. The conductor layer is located on the first surface of the ceramic layer. The connecting body is located between the conductor layer and the wiring layer of the substrate, and the conductor layer and the connecting body are electrically connected to the drain and the drain pattern of the first chip.

In some embodiments, the power module further includes an adhesive layer electrically connecting the first chip and the conductor layer.

In some embodiments, the thickness of the ceramic layer is between 0.2 mm and 2 mm.

In some embodiments, the sidewall of the heat dissipation layer is surrounded by encapsulant.

The power module according to some embodiments of the present disclosure can have good heat dissipation effect and proper creepage distance at the same time. Specifically, a ceramic layer can be placed on the chip of the power module, and a heat dissipation layer can be placed on the ceramic layer. Both the ceramic layer and the heat dissipation layer have good heat dissipation effects. In addition, the power module can also have an appropriate creepage distance by controlling the thickness of the ceramic layer.

The power module according to some embodiments of the present disclosure can have good heat dissipation effect and proper creepage distance at the same time. Specifically, a ceramic layer can be placed on the chip of the power module, and a heat dissipation layer can be placed on the ceramic layer. Both the ceramic layer and the heat dissipation layer have good heat dissipation effects. In addition, the power module can also have an appropriate creepage distance by controlling the thickness of the ceramic layer.

FIG. 1 shows a side view of a power module 100 according to some embodiments of the present disclosure. The power module 100 includes a substrate 110 , a first chip 120 , a ceramic layer 130 , a heat dissipation layer 140 and an encapsulant 150 .

The substrate 110 has a wiring layer 112 and a wiring layer 114 . In some embodiments, the substrate 110 , the wiring layer 112 and the wiring layer 114 can be printed circuit boards, and the wiring layer 112 and the wiring layer 114 are wirings located on opposite sides of the substrate 110 . In some embodiments, the substrate 110 may be made of, for example, plastic material, epoxy material, composite material, FR-4 material, or ceramic material. In some implementations, the wiring layer 112 and the wiring layer 114 can communicate with each other. The wiring layer 112 includes a source pattern 112S, a gate pattern 112G and a drain pattern 112D, and can be used to provide an electrical connection between the chip placed on the substrate 110 and external components. The gate pattern 112G and the drain pattern 112D may be respectively located on two sides of the source pattern 112S. The gate pattern 112G is adjacent to and separated from the source pattern 112S, and the drain pattern 112D is adjacent to and separated from the source pattern 112S. That is, the source pattern 112S is located between the gate pattern 112G and the drain pattern 112D, and the source pattern 112S, the gate pattern 112G, and the drain pattern 112D are electrically isolated from each other.

The first chip 120 is located on the wiring layer 112 of the substrate 110 and is electrically connected to the wiring layer 112 of the substrate 110 . In some embodiments, the first wafer 120 may be a silicon carbide wafer or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) wafer. The first wafer 120 includes a semiconductor layer 121 , a source 122 , a gate 124 and a drain 126 . In some embodiments, the source 122 and the gate 124 may be located on one side of the semiconductor layer 121 , and the drain 126 may be located on the other side of the semiconductor layer 121 . The source 122 and the gate 124 can face the substrate 110 , while the drain 126 can be away from the substrate 110 . The source 122 of the first chip 120 is electrically connected to the source pattern 112S. The gate 124 of the first chip 120 is electrically connected to the gate pattern 112G. The drain 126 of the first chip 120 is electrically connected to the drain pattern 112D. In some embodiments, the drain 126 of the first chip 120 is electrically connected to the drain pattern 112D through the conductor layer 162 and the connector 164 mentioned later.

The ceramic layer 130 is located on the first wafer 120 . The ceramic layer 130 may be made of Al ₂ O ₃ or Si ₃ N ₄ . The ceramic layer 130 includes a first surface 132 and a second surface 134 , the first surface 132 is opposite to the second surface 134 and the first surface 132 faces the first wafer 120 . The ceramic layer 130 has good thermal conductivity, so when the first chip 120 of the power module 100 is in operation, the heat dissipated by the first chip 120 can be transmitted upwards out of the power module 100 to reduce the first chip 120 of the power module 100. The temperature of the chip 120 during operation improves the stability of the power module 100 . In addition, the ceramic layer 130 also has good insulation properties, so the creepage distance between the heat dissipation layer 140 and the conductor layer 162 described later can be determined by determining the thickness T of the ceramic layer 130, so that under a specific applied voltage , the power module 100 can operate safely. The thickness T of the ceramic layer 130 can be adjusted according to the applied voltage of the power module 100 . In some embodiments, the thickness T of the ceramic layer 130 is between 0.2 mm and 2 mm.

The heat dissipation layer 140 is located on the second surface 134 of the ceramic layer 130 . That is, the ceramic layer 130 is located between the heat dissipation layer 140 and the first chip 120 . The heat dissipation layer 140 can be made of a material with good thermal conductivity, and in some embodiments, the heat dissipation layer 140 can be made of metal (such as copper, aluminum or silver). In other embodiments, the material of the heat dissipation layer 140 may also include ceramics, graphene, graphite, carbon nanotubes (carbon nanotube, CNT), carbon nanoballs (carbon nanoball), or combinations thereof . The heat dissipation layer 140 can be used to transfer the heat transferred to the ceramic layer 130 further upwards out of the power module 100 , so as to reduce the operating temperature of the first chip 120 of the power module 100 and improve the stability of the power module 100 .

The packaging glue 150 covers the substrate 110 , the wiring layer 112 and the ceramic layer 130 , and the upper surface 142 of the heat dissipation layer 140 is exposed outside the packaging glue 150 . That is, the upper surface 142 of the heat dissipation layer 140 is not covered by the encapsulant 150, so the heat dissipated from the first chip 120 to the heat dissipation layer 140 can be more easily dissipated to the outside of the power module 100, so that the first chip of the power module 100 The operating temperature of the power module 120 can be further reduced and the stability of the power module 100 can be improved. The encapsulant 150 can provide mechanical stability and protection against oxidation, humidity and other environmental conditions. In some embodiments, the encapsulant 150 may be formed of a molding material. The packaging material may include novolac-based resin, epoxy-based resin, silicone-based resin or other suitable encapsulating agents. The packaging material may also include a suitable filler, such as powdered silicon dioxide. The packaging material may be a pre-impregnated material, such as a pre-impregnated dielectric material. In some embodiments, the upper surface 142 of the heat dissipation layer 140 is flush with the upper surface 152 of the encapsulant 150 , and the sidewall 144 of the heat dissipation layer 140 is surrounded by the encapsulant 150 .

The power module 100 further includes a conductor layer 162 and a connecting body 164 . The conductive layer 162 is located on the first surface 132 of the ceramic layer 130 . The connecting body 164 is located between the conductor layer 162 and the wiring layer 112 of the substrate 110 . The conductor layer 162 and the connection body 164 are electrically connected to the first chip 120 and the wiring layer 112 , and the encapsulation glue 150 covers the connection body 164 . In some embodiments, the conductive layer 162 and the connecting body 164 are electrically connected to the drain 126 of the first chip 120 and the drain pattern 112D. In some embodiments, the conductive layer 162 and the connecting body 164 can be made of metal, such as copper.

The power module 100 further includes a second chip 170 , and the second chip 170 is electrically connected to the gate pattern 112G. The second chip 170 can be a driving chip to drive the first chip 120 .

The power module 100 may further include adhesive layers 182 , 184 , 186 , 188 and 189 . The adhesive layer 182 is electrically connected to the first chip 120 and the conductor layer 162 . The adhesive layers 184 and 186 are electrically connected to the first chip 120 and the wiring layer 112 . For example, the adhesive layer 184 is electrically connected to the gate 124 of the first chip 120 and the gate pattern 112G of the wiring layer 112 . The adhesive layer 186 is electrically connected to the source 122 of the first chip 120 and the source pattern 112S of the wiring layer 112 . The adhesive layer 188 is electrically connected to the connecting body 164 and the drain pattern 112D of the wiring layer 112 . The adhesive layer 189 is electrically connected to the second chip 170 and the gate pattern 112G of the wiring layer 112 . In some embodiments, the adhesive layers 182 , 184 , 186 , 188 , and 189 can be made of conductors, such as silver sintering, solder, or the like.

FIG. 2 to FIG. 9 are schematic diagrams illustrating the manufacturing process of the power module 100 in some embodiments of the present disclosure. Referring to FIG. 2, a ceramic layer 130 is provided. The ceramic layer 130 includes a first surface 132 and a second surface 134 , and the first surface 132 and the second surface 134 are opposite to each other. A conductive layer 162 is formed on the first surface 132 of the ceramic layer 130 , and a connecting body 164 is formed on the conductive layer 162 . The connecting body 164 may have any suitable shape, and in some embodiments, the connecting body 164 may be in the shape of a ball, a sheet, or the like. A heat dissipation layer 140 is formed on the second surface 134 of the ceramic layer 130 . The heat dissipation layer 140 is electrically isolated from the conductor layer 162 by the ceramic layer 130 .

Referring to FIG. 3 , an adhesive layer 182 is formed on the conductor layer 162 . Next, referring to FIG. 4 , the first wafer 120 is placed on the adhesive layer 182 . The drain 126 of the first chip 120 faces the ceramic layer 130 and contacts the adhesive layer 182 . The source 122 and the gate 124 of the first chip 120 are away from the ceramic layer 130 . That is, the adhesive layer 182 connects the conductor layer 162 and the drain 126 of the first chip 120 .

Referring to FIG. 5 , a substrate 110 is provided, and the substrate 110 includes a wiring layer 112 and a wiring layer 114 on two sides of the substrate 110 . The trace layer 112 includes a source pattern 112S, a gate pattern 112G and a drain pattern 112D. Next, adhesive layers 184 , 186 , 188 and 189 are formed on the wiring layer 112 of the substrate 110 . Specifically, the adhesive layer 186 can be formed on the source pattern 112S, the adhesive layers 184 and 189 can be formed on the gate pattern 112G, the adhesive layer 188 can be formed on the drain pattern 112D, and the adhesive layer 186 can be formed on the source pattern 112S. , the adhesive layers 184 and 189 on the gate pattern 112G, and the adhesive layer 188 on the drain pattern 112D are not in contact with each other.

Referring to FIG. 6 , a second wafer 170 is placed on the substrate 110 . The second chip 170 is placed on the adhesive layer 189 , and since the adhesive layer 189 is also in contact with the gate pattern 112G, the second chip 170 is also electrically connected to the gate pattern 112G. The number of second wafers 170 can be set according to different situations. In some embodiments, the number of second wafers 170 can be 2, as shown in FIG. 6 .

Referring to FIG. 7 , the ceramic layer 130 is turned over to place the first wafer 120 on the substrate 110 . The gate 124 of the first wafer 120 contacts the adhesive layer 184 on the gate pattern 112G, the source 122 of the first wafer 120 contacts the adhesive layer 186 on the source pattern 112S, and the connector 164 contacts the adhesive on the drain pattern 112D. Layer 184. Therefore, the gate 124 of the first chip 120 is electrically connected to the gate pattern 112G, the source 122 of the first chip 120 is electrically connected to the source pattern 112S, and the drain 126 of the first chip 120 is connected by the adhesive layer 182, the conductor The layer 162 and the connector 164 are electrically connected to the drain pattern 112D.

Referring to FIG. 8 , an encapsulant 150 is formed on the substrate 110 , the ceramic layer 130 , and the heat dissipation layer 140 . The encapsulant 150 covers the substrate 110 , the ceramic layer 130 , the heat dissipation layer 140 , the second chip 170 , and covers the first chip 120 and the connector 164 . At this time, the upper surface 152 of the encapsulant 150 is higher than the upper surface 142 of the heat dissipation layer 140 .

Referring to FIG. 9 , the upper surface 152 of the encapsulant 150 is ground so that the upper surface 152 of the encapsulant 150 is flush with the upper surface 142 of the heat dissipation layer 140 . The encapsulant 150 can be polished through a planarization process, and the planarization process can include mechanical polishing, chemical mechanical polishing, or other suitable processes and combinations thereof. The upper surface 142 of the heat dissipation layer 140 can be exposed through the encapsulation glue 150 . In this way, the power module 100 can be formed.

To sum up, the ceramic layer of the power module can be used for heat dissipation and control of creepage distance at the same time. Specifically, the ceramic layer and the heat dissipation layer above the ceramic layer have good heat dissipation capabilities, and the heat dissipation layer is not covered by the encapsulant, so the heat emitted by the first chip during operation can be transferred to the ceramic layer and the heat dissipation layer. , and is distributed outside the power module. In this way, the temperature of the first chip during operation can be reduced to increase the stability of the power module. In addition, the thickness of the ceramic layer can also be adjusted to control the creepage distance between the heat dissipation layer and the conductor layer, so that the power module can operate safely under a specific applied voltage.

The above are only some of the implementations of the disclosure, not all of the implementations. Any equivalent changes to the technical solution of the disclosure adopted by those of ordinary skill in the art by reading the description of the disclosure are covered by the patent scope of the disclosure. cover.

100: Power module 110: Substrate 112:Wiring layer 112D: drain pattern 112G: gate pattern 112S: source pattern 114:Wiring layer 120: first chip 121: semiconductor layer 122: source 124: Gate 126: drain 130: ceramic layer 132: The first side 134: second side 140: heat dissipation layer 142, 152: upper surface 144: side wall 150: encapsulation glue 162: conductor layer 164: Connector 170: second chip 182, 184, 186, 188, 189: adhesive layer T: Thickness

FIG. 1 shows a side view of a power module according to some embodiments of the present disclosure. FIG. 2 to FIG. 9 are schematic diagrams illustrating the manufacturing process of the power module in some embodiments of the present disclosure.

100: Power module

110: Substrate

112:Wiring layer

112D: drain pattern

112G: gate pattern

112S: source pattern

114:Wiring layer

120: first chip

121: semiconductor layer

122: source

124: Gate

126: drain

130: ceramic layer

132: The first side

134: second side

140: heat dissipation layer

142, 152: upper surface

144: side wall

150: encapsulation glue

162: conductor layer

164: Connector

170: second chip

182, 184, 186, 188, 189: adhesive layer

T: Thickness

Claims (10)

A power module, comprising: A substrate having a wiring layer on the substrate; a first chip located on the wiring layer of the substrate and electrically connected to the wiring layer of the substrate, wherein the first chip includes a source, a gate and a drain; a ceramic layer located on the first wafer, the ceramic layer includes a first surface and a second surface, the first surface is opposite to the second surface and the first surface faces the first wafer; a heat dissipation layer located on the second surface of the ceramic layer; and An encapsulation glue covers the substrate and the ceramic layer, and an upper surface of the heat dissipation layer is exposed outside the encapsulation glue. The power module according to claim 1, wherein the upper surface of the heat dissipation layer is flush with an upper surface of the encapsulant. The power module as described in claim 1 further includes: a conductive layer on the first face of the ceramic layer; and A connecting body is located between the conductor layer and the wiring layer of the substrate. The power module according to claim 3, wherein the encapsulant covers the connector. The power module as described in claim 1, wherein the wiring layer includes: a source pattern, wherein the source of the first wafer is electrically connected to the source pattern; a gate pattern adjacent to and separated from the source pattern, wherein the gate of the first wafer is electrically connected to the gate pattern; and A drain pattern is adjacent to and separated from the source pattern, wherein the drain of the first wafer is electrically connected to the drain pattern. The power module as described in claim item 5 further includes: A second chip is electrically connected to the gate pattern. The power module as described in claim item 5 further includes: a conductive layer on the first face of the ceramic layer; and A connecting body is located between the conductor layer and the wiring layer of the substrate, and the conductor layer and the connecting body are electrically connected to the drain and the drain pattern of the first chip. The power module as described in claim item 7 further includes: An adhesive layer electrically connects the first chip and the conductor layer. The power module according to claim 1, wherein the thickness of the ceramic layer is between 0.2 mm and 2 mm. The power module as claimed in claim 1, wherein a side wall of the heat dissipation layer is surrounded by the encapsulant.

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