TWI841391B - Flash memory apparatus and storage management method for flash memory - Google Patents

Flash memory apparatus and storage management method for flash memory Download PDF

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TWI841391B
TWI841391B TW112118732A TW112118732A TWI841391B TW I841391 B TWI841391 B TW I841391B TW 112118732 A TW112118732 A TW 112118732A TW 112118732 A TW112118732 A TW 112118732A TW I841391 B TWI841391 B TW I841391B
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flash memory
word lines
word line
data block
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TW202341158A (en
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楊宗杰
許鴻榮
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慧榮科技股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

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Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Description

快閃記憶體裝置及快閃記憶體儲存管理方法 Flash memory device and flash memory storage management method

本發明係關於一種快閃記憶體裝置，尤指一種執行一類似容錯式磁碟陣列的錯誤更正編碼操作之快閃記憶體裝置與儲存管理方法。 The present invention relates to a flash memory device, and more particularly to a flash memory device and storage management method for performing an error correction coding operation similar to a fault-tolerant disk array.

一般而言，對於一快閃記憶體控制器執行資料寫入以寫入一筆資料至單層單元資料區塊或是多層單元資料區塊，傳統的機制係採用於例如在一資料區塊的一字元線的最後一頁放置該字元線之其他資料頁所對應的校驗碼，使得當發生寫入失敗、字元線斷路及字元線短路時可利用該對應的校驗碼來進行一定程度的錯誤更正，然而，這樣的資料儲存率過低，例如一字元線如果包括8張資料頁，則僅有7張資料頁用來存資料，另一張資料頁是用來儲存校驗碼，如此一來，一個資料區塊中將會有1/8的比例是用來儲存校驗碼，而非用來儲存資料，就使用者的角度來說，無法被接受。 Generally speaking, for a flash memory controller to execute data writing to write a piece of data to a single-layer unit data block or a multi-layer unit data block, a conventional mechanism is to place a check code corresponding to other data pages of a word line in the last page of a word line of a data block, so that when a write failure, a word line disconnection, or a word line short circuit occurs, the corresponding check code can be used. To perform a certain degree of error correction, however, the data storage rate is too low. For example, if a word line includes 8 data pages, only 7 data pages are used to store data, and the other data page is used to store the checksum. In this way, 1/8 of a data block will be used to store the checksum instead of data. From the user's perspective, this is unacceptable.

因此，本發明的目的之一在於提供一種快閃記憶體裝置及對應的快閃記憶體儲存管理方法，採用一類似容錯式磁碟陣列的錯誤更正編碼操作，降低錯誤發生率，降低傳統機制所需要使用的校驗碼數目，同時適當地將所需的校驗碼儲存於對應的資料頁位置，令發生寫入失敗、字元線斷路及字元線短路時仍可利用所需的校驗碼來進行一定程度的錯誤更正，解決了上述的問題。 Therefore, one of the purposes of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which adopts an error correction coding operation similar to a fault-tolerant disk array to reduce the error rate and the number of checksums required by the traditional mechanism. At the same time, the required checksum is appropriately stored in the corresponding data page position, so that when a write failure, a word line break, or a word line short circuit occurs, the required checksum can still be used to perform a certain degree of error correction, thereby solving the above-mentioned problem.

根據本發明一實施例，其揭露了一種快閃記憶體裝置。快閃記憶體裝置包含有一快閃記憶體模組與快閃記憶體控制器，快閃記憶體模組包括複數 個單層單元資料區塊以及至少一多層單元資料區塊，快閃記憶體控制器具有複數條通道分別連接至快閃記憶體模組，快閃記憶體控制器係將一筆欲寫入之資料分類為複數群的資料，快閃記憶體控制器分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及對應的校驗碼寫入至複數個單層單元資料區塊；當完成複數個單層單元資料區塊的寫入時，快閃記憶體模組係執行內部複製，將複數個單層單元資料區塊所儲存之複數群的資料以及對應的校驗碼，依資料的先後順序，依序搬移寫入至至少一多層單元資料區塊。 According to an embodiment of the present invention, a flash memory device is disclosed. The flash memory device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of single-layer unit data blocks and at least one multi-layer unit data block. The flash memory controller has a plurality of channels respectively connected to the flash memory module. The flash memory controller classifies a data to be written into a plurality of groups of data. The flash memory controller respectively executes single-layer unit data writing and executes a similar fault-tolerant operation. The error correction coding operation of the disk array generates a corresponding check code to write the data of the plurality of groups and the corresponding check code into the plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, the flash memory module performs internal copying to move and write the data of the plurality of groups and the corresponding check code stored in the plurality of single-layer unit data blocks into at least one multi-layer unit data block in sequence according to the order of the data.

根據本發明一實施例，另揭露了一種快閃記憶體儲存管理方法。該方法包含有：提供一快閃記憶體模組，該快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊；將一筆欲寫入之資料分類為複數群的資料；分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及該對應的校驗碼寫入至該複數個單層單元資料區塊；當完成該複數個單層單元資料區塊的寫入時，執行一內部複製，將該複數個單層單元資料區塊所儲存之該複數群的資料以及該對應的校驗碼，依資料的先後順序，依序搬移寫入至該至少一多層單元資料區塊。 According to an embodiment of the present invention, a flash memory storage management method is disclosed. The method includes: providing a flash memory module, the flash memory module including a plurality of single-layer unit data blocks and at least one multi-layer unit data block; classifying a data to be written into a plurality of groups of data; performing a single-layer unit data writing and an error correction coding operation similar to a fault-tolerant disk array to generate a corresponding check code to convert the plurality of data blocks into a single-layer unit data block; The data of the group and the corresponding check code are written into the plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, an internal copy is executed to sequentially move and write the data of the plurality of groups and the corresponding check codes stored in the plurality of single-layer unit data blocks into the at least one multi-layer unit data block according to the order of the data.

100:快閃記憶體裝置 100: Flash memory device

105:快閃記憶體模組 105: Flash memory module

110:快閃記憶體控制器 110: Flash memory controller

205,210,401A,401B,402A,402B,403A,403B,605A,605B,605C:校驗碼儲存位置 205,210,401A,401B,402A,402B,403A,403B,605A,605B,605C: Verification code storage location

404,405,406,610,615,620:TLC資料區塊的資料頁 404,405,406,610,615,620: Data page of TLC data block

1051A,1051B,1051C:SLC資料區塊 1051A, 1051B, 1051C: SLC data block

1052:TLC資料區塊 1052: TLC data block

1101:錯誤更正碼編碼電路 1101: Error correction code encoding circuit

1102:校驗碼緩衝器 1102: Checksum buffer

1102A,1102B:緩衝區 1102A,1102B: Buffer area

第1圖為本發明一實施例之快閃記憶體裝置的裝置示意圖。 Figure 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention.

第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入將某一群之資料寫入至快閃記憶體模組內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。 FIG. 2 is a schematic diagram of the flash memory controller shown in FIG. 1 of the first embodiment of the present invention executing SLC data writing to write a certain group of data into an SLC data block in the flash memory module to perform an SLC data block write operation.

第3圖為快閃記憶體模組內之一SLC資料區塊通過內部複製將資料寫入至 TLC資料區塊的示意圖。 Figure 3 is a schematic diagram showing an SLC data block in a flash memory module writing data to a TLC data block through internal copying.

第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器寫入三個群的資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。 FIG. 4 is a schematic diagram showing that the flash memory controller shown in FIG. 1 of the first embodiment of the present invention writes three groups of data to multiple SLC data blocks in the flash memory module and moves the data to the TLC data block through internal copying to form a super block.

第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入以寫入一個群之資料至快閃記憶體模組內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。 FIG. 5 is a schematic diagram of the flash memory controller shown in FIG. 1 of the second embodiment of the present invention executing SLC data writing to write a group of data to the SLC data block in the flash memory module to complete an SLC data block writing operation.

第6圖為本發明第二實施例第1圖所示之快閃記憶體控制器寫入三個群之資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將該些SLC資料區塊之資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。 FIG. 6 is a schematic diagram showing that the flash memory controller shown in FIG. 1 of the second embodiment of the present invention writes data of three groups to multiple SLC data blocks in the flash memory module and moves the data of these SLC data blocks to the TLC data blocks through internal replication to form a super block.

請參照第1圖，其係為本發明一實施例之快閃記憶體裝置100的裝置示意圖。快閃記憶體裝置100包含快閃記憶體模組105及快閃記憶體控制器110，快閃記憶體模組105為一個具有二維平面架構的快閃記憶體模組；然此並非本案的限制。快閃記憶體模組105包含多個快閃記憶體晶片(並未繪示於第1圖)，每一快閃記憶體晶片包括多個單層單元資料區塊(single-level cell(SLC)block)及多個多層單元資料區塊(multiple-lelve-cell block)，單層單元資料區塊的每一單元可儲存2位元的資料，多層單元資料區塊的每一單元可儲存2N位元的資料，N大於或等於2並為整數，多層單元資料區塊例如包括有MLC區塊(multi-level cell block)之單元可儲存22位元的資料、TLC區塊(triple-level cell block)之單元可儲存23元的資料、QLC區塊(quad-level cell block)之單元可儲存24位元的資料，依此類推。 Please refer to FIG. 1, which is a schematic diagram of a flash memory device 100 according to an embodiment of the present invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module with a two-dimensional planar structure; however, this is not a limitation of the present invention. The flash memory module 105 includes a plurality of flash memory chips (not shown in FIG. 1 ), each of which includes a plurality of single-level cell (SLC) blocks and a plurality of multi-level cell blocks. Each cell of the single-level cell block can store 2 bits of data, and each cell of the multi-level cell block can store 2N bits of data, where N is greater than or equal to 2 and is an integer. For example, the multi-level cell block includes an MLC block (multi-level cell block) that can store 22 bits of data, and a TLC block (triple-level cell block) that can store 2 A cell in a QLC block (quad-level cell block) can store 24 bits of data, and so on.

快閃記憶體控制器110可通過複數條通道連接至快閃記憶體模組105，使可利用不同條通道同時寫入資料至不同的快閃記憶體晶片，增加寫入效 率，快閃記憶體控制器110包括一錯誤更正碼編碼電路1101及一校驗碼(parity check code)緩衝器1102，錯誤更正碼編碼電路1101用以對資料進行以一錯誤更正碼編碼操作，例如本案之實施例中包括里德-所羅門碼(Reed-solomon codes)的編碼操作及/或互斥或(exclusive-OR，XOR)運算的編碼操作，以產生相對應的校驗碼，校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼，而快閃記憶體控制器110係用以一類似容錯式磁碟陣列(Redundant Array of Independent Disks,RAID)的資料管理機制，將一筆資料寫入不同的快閃記憶體晶片，降低出錯率，並在寫入資料至單層單元資料區塊時即同時考慮不同編碼操作的校驗碼於單層單元資料區塊的儲位位置以及於TLC資料區塊的儲存位置，令在寫入資料至單層單元資料區塊時可更正資料出錯以及後續快閃記憶體模組105通過內部複製(internal copy)操作由單層單元區塊將資料複製搬移至TLC資料區塊時亦可更正資料出錯。 The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that different channels can be used to simultaneously write data to different flash memory chips, thereby increasing writing efficiency. The flash memory controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is used to encode data using an error correction code, such as a Reed-Solomon code in the embodiment of the present case. codes) and/or exclusive-OR (XOR) encoding operations to generate corresponding check codes. The check code buffer 1102 is used to temporarily store the generated corresponding check codes. The flash memory controller 110 is used to store the generated corresponding check codes in a redundant array of independent Disks, RAID) data management mechanism, writes a piece of data into different flash memory chips to reduce the error rate, and when writing data into the single-layer unit data block, it simultaneously considers the storage position of the check code of different encoding operations in the single-layer unit data block and the storage position in the TLC data block, so that when writing data into the single-layer unit data block, data errors can be corrected, and the subsequent flash memory module 105 can also correct data errors when copying and moving data from the single-layer unit block to the TLC data block through the internal copy operation.

實作上，為求資料寫入的效率及降低出錯率，快閃記憶體模組105包括多個通道(本案之實施例為2個通道，但非限定)，當一通道執行某一資料頁(page)的寫入時，可採用另一通道來執行另一資料頁的寫入，而不需要等候該通道，每一通道在快閃記憶體控制器110中有各自的序列傳輸器(sequencer)且均包含了多個快閃記憶體晶片(本案之實施例為2個晶片，但非限定)，使得一個通道可同時對多個快閃記憶體晶片執行不同資料頁的寫入，而不需要等候其中一個晶片，此外，每一快閃記憶體晶片可具有一折疊設計(folded)而具有不同的兩個平面(plane)，令一個快閃記憶體晶片在資料寫入時可同時利用不同兩平面上的兩個資料區塊來執行不同資料頁的寫入，而不需要等候其中某一個資料區塊。因此，快閃記憶體模組105的一個超級資料區塊(super block)係由多個通道的多個快閃記憶體晶片的多個資料頁所組成。上述的快閃記憶體控制器110即係將資料以超級資料區塊為單位來進行寫入，先將資料寫入至快閃記憶體模 組105內的單層單元資料區塊，由單層單元資料區塊緩衝，後續再從該些單層單元資料區塊將資料複製搬移至TLC資料區塊內。另外，應注意的是，其他實施例中，每一快閃記憶體晶片可不具有折疊設計，亦即，一個快閃記憶體晶片在資料寫入時係利用一資料區塊來執行一資料頁的寫入，其他資料頁的寫入需要等候時間。 In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes multiple channels (two channels in the embodiment of this case, but not limited to this). When one channel is executing the writing of a certain data page, another channel can be used to execute the writing of another data page without waiting for the channel. Each channel has its own sequencer in the flash memory controller 110 and includes multiple flash memory chips (the embodiment of this case). In one embodiment, the flash memory module 105 includes two flash memory chips (for example, two chips, but not limited thereto), so that one channel can simultaneously write different data pages to multiple flash memory chips without waiting for one of the chips. In addition, each flash memory chip can have a folded design (folded) and have two different planes, so that one flash memory chip can simultaneously use two data blocks on two different planes to write different data pages when writing data, without waiting for one of the data blocks. Therefore, a super block of the flash memory module 105 is composed of multiple data pages of multiple flash memory chips of multiple channels. The above-mentioned flash memory controller 110 writes data in super data blocks, first writes data to single-layer unit data blocks in the flash memory module 105, and then buffers the data in the single-layer unit data blocks. The data is then copied and moved from the single-layer unit data blocks to the TLC data blocks. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folding design, that is, when writing data, a flash memory chip uses a data block to execute the writing of a data page, and the writing of other data pages requires waiting time.

就資料寫入的流程而言，一筆資料會先被快閃記憶體控制器110寫入至多個單層單元資料區塊1051A~1051C，之後再從該些單層單元資料區塊1051A~1051C搬移至多層單元資料區塊1052，例如，在本實施例，係以TLC單元為架構的多層資料區塊為例，TLC單元可儲存23位元的資訊，也就是說，三個單層單元資料區塊(以下簡稱為SLC資料區塊)1051A~1051C的資料會被寫入至一個TLC資料區塊1052，據此，考量到需要共同對SLC資料區塊1051A~1051C的寫入以及TLC資料區塊1052的寫入進行錯誤更正的保護，快閃記憶體控制器110係將一筆資料分類為三個群(group)的資料，應注意的是，如果係以MLC單元為架構的多層資料區塊為例，由於MLC單元可儲存22位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為兩個群的資料，而如果係以QLC單元為架構的多層資料區塊為例，由於QLC單元可儲存24位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為四個群的資料；依此類推。也就是說，當上述多層單元資料區塊1052之單元可儲存具有2N位元的資訊，N大於等於2並為整數，單層單元資料區塊的數目會設計為N個SLC資料區塊，快閃記憶體控制器110係將該筆欲寫入之資料分類為N個群的資料，以分別寫入至N個SLC資料區塊。 In terms of the data writing process, a piece of data is first written into a plurality of single-layer cell data blocks 1051A-1051C by the flash memory controller 110, and then moved from the single-layer cell data blocks 1051A-1051C to the multi-layer cell data block 1052. For example, in this embodiment, a multi-layer data block with a TLC cell structure is used as an example. The TLC cell can store 2 3- bit information, that is, the data of three single-layer cell data blocks (hereinafter referred to as SLC data blocks) 1051A~1051C will be written into one TLC data block 1052. Therefore, considering the need to perform error correction protection on the writing of SLC data blocks 1051A~1051C and the writing of TLC data block 1052, the flash memory controller 110 classifies a piece of data into three groups of data. It should be noted that if a multi-layer data block with an MLC unit structure is used as an example, since the MLC unit can store 2 2 bits of information, so the flash memory controller 110 will classify the data into two groups of data. If a multi-layer data block with a QLC unit structure is used as an example, since the QLC unit can store 24 bits of information, the flash memory controller 110 will classify the data into four groups of data; and so on. That is to say, when the unit of the multi-layer unit data block 1052 can store information with 2N bits, N is greater than or equal to 2 and is an integer, the number of single-layer unit data blocks is designed to be N SLC data blocks, and the flash memory controller 110 classifies the data to be written into N groups of data to write them into the N SLC data blocks respectively.

在本實施例中，當快閃記憶體控制器110將該筆資料分類為三個群的資料後，會接著執行第一次的資料寫入(SLC program)將第一群的資料寫入上述第一個SLC資料區塊1051A以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第一個SLC資料區塊1051A中，如此便完成一次SLC資料區塊的寫入 操作，之後快閃記憶體控制器110接著執行第二次的資料寫入(SLC program)將第二群的資料寫入上述第二個SLC資料區塊1051B以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第二個SLC資料區塊1051B中，如此便完成第二次的SLC資料區塊的寫入操作，以及快閃記憶體控制器110接著執行第三次的資料寫入(SLC program)將第三群的資料寫入上述第三個SLC資料區塊1051C以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第三個SLC資料區塊1051C中，如此便完成第三次的SLC資料區塊的寫入操作。 In this embodiment, after the flash memory controller 110 classifies the data into three groups of data, it will then execute the first data write (SLC program) to write the first group of data into the first SLC data block 1051A and use the error correction code encoding circuit 1101 to generate a corresponding check code and write it into the first SLC data block 1051A, thus completing one SLC data block write operation. After that, the flash memory controller 110 then executes the second data write (SLC The second group of data is written into the second SLC data block 1051B by the SLC program and the corresponding check code is generated by the error correction code encoding circuit 1101 and written into the second SLC data block 1051B, thus completing the second SLC data block write operation. The flash memory controller 110 then executes the third data write (SLC program) to write the third group of data into the third SLC data block 1051C and the corresponding check code is generated by the error correction code encoding circuit 1101 and written into the third SLC data block 1051C, thus completing the third SLC data block write operation.

當快閃記憶體控制器110執行某一次的資料寫入(SLC program)將某一群的資料寫入某一個SLC資料區塊時，或該次資料寫入之後，快閃記憶體控制器110會檢測是否出錯，如果資料有錯，例如發生某一SLC資料區塊寫入的寫入失敗(program fail)、一字元線斷路(one word line open)及/或兩字元線短路(two word line short)的情況，快閃記憶體控制器110會利用錯誤更正碼編碼電路1101於該次資料寫入時所產生之對應校驗碼來更正上述的錯誤。 When the flash memory controller 110 executes a data write (SLC program) to write a group of data into a certain SLC data block, or after the data is written, the flash memory controller 110 will detect whether an error occurs. If the data is wrong, such as a write failure (program fail) in writing a certain SLC data block, a word line open, and/or two word lines short, the flash memory controller 110 will use the corresponding checksum generated by the error correction code encoding circuit 1101 during the data write to correct the above error.

當前述三個群的資料均寫入至三個SLC資料區塊時1051A~1051C或者某一個SLC資料區塊的資料寫入已完成時，快閃記憶體模組105係執行內部複製，從該些SLC資料區塊1051A~1051C或某一個SLC資料區塊中將三個群的資料或某一群的資料複製搬移並依三個群的資料順序執行資料寫入(TLC program)至一個TLC資料區塊1052(亦即前述的超級資料區塊)，TLC資料區塊1052係由不同通道的不同快閃記憶體晶片的字元線的資料頁所組成，例如，TLC資料區塊1052的一字元線的一資料頁包括有上資料頁(upper page)、中間資料頁(middle page)以及下資料頁(lower page)，快閃記憶體模組105的內部複製係依順序例如將一SLC資料區塊的第N條字元線上的多個資料頁寫入至TLC資料區塊1052之一字元線的多個上資料頁，將該SLC資料區塊的第N+1條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個中間資料頁，以及將該SLC資料區塊 的第N+2條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個下資料頁。待所有三個群的資料均寫入至TLC資料區塊1052，如此便完成了該超級資料區塊的寫入操作。 When the data of the three groups are written into the three SLC data blocks 1051A~1051C or the data writing of a certain SLC data block is completed, the flash memory module 105 performs internal copying, and copies and moves the data of the three groups or the data of a certain group from the SLC data blocks 1051A~1051C or a certain SLC data block and performs data writing (TLC program) to a TLC data block 1052 (i.e., the aforementioned super data block) in the order of the data of the three groups. The TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels. For example, a data page of a word line of the TLC data block 1052 includes an upper data page (upper data page); The internal copy of the flash memory module 105 is to write multiple data pages on the Nth word line of an SLC data block to multiple upper data pages of a word line of the TLC data block 1052, write multiple data pages on the N+1th word line of the SLC data block to multiple middle data pages of the same word line of the TLC data block 1052, and write multiple data pages on the N+2th word line of the SLC data block to multiple lower data pages of the same word line of the TLC data block 1052. When all three groups of data are written to the TLC data block 1052, the write operation of the super data block is completed.

應注意的是，為了令內部複製易於實現、符合TLC資料區塊1052的亂數種子數(randomizer seed)規則要求、以及同時考量錯誤更正編碼能力以降低出錯率，該內部複製操作係只是依資料的順序將資料搬移至TLC資料區塊1052的多條字元線的上、中、下資料頁的位置，而由快閃記憶體控制器110於寫入不同群的資料以及對應產生之校驗碼至該些SLC資料區塊1051A~1051C時，同時依據TLC資料區塊的亂數種子數規則要求以及考量錯誤更正編碼之校驗碼的寫入儲存位置，令錯誤更正碼編碼電路1101的錯誤更正編碼能力可於執行一次SLC資料區塊的寫入操作時更正SLC資料區塊的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤，以及可於執行該超級資料區塊的寫入操作時更正TLC資料區塊1052的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤。 It should be noted that in order to facilitate the internal copying, comply with the randomizer seed rule requirements of the TLC data block 1052, and consider the error correction coding capability to reduce the error rate, the internal copying operation is to move the data to the upper, middle, and lower data pages of the multiple word lines of the TLC data block 1052 in order, and when the flash memory controller 110 writes different groups of data and the corresponding check codes to the SLC data blocks 1051A~1051C, it also writes the randomizer seed rule requirements of the TLC data block to the upper, middle, and lower data pages of the multiple word lines of the TLC data block 1052. And considering the write storage location of the checksum of the error correction coding, the error correction coding capability of the error correction coding circuit 1101 can correct the error caused by the write failure of the SLC data block, a word line break and/or a two-word line short circuit when executing a write operation of the SLC data block, and can correct the error caused by the write failure of the TLC data block 1052, a word line break and/or a two-word line short circuit when executing the write operation of the super data block.

此外，如果快閃記憶體模組105進行記憶體垃圾回收(garbage collection)，快閃記憶體控制器110係通過外部讀取，從該些SLC資料區塊1051A~1051C中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入(SLC program)，及/或從TLC資料區塊1052中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入(SLC program)。此外，如果寫入資料(SLC program)至一SLC資料區塊且突然發生關機時，快閃記憶體控制器110係從該SLC資料區塊讀回資料並重新進行錯誤更正的編碼、寫入資料(SLC program)至另一新的SLC資料區塊。此外，如果寫入資料(TLC program)至TLC資料區塊1052且突然發生關機時，快閃記憶體模組105係放棄該TLC資料區塊1052中目前所儲存之資料，並從該些SLC資料區塊1051A~1051C，通過內部複製重新將對應的資料執行TLC資料寫入(TLC program)至該TLC資料區塊1052。 In addition, if the flash memory module 105 performs memory garbage collection, the flash memory controller 110 reads data from the SLC data blocks 1051A~1051C through external reading and re-encodes the data with error correction to execute data writing (SLC program), and/or reads data from the TLC data block 1052 and re-encodes the data with error correction to execute data writing (SLC program). In addition, if data (SLC program) is written to an SLC data block and a shutdown occurs suddenly, the flash memory controller 110 reads back the data from the SLC data block and re-encodes the error correction and writes the data (SLC program) to another new SLC data block. In addition, if data (TLC program) is written to the TLC data block 1052 and a shutdown occurs suddenly, the flash memory module 105 abandons the data currently stored in the TLC data block 1052 and re-writes the corresponding data from the SLC data blocks 1051A~1051C to the TLC data block 1052 through internal copying.

請參照第2圖，第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器110執行SLC資料寫入(SLC program)將某一群之資料寫入至快閃記憶體模組105內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的里德-所羅門(Reed Solomon，RS)編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。 Please refer to FIG. 2, which is a schematic diagram of the flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention executing SLC data writing (SLC program) to write a group of data into an SLC data block in the flash memory module 105 to perform an SLC data block writing operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a Reed Solomon (RS) encoding operation similar to a fault-tolerant disk array on the data to generate a corresponding check code, and the check code buffer 1102 is used to temporarily store the generated corresponding check code.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片及每一晶片的兩組區塊有兩不同平面，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片的兩區塊。如第2圖之實施方式所示，一SLC資料區塊包括有例如128條字元線(分別由WL0至WL127表示之)，該SLC資料區塊可以是由一個SLC資料區塊或是一組SLC子資料區塊所組成，視SLC資料區塊的定義而變，為方便描述，在實施例係將包括128條字元線視為一個SLC資料區塊的大小，其中每一條字元線包括有例如8個資料頁，以該SLC資料區塊的第一條字元線WL0為例，快閃記憶體控制器110藉由通道CH0及摺疊平面PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及摺疊平面PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及摺疊平面PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及摺疊平面PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。其他則依此類推。 The flash memory module 105 includes two channels, two flash memory chips, and two groups of blocks in each chip have two different planes. To improve writing efficiency, the flash memory controller 110 writes data to two blocks of the two flash memory chips in the flash memory module 105 through the two channels. As shown in the embodiment of FIG. 2, an SLC data block includes, for example, 128 word lines (represented by WL0 to WL127, respectively). The SLC data block may be composed of one SLC data block or a group of SLC sub-data blocks, depending on the definition of the SLC data block. For the convenience of description, in the embodiment, 128 word lines are regarded as the size of an SLC data block, wherein each word line includes, for example, 8 data pages. Taking the first word line WL0 of the SLC data block as an example, the flash memory controller 11 0 writes data pages P1 and P2 to the flash memory chip CE0 through channel CH0 and folding planes PLN0 and PLN1, then writes data pages P3 and P4 to another flash memory chip CE1 through the same channel CH0 and folding planes PLN0 and PLN1, then writes data pages P5 and P6 to the flash memory chip CE0 through another channel CH1 and folding planes PLN0 and PLN1, then writes data pages P7 and P8 to the flash memory chip CE1 through channel CH1 and folding planes PLN0 and PLN1. The same applies to the others.

快閃記憶體控制器110係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如為3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、WL127，其中 第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料(包括三條字元線之資料)，係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行錯誤更正編碼，並將所產生之對應之部分的校驗碼(partial parity code)輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。 The flash memory controller 110 classifies the multiple word lines WL0 to WL127 of an SLC data block into a group in sequence, where M is a positive integer greater than or equal to 2, for example, M is 3, for example, word lines WL0 to WL2 are the first group, word lines WL3 to WL5 are the second group, word lines WL6 to WL8 are the third group, word lines WL9 to WL11 are the fourth group, etc., word lines WL120 to WL122 are the third to last group, word lines WL123 to WL125 are the fourth group, and word lines WL127 to WL128 are the third to last group. The second to last group, the last group of word lines is WL126, WL127, among which the first, third, fifth, etc. groups of word lines are odd-numbered groups of word lines, and the second, fourth, sixth, etc. groups of word lines are even-numbered groups of word lines. Each time the flash memory controller 110 writes a group of word line data (including data of three word lines), the error correction code encoding circuit 1101 performs error correction encoding on the data of the group of word lines, and outputs the generated corresponding partial parity code to the parity code buffer 1102 to temporarily store the partial parity code.

校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組字元線資料所對應之部分的校驗碼儲存於一第一緩衝區1102A，將偶數組字元線資料所對應之部分的校驗碼儲存於一第二緩衝區1102B，舉例來說，當寫入字元線WL0~WL2之資料頁P1~P24時，錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；接著當寫入字元線WL3~WL5之資料頁P1~P24，錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第二緩衝區1102B；接著錯誤當寫入字元線WL6~WL8之資料頁P25~P48，錯誤更正碼編碼電路1101係對於資料頁P25~P48執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；後續的資料頁寫入與編碼操作係依此類推…；之後，當寫入字元線WL120~WL122之資料頁，錯誤更正碼編碼電路1101係對於字元線WL120~WL122之資料頁執行編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A。 When temporarily storing part of the check code, the check code buffer 1102 stores the part of the check code corresponding to the odd-numbered word line data in a first buffer 1102A, and stores the part of the check code corresponding to the even-numbered word line data in a second buffer 1102B. For example, when writing data pages P1-P24 of word lines WL0-WL2, the error correction code encoding circuit 1101 is The error correction coding is performed on the data pages P1 to P24, and the generated corresponding part of the check code is output to the check code buffer 1102 and temporarily stored in the first buffer area 1102A. Then, when the data pages P1 to P24 of the word lines WL3 to WL5 are written, the error correction code encoding circuit 1101 performs error correction coding on the data pages P1 to P24, and the generated corresponding part of the check code is output to the check code buffer 1102 and temporarily stored in the first buffer area 1102A. The check code is output to the check code buffer 1102 and temporarily stored in the second buffer 1102B; then, when the data pages P25 to P48 of the word lines WL6 to WL8 are written with errors, the error correction code encoding circuit 1101 performs error correction encoding on the data pages P25 to P48 and outputs the generated corresponding part of the check code to the check code buffer 1102 and temporarily stored in the first buffer. 1102A; The subsequent data page writing and encoding operations are similar to this...; Afterwards, when the data page of word lines WL120~WL122 is written, the error correction code encoding circuit 1101 performs encoding on the data page of word lines WL120~WL122, and outputs the generated corresponding partial checksum to the checksum buffer 1102, which is temporarily stored in the first buffer 1102A.

接著，快閃記憶體控制器110於寫入偶數組字元線的最後一組字元線(WL123~WL125)時，除了執行資料寫入(SLC program)與對應的錯誤更正編碼外，亦將第二緩衝區1102B所暫存之所有偶數組字元線之資料的部分校驗碼讀回，並將偶數組字元線之資料所對應之所有校驗碼寫入至最後一組偶數組字元線之最後一條字元線WL125的資料頁，例如最後3個資料頁(標記為205)，以儲 存偶數組字元線之資料所對應的里德-所羅門校驗碼。 Next, when writing the last word line (WL123~WL125) of the even-numbered word lines, the flash memory controller 110 not only executes data writing (SLC program) and corresponding error correction coding, but also reads back part of the checksum of the data of all even-numbered word lines temporarily stored in the second buffer 1102B, and writes all the checksums corresponding to the data of the even-numbered word lines to the data page of the last word line WL125 of the last even-numbered word line, for example, the last 3 data pages (marked as 205), to store the Reed-Solomon checksums corresponding to the data of the even-numbered word lines.

另外，對於寫入最後一組奇數組字元線的最後一條字元線WL127時，快閃記憶體控制器110除了執行資料寫入(SLC program)與對應的錯誤更正編碼外，會將第一緩衝區1102A所暫存之所有奇數組字元線之資料的部分校驗碼讀回，並將奇數組字元線之資料所對應之所有校驗碼寫入至最後一組奇數組字元線之最後一條字元線WL127的資料頁，例如最後3個資料頁(標記為210)，以儲存奇數組字元線之資料所對應的里德-所羅門校驗碼。如此便完成一次SLC資料區塊的寫入。因此，就里德-所羅門編碼操作而言，奇數組字元線之資料所對應的校驗碼係儲存於最後一組奇數組字元線之最後一條字元線WL127的最後複數張資料頁的位置，而偶數組字元線之資料所對應的校驗碼係儲存於最後一組偶數組字元線之最後一條字元線WL125的最後複數張資料頁的位置。 In addition, when writing the last word line WL127 of the last group of odd word lines, the flash memory controller 110, in addition to executing data writing (SLC program) and corresponding error correction coding, will read back part of the check codes of the data of all odd word lines temporarily stored in the first buffer 1102A, and write all the check codes corresponding to the data of the odd word lines into the data page of the last word line WL127 of the last group of odd word lines, such as the last 3 data pages (marked as 210), to store the Reed-Solomon check codes corresponding to the data of the odd word lines. In this way, the writing of an SLC data block is completed. Therefore, for the Reed-Solomon encoding operation, the check code corresponding to the data of the odd-numbered word lines is stored in the last data page of the last word line WL127 of the last odd-numbered word line, and the check code corresponding to the data of the even-numbered word lines is stored in the last data page of the last word line WL125 of the last even-numbered word line.

此外，錯誤更正碼編碼電路1101在第2圖所示之實施例所執行的是里德-所羅門編碼操作，可更正發生在SLC資料區塊之任意三個位置之資料頁的出錯，舉例來說，錯誤更正碼編碼電路1101對於字元線WL0~WL2的三條字元線的資料執行錯誤更正編碼並產生相對應的部分校驗碼，如果同一通道的相同晶片的同一摺疊平面的三個資料頁出錯，例如資料頁P1、P9、P17出錯，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將該三個資料頁的錯誤更正。 In addition, the error correction code encoding circuit 1101 in the embodiment shown in FIG. 2 performs a Reed-Solomon encoding operation, which can correct errors in data pages at any three locations in the SLC data block. For example, the error correction code encoding circuit 1101 performs error correction encoding on the data of the three word lines WL0~WL2 and generates corresponding partial check codes. If three data pages of the same folding plane of the same chip in the same channel have errors, such as data pages P1, P9, and P17, the error correction code encoding circuit 1101 can use the generated corresponding partial check codes to correct the errors of the three data pages.

如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗(program fail)的情況，例如以發生機率來說，例如檢測到資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9的錯誤更正。 If a program fail is detected when executing the write of the SLC data block, for example, if a write failure of data page P9 is detected, the error correction code encoding circuit 1101 can use the generated corresponding partial check code to correct the error of data page P9.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路(one word line open)而造成例如資料頁P9錯誤，錯誤更正碼編碼電路1101可利 用所產生之相對應的部分校驗碼，將資料頁P9的錯誤更正。 If a word line open is detected when executing the write of the SLC data block, resulting in, for example, an error in data page P9, the error correction code encoding circuit 1101 can use the generated corresponding partial check code to correct the error in data page P9.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路(two word line short)而造成例如資料頁P9、P17均錯誤，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9、P17的錯誤更正。如果發生兩字元線短路而造成例如字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼以及另一組字元線WL3~WL5的部分校驗碼，分別將字元線WL2的資料頁P17與字元線WL3的資料頁P1的錯誤更正。如果發生兩字元線短路而造成例如字元線WL0的資料頁P1、P2錯誤，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼，分別將字元線WL0的資料頁P1、P2的錯誤更正。 If two word line shorts are detected when executing the write of the SLC data block, causing errors in, for example, data pages P9 and P17, the error correction code encoding circuit 1101 can use the generated corresponding partial check codes to correct the errors in data pages P9 and P17. If two word line shorts occur, causing errors in, for example, data page P17 of word line WL2 and data page P1 of word line WL3, the error correction code encoding circuit 1101 can use partial check codes of one set of word lines WL0-WL2 and partial check codes of another set of word lines WL3-WL5 to respectively correct the errors in data page P17 of word line WL2 and data page P1 of word line WL3. If a short circuit occurs between two word lines, causing errors in data pages P1 and P2 of word line WL0, for example, the error correction code encoding circuit 1101 can use a set of partial check codes of word lines WL0~WL2 to correct the errors of data pages P1 and P2 of word line WL0 respectively.

因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。 Therefore, no matter a data page error is caused by a write failure, a word line break, or a two-word line short circuit when executing SLC data block writing, the error correction code encoding circuit 1101 can correct the erroneous data pages accordingly.

請參照第3圖，第3圖為快閃記憶體模組105內之一SLC資料區塊通過內部複製將資料寫入至TLC資料區塊1052的示意圖。如第3圖所示，一SLC資料區塊之一組三條字元線資料係寫入至TLC資料區塊1052之一字元線，對應地形成該字元線之一資料頁的最低有效位LSB、中間有效位CSB及最高有效位MSB的資料，例如SLC資料區塊之字元線資料WL0~WL2寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL0之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；SLC資料區塊之字元線資料WL3~WL5寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL1之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；SLC資料區塊之字元線資料WL6~WL8寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL2之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；也就是說，快閃記憶體模組105的內部複製係將SLC 資料區塊之資料依字元線的順序搬移並寫入填入至TLC資料區塊的字元線內。 Please refer to FIG. 3 , which is a schematic diagram showing that an SLC data block in the flash memory module 105 writes data to the TLC data block 1052 through internal copying. As shown in FIG. 3 , a group of three word line data of an SLC data block is written into a word line of a TLC data block 1052, and correspondingly forms the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB data of a data page of the word line. For example, the word line data WL0~WL2 of the SLC data block is written into the TLC data block 1052 as the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB data of the word line WL0 of the TLC data block 1052; the word line data WL3~WL5 of the SLC data block is written into the TLC data block 1052 as the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB data of the word line WL0 of the TLC data block 1052. Block 1052 is used as the data of the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB of the word line WL1 of the TLC data block 1052; the word line data WL6~WL8 of the SLC data block is written into the TLC data block 1052 as the data of the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB of the word line WL2 of the TLC data block 1052; that is, the internal copy of the flash memory module 105 is to move the data of the SLC data block in the order of the word line and write it into the word line filled in the TLC data block.

請參照第4圖，第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級資料區塊的示意圖。由於錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線及偶數組字元線兩組，並將對應產生之校驗碼儲存於奇數組字元線之最後一字元線的最後3張資料頁及偶數組字元線之最後一字元線的最後3張資料頁，因此，當執行TLC資料區塊的寫入時，如第4圖所示，第一個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL42的中間有效位CSB的最後三個資料頁(標記為401A)，而第一個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL41的最高有效位MSB的最後三個資料頁(標記為401B)；第二個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL85的最低有效位LSB的最後三個資料頁(標記為402A)，而第二個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL84的最高有效位MSB的最後三個資料頁(標記為402B)；第三個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127的最高有效位MSB的最後三個資料頁(標記為403A)，而第三個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127之最低有效位LSB的最後三個資料頁(標記為403B)。 Please refer to FIG. 4, which is a schematic diagram showing that the flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention writes three groups of data into multiple SLC data blocks 1051A~1051C in the flash memory module 105 and moves the data into the TLC data block through internal copying to form a super data block. Since the error correction code encoding circuit 1101 classifies the data into two groups, odd-numbered word lines and even-numbered word lines, each time the SLC data block is written, and stores the corresponding check code in the last three data pages of the last word line of the odd-numbered word line and the last three data pages of the last word line of the even-numbered word line, when the TLC data block is written, as in step 4 As shown in the figure, the check code corresponding to the odd-numbered word lines of the first group of data is stored in the last three data pages (marked as 401A) of the middle significant bit CSB of the word line WL42 of the super block, and the check code corresponding to the even-numbered word lines of the first group of data is stored in the last three data pages (marked as 401B) of the most significant bit MSB of the word line WL41 of the super block. ); the check code corresponding to the odd-numbered word lines of the second group of data is stored in the last three data pages (marked as 402A) of the least significant bit LSB of the word line WL85 of the super block, and the check code corresponding to the even-numbered word lines of the second group of data is stored in the last three data pages (marked as 402B) of the most significant bit MSB of the word line WL84 of the super block; The check codes corresponding to the odd-numbered word lines of the third group of data are stored in the last three data pages (marked as 403A) of the most significant bit MSB of the word line WL127 of the super block, and the check codes corresponding to the even-numbered word lines of the third group of data are stored in the last three data pages (marked as 403B) of the least significant bit LSB of the word line WL127 of the super block.

如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL0、WL1的兩資料頁(如框線404所標示)發生錯誤，快閃記憶體模組105可利用字元線WL42之中間有效位CSB的最後三張資料頁上儲存之校驗碼401A來更正字元線WL0之資料頁的錯誤，以及利用字元線WL41之最高有效位MSB之最後三張資料頁上儲存之校驗碼401B來更正字元線WL1之資料頁的錯誤。 If a short circuit between two word lines is detected, causing errors in two data pages (as indicated by frame 404) of word lines WL0 and WL1 of the superblock, for example, the flash memory module 105 can use the checksum 401A stored on the last three data pages of the middle valid bit CSB of word line WL42 to correct the error of the data page of word line WL0, and use the checksum 401B stored on the last three data pages of the most significant bit MSB of word line WL41 to correct the error of the data page of word line WL1.

相同地，如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL43、WL44的兩資料頁(如框線405所標示)發生錯誤，快閃記憶體模組105可利用字元線WL85之最後三張資料頁之最低有效位LSB上儲存之校驗碼402A來更正405所標示之字元線WL43之一資料頁之最低有效位LSB、中間有效位CSB的錯誤以及字元線WL44之一資料頁之最高有效位MSB的錯誤，以及利用字元線WL84之最後三張資料頁之中間有效位CSB上儲存之校驗碼402B，來更正405所標示之字元線WL43一資料頁之最高有效位MSB之錯誤以及字元線WL44一資料頁之最低有效位LSB、中間有效位CSB的錯誤。 Similarly, if a short circuit is detected between two word lines, causing errors in two data pages (as indicated by frame line 405) of word lines WL43 and WL44 of the superblock, the flash memory module 105 can use the checksum 402A stored on the least significant bit LSB of the last three data pages of word line WL85 to correct the least significant bit LSB, the middle significant bit LSB, and the middle significant bit LSB of one data page of word line WL43 indicated by frame line 405. The error of the most significant bit CSB of a data page of word line WL44 and the error of the most significant bit MSB of a data page of word line WL44 are corrected by using the check code 402B stored on the middle significant bit CSB of the last three data pages of word line WL84 to correct the error of the most significant bit MSB of a data page of word line WL43 marked by 405 and the error of the least significant bit LSB and the middle significant bit CSB of a data page of word line WL44.

相同地，如果是檢測到兩字元線短路而造成例如該TLC資料區塊之字元線WL125、WL126的兩資料頁(如框線406所標示)發生錯誤，快閃記憶體模組105可利用字元線WL127之最後三張資料頁之最高有效位MSB上儲存之校驗碼403A來更正406所標示之字元線WL125一資料頁之中間有效位CSB、最高有效位MSB的錯誤以及字元線WL126一資料頁之最高有效位MSB的錯誤，以及利用字元線WL127之最後三張資料頁之最低有效位LSB上儲存之校驗碼403B，來更正406所標示之字元線WL125一資料頁之最低有效位LSB之錯誤以及406所標示之字元線WL126一資料頁之中間有效位CSB、最高有效位MSB的錯誤。 Similarly, if a short circuit is detected between two word lines, causing errors in two data pages (as indicated by frame line 406) of word lines WL125 and WL126 of the TLC data block, for example, the flash memory module 105 can use the checksum 403A stored on the most significant bit MSB of the last three data pages of word line WL127 to correct the middle significant bit CSB, the most significant bit CSB, and the most significant bit CSB of the data page of word line WL125 indicated by frame line 406. The error of the MSB and the error of the most significant bit MSB of a data page of word line WL126, and the error of the least significant bit LSB of the last three data pages of word line WL127 are used to correct the error of the least significant bit LSB of a data page of word line WL125 marked by 406 and the error of the middle significant bit CSB and the most significant bit MSB of a data page of word line WL126 marked by 406.

如果是檢測到一字元線斷路或寫入失敗而造成超級區塊之任一字元線的任一資料頁發生錯誤(亦即連續任意三張子資料頁出錯)，則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三張子資料頁的錯誤。 If a word line break or write failure is detected, causing an error in any data page of any word line of the super block (i.e., any three consecutive sub-data pages are wrong), the flash memory module 105 can use the corresponding stored checksum to correct the error of any three consecutive sub-data pages.

也就是說，通過快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼之儲存位置管理設計，當快閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製寫入至TLC資料區塊而形成一個超級資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊 1051A~1051C所儲存之校驗碼來進行更正。 That is, the flash memory controller 110 writes the data of the three groups to the storage location management design of the checksum of the multiple SLC data blocks 1051A~1051C in the flash memory module 105. When the flash memory module 105 copies and writes the data from the multiple SLC data blocks 1051A~1051C to the TLC data block to form a super data block through internal copying, if a word line break, two word lines short circuit or write failure error is detected, it can be corrected by the checksum stored in the multiple SLC data blocks 1051A~1051C.

再者，請參照第5圖，第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器110執行資料寫入(SLC program)以寫入一個群之資料至快閃記憶體模組105內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的互斥或運算的編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。此外，錯誤更正碼編碼電路1101的互斥或運算包括有三個不同的編碼引擎以對SLC資料區塊的不同字元線資料進行互斥或運算；詳細操作內容如下所述。 Furthermore, please refer to FIG. 5, which is a schematic diagram of the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention executing a data write (SLC program) to write a group of data to the SLC data block in the flash memory module 105 to complete an SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a mutual exclusion or operation encoding operation similar to a fault-tolerant disk array on the data to generate a corresponding check code, and the check code buffer 1102 is used to temporarily store the generated corresponding check code. In addition, the mutual exclusion or operation of the error correction code encoding circuit 1101 includes three different encoding engines to perform mutual exclusion or operation on different word line data of the SLC data block; the detailed operation content is described as follows.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片，將一個SLC資料區塊之資料頁分別程式化至不同快閃記憶體晶片內，快閃記憶體控制器110的一次SLC資料區塊寫入操作所寫入的資料包括128條字元線(分別由WL0至WL127表示之)，每一條字元線包括8個資料頁，例如以字元線WL0為例，錯誤更正碼編碼電路1101藉由通道CH0及PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。 The flash memory module 105 includes two channels and two flash memory chips. To improve writing efficiency, the flash memory controller 110 writes data to the two flash memory chips in the flash memory module 105 through the two channels, and programs the data pages of an SLC data block into different flash memory chips. The data written by the flash memory controller 110 in one SLC data block write operation includes 128 word lines (represented by WL0 to WL127, respectively). Each word line includes 8 data pages, for example, Taking line WL0 as an example, the error correction code encoding circuit 1101 writes data pages P1 and P2 to the flash memory chip CE0 through channel CH0 and PLN0 and PLN1, then writes data pages P3 and P4 to another flash memory chip CE1 through the same channel CH0 and PLN0 and PLN1, then writes data pages P5 and P6 to the flash memory chip CE0 through another channel CH1 and PLN0 and PLN1, then writes data pages P7 and P8 to the flash memory chip CE1 through channel CH1 and PLN0 and PLN1.

錯誤更正碼編碼電路1101係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如為3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、 WL127，其中第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料(包括三條字元線之資料)，係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行互斥或運算的錯誤更正編碼，並將所產生之對應之部分的校驗碼(partial parity code)輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。 The error correction code encoding circuit 1101 classifies a plurality of word lines WL0 to WL127 of an SLC data block into a group in sequence, where M is a positive integer greater than or equal to 2, for example, M is 3, for example, word lines WL0 to WL2 are the first group, word lines WL3 to WL5 are the second group, word lines WL6 to WL8 are the third group, word lines WL9 to WL11 are the fourth group, etc., word lines WL120 to WL122 are the third to last group, word lines WL123 to WL125 are the last to last group, and word lines WL127 to WL128 are the third to last group. The second group, the last group of word lines is WL126, WL127, wherein the first, third, fifth, etc. groups of word lines are odd-numbered word lines, and the second, fourth, sixth, etc. groups of word lines are even-numbered word lines. Each time the flash memory controller 110 writes a group of word line data (including data of three word lines), the error correction code encoding circuit 1101 performs mutually exclusive or operational error correction encoding on the data of the group of word lines, and outputs the generated corresponding partial parity code to the parity code buffer 1102 to temporarily store the partial parity code.

錯誤更正碼編碼電路1101每次寫入資料至一組三條不同字元線時，係採用三個不同的編碼引擎對於所寫入之資料執行互斥或運算的編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，以暫存部分的校驗碼，而校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組之字元線資料所對應之部分的校驗碼儲存於一第一緩衝區，將偶數組之字元線資料所對應之部分的校驗碼儲存於一第二緩衝區。 Each time the error correction code encoding circuit 1101 writes data to a group of three different word lines, three different encoding engines are used to perform mutually exclusive or operational encoding on the written data, and the generated corresponding partial check codes are output to the check code buffer 1102 to temporarily store the partial check codes. When temporarily storing the partial check codes, the check code buffer 1102 stores the partial check codes corresponding to the odd-numbered word line data in a first buffer, and stores the partial check codes corresponding to the even-numbered word line data in a second buffer.

舉例來說，錯誤更正碼編碼電路1101包括有第一編碼引擎、第二編碼引擎及第三編碼引擎，當寫入字元線WL0~WL2之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL0的資料頁P1~P8執行互斥或運算以產生一第一部分校驗碼、利用第二編碼引擎對於字元線WL1的資料頁P9~P16進行互斥或運算以產生一第二部分校驗碼以及利用第三編碼引擎對於字元線WL2的資料頁P17~P24進行互斥或運算以產生一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第一緩衝區；接著錯誤更正碼編碼電路1101寫入字元線WL3~WL5之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL3的資料頁P1~P8執行互斥或運算以產生另一第一部分校驗碼、利用第二編碼引擎對於字元線WL4的資料頁P9~P16執行互斥或運算以產生另一第二部分校驗碼以及利用第三編碼引擎對於字元線WL5的資料頁P17~P24執行互斥或運算以產生另一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第二緩衝區。 For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine and a third encoding engine. When writing data pages P1-P24 of word lines WL0-WL2, the first encoding engine is used to perform an exclusive OR operation on data pages P1-P8 of word line WL0 to generate a first partial check code, the second encoding engine is used to perform an exclusive OR operation on data pages P9-P16 of word line WL1 to generate a second partial check code, and the third encoding engine is used to perform an exclusive OR operation on data pages P17-P24 of word line WL2 to generate a third partial check code, and the generated partial check codes are output to the check code buffer 11 respectively. 02, temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1~P24 of the word lines WL3~WL5, and sequentially uses the first encoding engine to perform exclusive or operation on the data pages P1~P8 of the word line WL3 to generate another first partial check code, uses the second encoding engine to perform exclusive or operation on the data pages P9~P16 of the word line WL4 to generate another second partial check code, and uses the third encoding engine to perform exclusive or operation on the data pages P17~P24 of the word line WL5 to generate another third partial check code, and outputs the generated partial check codes to the check code buffer 1102 respectively, and temporarily stored in the second buffer.

後續的資料頁寫入與編碼操作係依此類推…，也就是說，對於一組奇數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料以及對於一組偶數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料，均分別執行不同次的互斥或運算，產生相對應的校驗碼。之後為了寫入該些對應的校驗碼於SLC資料區塊的適當儲存位置，錯誤更正碼編碼電路1101在寫入最後6條字元線WL122~WL127之資料頁時，係將該些相對應的校驗碼寫入於最後6條字元線WL122~WL127之最後一張資料頁(如第5圖之長方形斜線框所示)，例如，在寫入字元線WL122之資料頁時，字元線WL122為一組奇數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL122的最後一張資料頁中寫入所有奇數組字元線中所有第三條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼)，而在寫入字元線WL123之資料頁時，字元線WL123為最後一組偶數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於字元線WL123的最後一張資料頁中寫入所有偶數組字元線中所有第一條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼)，而在寫入字元線WL124之資料頁時，字元線WL124為最後一組偶數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL124的最後一張資料頁中寫入所有偶數組字元線中所有第二條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼)，而在寫入字元線WL125之資料頁時，字元線WL125為最後一組偶數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL125的最後一張資料頁中寫入所有偶數組字元線中所有第三條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼)，而在寫入字元線WL126之資料頁時，字元線WL126為最後一組奇數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於 字元線WL126的最後一張資料頁中寫入所有奇數組字元線中所有第一條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼)，而在寫入字元線WL127之資料頁時，字元線WL127為最後一組奇數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL127的最後一張資料頁中寫入所有奇數組字元線中所有第二條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼)。如此便完成一次SLC資料區塊的寫入。 Subsequent data page writing and encoding operations are carried out in this way... That is, for the data of the first word line, the data of the second word line, and the data of the third word line of a set of odd-numbered word lines, and for the data of the first word line, the data of the second word line, and the data of the third word line of an even-numbered word line, different mutual exclusion or operations are performed respectively to generate corresponding checksums. Then, in order to write the corresponding check codes into the appropriate storage location of the SLC data block, the error correction code encoding circuit 1101 writes the corresponding check codes into the last data page of the last 6 word lines WL122 to WL127 when writing the data page of the last 6 word lines WL122 to WL127 (as shown in the rectangular diagonal frame in FIG. 5). For example, when writing the data page of word line WL122, word line WL122 is the third word line of a group of odd-numbered word lines. The error correction code encoding circuit 1101 writes the check codes corresponding to the data of all the third word lines in all the odd-numbered word lines in the last data page of word line WL122 (that is, the third word line of the odd-numbered word lines). When writing the data page of word line WL123, word line WL123 is the first word line of the last group of even-numbered word lines, and the error correction code encoding circuit 1101 writes the check code corresponding to the data of all the first word lines in all the even-numbered word lines in the last data page of word line WL123 (that is, all the first part of the check code generated by the first encoding engine in the even-numbered word lines), and when writing the data page of word line WL124, word line WL124 is the second word line of the last group of even-numbered word lines, and the error correction code encoding circuit 1101 writes the check code corresponding to the data of all the first word lines in all the even-numbered word lines in the last data page of word line WL123 (that is, all the first part of the check code generated by the first encoding engine in the even-numbered word lines). When writing the data page of word line WL125, word line WL125 is the third word line of the last group of even-numbered word lines. The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the third word lines in the even-numbered word lines in the last data page of word line WL125 (that is, all the third check codes generated by the third encoding engine in the even-numbered word lines). When writing the data page of word line WL126, word line WL126 is the third word line of the last group of odd-numbered word lines. For the first word line, the error correction code encoding circuit 1101 writes the check code corresponding to the data of all the first word lines in all odd word lines in the last data page of word line WL126 (that is, all the first part of the check code generated by the first encoding engine in the odd word lines), and when writing the data page of word line WL127, word line WL127 is the second word line of the last group of odd word lines, and the error correction code encoding circuit 1101 writes the check code corresponding to the data of all the second word lines in all odd word lines in the last data page of word line WL127 (that is, all the second part of the check code generated by the second encoding engine in the odd word lines). In this way, the writing of an SLC data block is completed.

也就是說，當快閃記憶體控制器110寫入一群的資料至一SLC資料區塊時，快閃記憶體控制器110係將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線，以及對一組奇數組的每一條字元線及一組偶數組的每一條字元線，分別執行不同M次的互斥或運算的編碼操作，產生該組奇數組的每一條字元線的M個部分校驗碼以及該組偶數組的每一條字元線的M個部分校驗碼，寫入並儲存該複數組奇數組的每一條字元線的M個部分校驗碼於該複數組奇數組字元線中最後M條字元線之最後一張資料頁、寫入並儲存該複數組偶數組的每一條字元線的M個部分校驗碼於該複數組偶數組字元線中最後M條字元線之最後一張資料頁。而以上述實施例，M為3，然此並非是本案的限制。 That is, when the flash memory controller 110 writes a group of data to an SLC data block, the flash memory controller 110 classifies all word lines of the SLC data block into a group of word lines in order, with each M word lines being a group, to generate a plurality of groups of odd-numbered word lines and a plurality of groups of even-numbered word lines, and performs M different mutually exclusive or arithmetic encoding operations on each word line of a group of odd-numbered word lines and each word line of a group of even-numbered word lines, respectively. Generate M partial check codes for each word line of the odd group and M partial check codes for each word line of the even group, write and store the M partial check codes for each word line of the odd group in the last data page of the last M word lines of the odd group, and write and store the M partial check codes for each word line of the even group in the last data page of the last M word lines of the even group. In the above embodiment, M is 3, but this is not a limitation of the present case.

錯誤更正碼編碼電路1101在第5圖所示之實施例所執行的是互斥或運算編碼操作，可更正發生在SLC資料區塊之一條字元線上一個位置的資料頁錯誤，舉例來說，如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗的情況，例如檢測到字元線WL1的資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。 The error correction code encoding circuit 1101 in the embodiment shown in FIG. 5 performs a mutually exclusive or arithmetic encoding operation, which can correct a data page error occurring at a position on a word line of the SLC data block. For example, if a write failure is detected when executing the write of the SLC data block, such as a write failure of data page P9 of word line WL1, the error correction code encoding circuit 1101 can use the corresponding partial checksum generated by the second encoding engine when processing the word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1 to correct the error of data page P9 of word line WL1.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路而造成例如字元線WL1的資料頁P9錯誤，錯誤更正碼編碼電路1101亦可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。 If a word line break is detected when executing the write of the SLC data block, resulting in an error in data page P9 of word line WL1, for example, the error correction code encoding circuit 1101 can also use the corresponding partial checksum generated by the second encoding engine when processing word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1 to correct the error of data page P9 of word line WL1.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路而造成例如字元線WL1的資料頁P9與字元線WL2的P17均錯誤，錯誤更正碼編碼電路1101可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤，以及利用第三編碼引擎於處理第一組字元線的字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤。而如果是字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，則錯誤更正碼編碼電路1101可利用第三編碼引擎於處理第一組字元線之字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤，以及利用第一編碼引擎於處理第二組字元線之字元線WL3時所產生之相對應的部分校驗碼及同一字元線WL3之其他正確的資料頁P2~P8，更正字元線WL3的資料頁P1的錯誤。因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。快閃記憶體模組105通過內部複製將上述SLC資料區塊將資料寫入至TLC資料區塊的操作如同前述第3圖的內容，不再贅述。 If a short circuit between two word lines is detected when executing the write of the SLC data block, resulting in errors in, for example, data page P9 of word line WL1 and data page P17 of word line WL2, the error correction code encoding circuit 1101 can utilize the corresponding partial check code generated by the second encoding engine when processing word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1 to correct the error of data page P9 of word line WL1, and utilize the corresponding partial check code generated by the third encoding engine when processing word line WL2 of the first group of word lines and other correct data pages P18~P24 of the same word line WL2 to correct the error of data page P17 of word line WL2. If errors occur in data page P17 of word line WL2 and data page P1 of word line WL3, the error correction code encoding circuit 1101 can utilize the corresponding partial check code generated by the third encoding engine when processing word line WL2 of the first group of word lines and other correct data pages P18~P24 of the same word line WL2 to correct the error of data page P17 of word line WL2, and utilize the corresponding partial check code generated by the first encoding engine when processing word line WL3 of the second group of word lines and other correct data pages P2~P8 of the same word line WL3 to correct the error of data page P1 of word line WL3. Therefore, no matter a data page error is caused by a write failure, a word line break, or a two-word line short circuit when executing the SLC data block write, the error correction code encoding circuit 1101 can correct the erroneous data pages accordingly. The operation of the flash memory module 105 writing the data from the SLC data block to the TLC data block through internal copying is the same as the content of the aforementioned Figure 3, which will not be repeated.

接著請參照第6圖，第6圖為本發明第二實施例第1圖所示之快閃記憶體控制器110寫入三個群之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將該些SLC資料區塊1051A~1051C之資料搬移寫入 至TLC資料區塊1052而形成一個超級區塊的示意圖。錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線與偶數組字元線，並將對應產生之校驗碼儲存於所有奇數組字元線中最後3條字元線之最後每一張資料頁以及所有偶數組字元線之最後3條字元線之最後每一張資料頁，如第6圖所示，執行TLC資料區塊寫入時，依資料寫入的順序，第一群中的字元線資料的對應校驗碼，如605A所標示，係寫入並儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB、字元線WL41之最後一張資料頁以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，其中第一個群中的SLC資料區塊的奇數組字元線的校驗碼儲存於字元線WL40之最後一張資料頁之最高有效位MSB以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，而第一個群中的SLC資料區塊的偶數組字元線的校驗碼儲存於字元線WL41之最後一張資料頁(包括最低有效位LSB、中間有效位CSB與最高有效位MSB)。 Next, please refer to FIG. 6, which is a schematic diagram showing that the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention writes data of three groups into multiple SLC data blocks 1051A~1051C in the flash memory module 105 and moves the data of the SLC data blocks 1051A~1051C to the TLC data block 1052 through internal copying to form a super block. Each time the error correction code encoding circuit 1101 performs writing of the SLC data block, the data is classified into odd-numbered word lines and even-numbered word lines, and the corresponding check code is stored in the last data page of the last 3 word lines of all odd-numbered word lines and the last data page of the last 3 word lines of all even-numbered word lines, as shown in FIG. 6. When performing writing of the TLC data block, according to the order of data writing, the corresponding check code of the word line data in the first group, as indicated by 605A, is written and stored in the most significant bit MSB of the last data page of word line WL40 of TLC data block 1052. , the last data page of word line WL41 and the least significant bit LSB and the middle significant bit CSB of the last data page of word line WL42, wherein the check code of the odd-numbered word lines of the SLC data block in the first group is stored in the most significant bit MSB of the last data page of word line WL40 and the least significant bit LSB and the middle significant bit CSB of the last data page of word line WL42, and the check code of the even-numbered word lines of the SLC data block in the first group is stored in the last data page of word line WL41 (including the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB).

第二個群中的字元線資料的對應校驗碼，如605B所標示，係寫入並儲存於TLC資料區塊1052之字元線WL83之最後一張資料頁之中間有效位CSB與最高有效位MSB、字元線WL84之最後一張資料頁以及字元線WL85之最後一張資料頁之最低有效位LSB，其中對於第二個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之中間有效位CSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最高有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL85之最後一張資料頁之最低有效位LSB，而對於第二個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之最高 有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最低有效位LSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之中間有效位CSB。 The corresponding checksum of the word line data in the second group, as indicated by 605B, is written and stored in the middle significant bit CSB and the most significant bit MSB of the last data page of word line WL83 of TLC data block 1052, the last data page of word line WL84, and the least significant bit LSB of the last data page of word line WL85. For the odd-numbered word line data of the data block, all the third partial check codes generated by the third encoding engine are stored in the middle valid bit CSB of the last data page of the word line WL83 of the TLC data block 1052, and all the first partial check codes generated by the first encoding engine are stored in the most significant bit MSB of the last data page of the word line WL84 of the TLC data block 1052. All the second partial check codes generated by the second encoding engine are stored in the least significant bit LSB of the last data page of word line WL85 of TLC data block 1052, and for the even-numbered word line data in the SLC data block in the second group, all the first partial check codes generated by the first encoding engine are stored in the last data page of word line WL83 of TLC data block 1052. The most significant bit MSB of the data page, all the second part check codes generated by the second encoding engine are stored in the least significant bit LSB of the last data page of the word line WL84 of the TLC data block 1052, and all the third part check codes generated by the third encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL84 of the TLC data block 1052.

第三個群之字元線資料的對應校驗碼，如605C所標示，係寫入並儲存於TLC資料區塊1052之字元線WL126、127之最後一張資料頁(包括最低有效位LSB、中間有效位CSB與最高有效位MSB)，其中對於第三個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最低有效位LSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最高有效位MSB，而對於第三個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最高有效位MSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最低有效位LSB。 The corresponding check codes of the word line data of the third group, as indicated by 605C, are written and stored in the last data page (including the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB) of the word lines WL126 and 127 of the TLC data block 1052, wherein for the odd-numbered word line data in the SLC data block of the third group, all the third partial check codes generated by the third encoding engine are stored in the least significant bit LSB of the last data page of the word line WL126 of the TLC data block 1052, all the first partial check codes generated by the first encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL127 of the TLC data block 1052, and all the first partial check codes generated by the second encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL127 of the TLC data block 1052. The second part of the check code is stored in the most significant bit MSB of the last data page of word line WL127 of TLC data block 1052, and for the even-numbered word line data in the SLC data block in the third group, all the first part of the check code generated by the first encoding engine is stored in the middle significant bit CSB of the last data page of word line WL126 of TLC data block 1052, all the second part of the check code generated by the second encoding engine is stored in the most significant bit MSB of the last data page of word line WL126 of TLC data block 1052, and all the third part of the check code generated by the third encoding engine is stored in the least significant bit LSB of the last data page of word line WL127 of TLC data block 1052.

因此，當快閃記憶體模組105透過內部複製操作從該些SLC資料區塊1051A~1051C搬移寫入資料至TLC資料區塊1052時，如果檢測到兩字元線短路而造成例如TLC資料區塊1052之字元線WL0、WL1的兩資料頁(如框線610所標示)發生錯誤，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL42之最後一張資料頁之中間有效位CSB的第一部分校驗碼以及字元線WL0之其他資料頁的最低有效位LSB的資料，更正610所標記之字元線WL0之資料頁的最低有 效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL42之最後一張資料頁之最高有效位MSB的第二部分校驗碼以及字元線WL0之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL0之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL0之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL0之資料頁的最高有效位MSB的資料。相同地，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最低有效位LSB的第一部分校驗碼以及字元線WL1之其他資料頁的最低有效位LSB的資料，來更正610所標記之字元線WL1之資料頁的最低有效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之中間有效位CSB的第二部分校驗碼以及字元線WL1之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL1之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL1之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL1之資料頁的最高有效位MSB的資料。 Therefore, when the flash memory module 105 moves the write data from the SLC data blocks 1051A~1051C to the TLC data block 1052 through the internal copy operation, if a short circuit between two word lines is detected, causing errors in, for example, two data pages of word lines WL0 and WL1 of the TLC data block 1052 (as indicated by frame line 610), the flash memory module 105 can use the first part of the checksum of the middle valid bit CSB of the last data page of word line WL42 of the TLC data block 1052 and the data of the least significant bit LSB of other data pages of word line WL0 to correct the least significant bit LSB of the data page of word line WL0 marked by frame line 610. The data of the valid bit LSB is used to correct the data of the middle valid bit CSB of the data page of the word line WL0 marked by 610 using the second part of the check code of the most significant bit MSB of the last data page of the word line WL42 stored in the TLC data block 1052 and the data of the middle valid bit CSB of other data pages of the word line WL0, and the data of the most significant bit MSB of the data page of the word line WL0 marked by 610 is corrected using the third part of the check code of the most significant bit MSB of the last data page of the word line WL40 stored in the TLC data block 1052 and the data of the most significant bit MSB of other data pages of the word line WL0. Similarly, the flash memory module 105 can use the first part of the least significant bit LSB of the last data page of the word line WL41 stored in the TLC data block 1052 and the data of the least significant bit LSB of other data pages of the word line WL1 to correct the data of the least significant bit LSB of the data page of the word line WL1 marked by 610, and use the second part of the middle valid bit CSB of the last data page of the word line WL41 stored in the TLC data block 1052 to correct the data of the least significant bit LSB of the data page of the word line WL1 marked by 610. The data of the middle significant bit CSB of the data page of word line WL1 marked by 610 is corrected by using the third part of the checksum of the most significant bit MSB of the last data page of word line WL41 stored in TLC data block 1052 and the data of the most significant bit MSB of other data pages of word line WL1 to correct the data of the most significant bit MSB of the data page of word line WL1 marked by 610.

相似地，如果兩字元線短路而造成之錯誤是發生在超級區塊之任兩連續字元線的之連續資料頁(例如如615、620所標示的錯誤位置)，快閃記憶體模組105均可利用每一群組中一SLC資料區塊之最後6條字元線之最後一資料頁所儲存之相對應的校驗碼來更正錯誤。此外，如果是檢測到一字元線斷路或寫入失敗而造成TLC資料區塊1052之任一字元線的任一資料頁發生錯誤(亦即同一資料頁的三個有效位均出錯或是連續兩不同資料頁的不同有效位出錯)，則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三個有效位的錯誤。 Similarly, if the error caused by the short circuit of two word lines occurs in consecutive data pages of any two consecutive word lines of the super block (for example, the error positions indicated by 615 and 620), the flash memory module 105 can use the corresponding checksum stored in the last data page of the last 6 word lines of an SLC data block in each group to correct the error. In addition, if a word line break or write failure is detected, causing an error in any data page of any word line of the TLC data block 1052 (i.e., all three valid bits of the same data page are wrong or different valid bits of two different data pages are wrong), the flash memory module 105 can use the corresponding stored checksum to correct the errors of any three consecutive valid bits.

也就是說，通過快閃記憶體控制器110寫入三個群的資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼儲存位置管理設計，當快 閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製搬移寫入至TLC資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊1051A~1051C儲存之校驗碼來進行更正。 That is, the flash memory controller 110 writes the data of the three groups to the checksum storage location management design of the multiple SLC data blocks 1051A~1051C in the flash memory module 105. When the flash memory module 105 copies and moves the data from the multiple SLC data blocks 1051A~1051C to the TLC data block through internal replication, if a word line break, two word lines short circuit or write failure error is detected, it can be corrected by the checksum stored in the multiple SLC data blocks 1051A~1051C.

再者，本案上述的實施例亦適用於MLC資料區塊或QLC資料區塊等架構，當使用於MLC資料區塊時，上述三個群資料改為分類為兩個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用兩個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；因此，如果是使用於QLC資料區塊時，上述三個群資料改為分類為四個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用四個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；其他資料區塊的架構則依此類推。 Furthermore, the above-mentioned embodiments of the present case are also applicable to MLC data block or QLC data block architectures. When used in MLC data blocks, the above-mentioned three groups of data are changed to be classified into two groups of data, and if the mutually exclusive or calculation encoding operation is performed, two encoding engines are used to implement it, and other conditions are the same as those used in TLC data blocks; therefore, if used in QLC data blocks, the above-mentioned three groups of data are changed to be classified into four groups of data, and if the mutually exclusive or calculation encoding operation is performed, four encoding engines are used to implement it, and other conditions are the same as those used in TLC data blocks; the architecture of other data blocks is similar.

以資料儲存的成本(overhead)來看，如果是採用兩個通道寫入兩個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入兩個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有8*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比不到1%(6/(128*8))，亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用低於1%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率極高。而如果是採用4個通道寫入4個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入2個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有4*4*2*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比將可更低，約為0.15%(6/(128*4*4*2))，亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用約為0.15%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率更高。 From the perspective of data storage cost (overhead), if two channels are used to write to two memory chips, and each memory chip has a folded plane design that allows two blocks to be written at the same time, then for data writing of an SLC data block, 128 word lines have a total of 8*128 data pages, and only 6 data pages are needed to store the corresponding checksums, and the cost percentage is less than 1% (6/(128*8)). In other words, for writing to SLC data blocks and TLC data blocks, only less than 1% of the data space is used to store the corresponding error correction checksums, and the data space usage efficiency is extremely high. If 4 channels are used to write 4 memory chips, and each memory chip has a folded plane design that allows 2 blocks to be written at the same time, then for data writing of an SLC data block, 128 word lines have a total of 4*4*2*128 data pages, and only 6 data pages are needed to store the corresponding checksums. The cost percentage will be lower, about 0.15% (6/(128*4*4*2)). That is, for writing SLC data blocks and TLC data blocks, only about 0.15% of the data space is used to store the corresponding error correction checksums, and the data space usage efficiency is higher.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化 與修飾，皆應屬本發明之涵蓋範圍。 The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:快閃記憶體裝置 100: Flash memory device

105:快閃記憶體模組 105: Flash memory module

110:快閃記憶體控制器 110: Flash memory controller

1051A,1051B,1051C:SLC資料區塊 1051A, 1051B, 1051C: SLC data block

1052:TLC資料區塊 1052: TLC data block

1101:錯誤更正碼編碼電路 1101: Error correction code encoding circuit

1102:校驗碼緩衝器 1102: Checksum buffer

1102A,1102B:緩衝區 1102A,1102B: Buffer area

Claims (13)

一種快閃記憶體裝置，包含有：一快閃記憶體模組，包括複數個第一資料區塊以及至少一第二資料區塊；以及一快閃記憶體控制器，連接至該快閃記憶體模組的複數個快閃記憶體晶片，該快閃記憶體控制器係先將一筆欲寫入之資料分類為複數群的資料，分別將該複數群的資料以及一對應的校驗碼寫入至位於該複數個快閃記憶體晶片的該複數個第一資料區塊，待完成該複數個第一資料區塊的寫入後，由該快閃記憶體模組將該複數個第一資料區塊所儲存之該複數群的資料以及該對應的校驗碼搬移寫入至該快閃記憶體模組的該至少一第二資料區塊，完成將該筆欲寫入之資料寫到該至少一第二資料區塊之操作；以及，當進行記憶體垃圾回收(garbage collection)時，該快閃記憶體控制器係從外部讀取出該複數個第一資料區塊之資料並進行重新編碼與SLC寫入，或從外部讀取出該至少一第二資料區塊並進行重新編碼與SLC寫入。 A flash memory device includes: a flash memory module, including a plurality of first data blocks and at least one second data block; and a flash memory controller connected to a plurality of flash memory chips of the flash memory module. The flash memory controller first classifies a data to be written into a plurality of groups of data, and writes the plurality of groups of data and a corresponding check code into the plurality of flash memory chips. The plurality of first data blocks of the chip, after the writing of the plurality of first data blocks is completed, the flash memory module moves the plurality of groups of data stored in the plurality of first data blocks and the corresponding check code to the at least one second data block of the flash memory module, completing the operation of writing the data to be written to the at least one second data block; and when performing memory garbage collection, the flash memory controller reads the data of the plurality of first data blocks from the outside and re-encodes and writes them to the SLC, or reads the at least one second data block from the outside and re-encodes and writes them to the SLC. 如申請專利範圍第1項所述之快閃記憶體裝置，其中該至少一第二資料區塊為一TLC資料區塊，儲存三個位元的資料，該快閃記憶體控制器係將該筆欲寫入之資料分類為三個群的資料，以分別寫入至三個SLC資料區塊。 As described in the first item of the patent application scope, the at least one second data block is a TLC data block storing three bits of data, and the flash memory controller classifies the data to be written into three groups of data to be written into three SLC data blocks respectively. 如申請專利範圍第1項所述之快閃記憶體裝置，其中該複數個第一資料區塊為複數個SLC資料區塊，當快閃記憶體控制器寫入一群的資料至一SLC資料區塊時，該快閃記憶體控制器係將該SLC資料區塊的所有字元線(word line)依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組 偶數組的字元線，以及對一組奇數組的每一條字元線及一組偶數組的每一條字元線，分別執行不同M次的互斥或運算的編碼操作，產生該組奇數組的每一條字元線的M個部分校驗碼以及該組偶數組的每一條字元線的M個部分校驗碼，寫入並儲存該複數組奇數組的每一條字元線的M個部分校驗碼於該複數組奇數組字元線中最後M條字元線之最後一張資料頁、寫入並儲存該複數組偶數組的每一條字元線的M個部分校驗碼於該複數組偶數組字元線中最後M條字元線之最後一張資料頁。 As described in the first item of the patent application, the plurality of first data blocks are a plurality of SLC data blocks. When the flash memory controller writes a group of data to an SLC data block, the flash memory controller writes all word lines of the SLC data block to the SLC data block. line) classifies each M word lines into a group of word lines in sequence to generate a plurality of groups of odd word lines and a plurality of groups of even word lines, and performs M different mutually exclusive or operation encoding operations on each word line of a group of odd word lines and each word line of a group of even word lines, respectively, to generate M partial check codes of each word line of the group of odd word lines and M partial check codes of each word line of the group of even word lines, write and store the M partial check codes of each word line of the group of odd word lines in the last data page of the last M word lines of the group of odd word lines, and write and store the M partial check codes of each word line of the group of even word lines in the last data page of the last M word lines of the group of even word lines. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至該至少一第二資料區塊且突然發生關機時，該快閃記憶體控制器係放棄該至少一第二資料區塊所儲存之資料，並執行內部複製，從該些複數第一資料區塊搬移寫入資料至該至少一第二資料區塊。 As described in item 1 of the patent application scope, the flash memory device, when data is written to the at least one second data block and a sudden shutdown occurs, the flash memory controller abandons the data stored in the at least one second data block and performs an internal copy to move the written data from the plurality of first data blocks to the at least one second data block. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至該些第一資料區塊時，該快閃記憶體控制器係依據該至少一第二資料區塊之一亂數種子數(randomizer seed)規則，寫入資料至該些複數第一資料區塊。 A flash memory device as described in item 1 of the patent application scope, wherein when writing data to the first data blocks, the flash memory controller writes data to the plurality of first data blocks according to a randomizer seed rule of the at least one second data block. 如申請專利範圍第1項所述之快閃記憶體裝置，其中所產生之該對應的校驗碼係用來更正當寫入該複數群的資料至該複數個第一資料區塊時所發生的錯誤以及用來更正當將該複數個第一資料區塊所儲存之該複數群的資料搬移寫入至該至少一第二資料區塊時所發生的錯誤。 The flash memory device as described in item 1 of the patent application scope, wherein the corresponding checksum generated is used to correct errors that occur when writing the data of the plurality of groups to the plurality of first data blocks and to correct errors that occur when moving the data of the plurality of groups stored in the plurality of first data blocks to the at least one second data block. 一種快閃記憶體儲存管理方法，其係用於一快閃記憶體模組，該快閃記憶體模組包括複數個第一資料區塊以及至少一第二資料區塊，該方法包 含有：將一筆欲寫入之資料分類為複數群的資料；分別將該複數群的資料以及一對應的校驗碼寫入至位於複數個快閃記憶體晶片的該複數個第一資料區塊；以及待完成該複數個第一資料區塊的寫入後，令該快閃記憶體模組將該複數個第一資料區塊所儲存之該複數群的資料以及該對應的校驗碼寫入至該快閃記憶體模組的該至少一第二資料區塊，完成將該筆欲寫入之資料寫到該至少一第二資料區塊之操作；其中當進行記憶體垃圾回收(garbage collection)時，從外部讀取出該複數個第一資料區塊之資料並進行重新編碼與SLC寫入，或從外部讀取出該至少一第二資料區塊並進行重新編碼與SLC寫入。 A flash memory storage management method is used for a flash memory module, the flash memory module includes a plurality of first data blocks and at least one second data block, the method includes: classifying a data to be written into a plurality of groups of data; writing the plurality of groups of data and a corresponding check code into the plurality of first data blocks located in a plurality of flash memory chips respectively; ; and after the writing of the plurality of first data blocks is completed, the flash memory module is made to write the plurality of groups of data stored in the plurality of first data blocks and the corresponding check code into the at least one second data block of the flash memory module, completing the operation of writing the data to be written into the at least one second data block; wherein when performing memory garbage collection, the data of the plurality of first data blocks are read from the outside and re-encoded and SLC written, or the at least one second data block is read from the outside and re-encoded and SLC written. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其中該至少一第二資料區塊為一TLC資料區塊，儲存三個位元的資料，以及將該筆欲寫入之資料分類為該複數群的資料的步驟包括：將該筆欲寫入之資料分類為三個群的資料，以分別寫入至三個SLC資料區塊。 As described in item 7 of the patent application scope, the flash memory storage management method, wherein the at least one second data block is a TLC data block, storing three bits of data, and the step of classifying the data to be written into the plurality of groups of data includes: classifying the data to be written into three groups of data, so as to write them into three SLC data blocks respectively. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其中該複數個第一資料區塊為複數個SLC資料區塊，以及該快閃記憶體儲存管理方法另包括：當寫入一群的資料至一SLC資料區塊時，該快閃記憶體控制器係將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線；對一組奇數組的每一條字元線及一組偶數組的每一條字元線，分別執行不同 M次的互斥或運算的編碼操作，產生該組奇數組的每一條字元線的M個部分校驗碼以及該組偶數組的每一條字元線的M個部分校驗碼；以及寫入並儲存該複數組奇數組的每一條字元線的M個部分校驗碼於該複數組奇數組字元線中最後M條字元線之最後一張資料頁、寫入並儲存該複數組偶數組的每一條字元線的M個部分校驗碼於該複數組偶數組字元線中最後M條字元線之最後一張資料頁。 The flash memory storage management method as described in item 7 of the patent application scope, wherein the plurality of first data blocks are a plurality of SLC data blocks, and the flash memory storage management method further comprises: when writing a group of data to an SLC data block, the flash memory controller classifies all word lines of the SLC data block into a group of word lines in sequence, with each M word lines being grouped to generate a plurality of groups of odd-numbered word lines and a plurality of groups of even-numbered word lines; for each word line of a group of odd-numbered word lines and each word line of a group of even-numbered word lines, , respectively executing M different mutually exclusive or operation encoding operations, generating M partial check codes for each word line of the odd group and M partial check codes for each word line of the even group; and writing and storing the M partial check codes for each word line of the plurality of odd groups in the last data page of the last M word lines of the plurality of odd groups, and writing and storing the M partial check codes for each word line of the plurality of even groups in the last data page of the last M word lines of the plurality of even groups. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其另包含有：當寫入資料至該至少一第二資料區塊且突然發生關機時，放棄該至少一第二資料區塊所儲存之資料，並執行內部複製，從該些複數第一資料區塊搬移寫入資料至該至少一第二資料區塊。 The flash memory storage management method as described in Item 7 of the patent application scope further includes: when data is written to the at least one second data block and a sudden shutdown occurs, the data stored in the at least one second data block is abandoned, and an internal copy is performed to move the written data from the plurality of first data blocks to the at least one second data block. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其另包含有：當寫入資料至該些第一資料區塊時係依據該至少一第二資料區塊之一亂數種子數(randomizer seed)規則來寫入資料至該些複數第一資料區塊。 The flash memory storage management method as described in Item 7 of the patent application scope further includes: when writing data to the first data blocks, the data is written to the plurality of first data blocks according to a randomizer seed rule of the at least one second data block. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其中所產生之該對應的校驗碼係用來更正當寫入該複數群的資料至該複數個第一資料區塊時所發生的錯誤以及用來更正當將該複數個第一資料區塊所儲存之該複數群的資料搬移寫入至該至少一第二資料區塊時所發生的錯誤。 As described in item 7 of the patent application scope, the corresponding checksum generated is used to correct errors that occur when writing the data of the plurality of groups to the plurality of first data blocks and to correct errors that occur when moving the data of the plurality of groups stored in the plurality of first data blocks to the at least one second data block. 一種快閃記憶體控制器，包含： 複數條通道，分別連接至一快閃記憶體模組的複數個快閃記憶體晶片，該快閃記憶體模組包括複數個第一資料區塊以及至少一第二資料區塊；以及一錯誤更正碼編碼電路；其中該快閃記憶體控制器係先將一筆欲寫入之資料分類為複數群的資料，採用該錯誤更正碼編碼電路來分別通過該複數條通道將該複數群的資料以及該對應的校驗碼寫入至位於該複數個快閃記憶體晶片的該複數個第一資料區塊，待完成該複數個第一資料區塊的寫入後，該快閃記憶體控制器令該快閃記憶體模組將該複數個第一資料區塊所儲存之該複數群的資料以及該對應的校驗碼，搬移寫入至該快閃記憶體模組的該至少一第二資料區塊，完成將該筆欲寫入之資料寫到該至少一第二資料區塊之操作；以及，當進行記憶體垃圾回收(garbage collection)時，該快閃記憶體控制器係從外部讀取出該複數個第一資料區塊之資料並進行重新編碼與SLC寫入，或從外部讀取出該至少一第二資料區塊並進行重新編碼與SLC寫入。 A flash memory controller comprises: a plurality of channels, respectively connected to a plurality of flash memory chips of a flash memory module, the flash memory module comprising a plurality of first data blocks and at least one second data block; and an error correction code encoding circuit; wherein the flash memory controller first classifies a data to be written into a plurality of groups of data, and uses the error correction code encoding circuit to write the plurality of groups of data and the corresponding check codes into the plurality of channels respectively. The plurality of first data blocks located in the plurality of flash memory chips, after the writing of the plurality of first data blocks is completed, the flash memory controller instructs the flash memory module to move and write the plurality of groups of data stored in the plurality of first data blocks and the corresponding check code to the at least one second data block of the flash memory module, completing the operation of writing the data to be written to the at least one second data block; and, when performing memory garbage collection, the flash memory controller reads the data of the plurality of first data blocks from the outside and re-encodes and writes them to the SLC, or reads the at least one second data block from the outside and re-encodes and writes them to the SLC.
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