TWI821319B - Integrated cmos source drain formation with advanced control - Google Patents

Abstract

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Description

Integrated CMOS source-drain formation using advanced control methods

Embodiments of the present disclosure generally relate to the fabrication of integrated circuits, and in particular, to apparatus and methods for forming source-drain extensions in finFETs using selective epitaxial growth (SEG).

Transistors are key components of most integrated circuits. Since the drive current of a transistor, and therefore its speed, is proportional to the transistor's gate width, faster transistors usually require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin field-effect transistors (finFETs) have been developed to resolve the conflicting goals of having maximum drive current and minimum size transistors. FinFET is characterized by a fin-shaped channel area that greatly increases the size of the transistor without significantly increasing the area occupied by the transistor, and FinFFT is currently used in many integrated circuits. However, finFETs have their own drawbacks.

Forming horizontal source/drain extensions becomes increasingly difficult for narrow and tall finFETs because the fin channel regions can simply be amorphized or otherwise destroyed by conventional ion implantation techniques such as beamline ion implantation. . Specifically, in some finFET architectures (e.g., horizontal gate all-wound, hGAA), ion implantation can cause severe intermixing between the silicon channel and the adjacent silicon germanium (SiGe) sacrificial layer. Such intermixing is highly undesirable due to the subsequent reduced ability to selectively remove the sacrificial SiGe layer. Additionally, repairing this implant damage via thermal annealing increases the thermal budget of the finFET device.

Furthermore, because the source/drain extensions in a finFET can be covered by other structures, precise placement of the desired dopants in the horizontal source/drain extension regions of the finFET is very difficult at best. For example, (inner) sidewall spacers on a sacrificial SiGe superlattice (SL) layer typically cover the source/drain extensions when doping is performed. Therefore, conventional line-of-sight ion implantation techniques cannot uniformly deposit dopants directly into the finFET source/drain extension regions.

In addition, the time the substrate is exposed to the atmosphere (also known as Q-time) can have a significant impact on the defectiveness of the epitaxial film. As a result, there is a need for processing equipment and techniques for precisely doping the source/drain regions in finFET devices currently available or under development.

One or more embodiments of the present disclosure relate to a method of forming a semiconductor device. An anisotropic etching process is performed on the semiconductor material on the semiconductor substrate to expose surfaces in the semiconductor material. The surface is provided between the existing structure of the semiconductor element and the bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate a distance for forming the cavity. The deposited material layer is formed on the surface of the cavity through a selective epitaxial growth (SEG) process. The substrate does not undergo a pre-cleaning process between cavity formation and SEG.

Additional embodiments of the present disclosure relate to methods of forming semiconductor devices. The semiconductor substrate is positioned within the semiconductor material thereon in the first processing chamber. Anisotropic etching processes are performed on semiconductor materials to expose surfaces in the semiconductor materials. The surface is provided between the existing structure of the semiconductor element and the bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate a distance for forming the cavity. The semiconductor substrate is moved from the first processing chamber to the second processing chamber without exposing the semiconductor substrate to oxidizing conditions. Determines the distance over which the semiconductor material has been recessed after isotropic etching. A layer of deposited material is formed on the cavity surface using a selective epitaxial growth (SEG) process in the second processing chamber. The semiconductor substrate does not undergo a pre-cleaning process between cavity formation and SEG. The SEG process takes into account the distance by which the semiconductor material has been recessed after isotropic etching.

Further embodiments of the present disclosure relate to processing tools for forming semiconductor components. The central transfer station has a plurality of processing chambers arranged around the central transfer station. The robot is housed within a central transfer station and is configured to move substrates between a plurality of processing chambers. The first processing chamber is connected to the central transfer station. The first processing chamber is configured to perform an isotropic etching process. The metrology station is attached to the processing tool and is accessible to the robot. Spend The metrology station is configured to determine the recess distance of the semiconductor material on the substrate from the isotropic etching process. The second processing chamber is connected to the central transfer station. The second processing chamber is configured to perform a selective epitaxial growth (SEG) process. The controller is connected to one or more of the central transfer station, the robot, the first processing chamber, the metrology station, or the second processing chamber. The controller has one or more configurations selected from the group consisting of: a first configuration for moving the substrate on the robot between the plurality of processing chambers and the metrology station; and a configuration for performing each direction on the substrate in the first processing chamber. a second configuration for a isotropic etching process; a third configuration for performing analysis to determine depression of the semiconductor material in the metrology station; or a fourth configuration for performing a selective epitaxial growth process in the second processing chamber, select The epitaxial growth process is adjusted for the depression of semiconductor materials.

Before describing several exemplary embodiments of the present disclosure, it is to be understood that this disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or carried out in various ways.

As used in this specification and the accompanying claims, the term "substrate" refers to the surface, or a portion of a surface, on which a process is performed. As will also be understood by those skilled in the art, reference to a substrate may also refer to only a portion of the substrate unless the context clearly dictates otherwise. Additionally, references to depositing on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

"Substrate" as used herein refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped Silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and/or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in this disclosure, as disclosed in more detail below, any of the film processing steps disclosed may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such as Such substratum as indicated by the context. Thus, for example, where a film/layer or part of a film/layer has already been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

Embodiments of the present disclosure are directed to semiconductor devices, processing tools, and processing methods that include doped semiconductor material formed in a region disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of a semiconductor substrate. In one or more embodiments, the semiconductor devices include finFET devices. In such an embodiment, the n-doped silicon-containing material forms an n-doped source or drain extension that is disposed between the gate spacer of the finFET and the n-doped source or drain extension disposed thereon. The drain extension is provided between the main semiconductor portions of the semiconductor substrate. Although the embodiments of the present disclosure are described with respect to forming nMOS (n-type metal oxide semiconductor) and an n-doped film, those skilled in the art will recognize that a p-doped film can also be formed through a similar process. References to "nMOS" or "n-doped" throughout this disclosure are for simplicity of description only, and this disclosure should not be considered limited to nMOS or n-doped structures. In some embodiments, methods involve forming pMOS (p-type metal oxide semiconductor) or p-doped films. Some embodiments of the present disclosure relate to processes for forming PMOS devices in which the source/drain (SD) includes multiple layers of SiGe and boron. In one or more embodiments, the SD material provides compressive stress to the PMOS device that increases hole mobility. Controlling the amount of lateral push in conjunction with the epitaxial SD layer can affect overall performance.

Figure 1 is a perspective view of a fin-field-effect transistor (finFET) 100 according to an embodiment of the present disclosure. FinFET 100 includes a semiconductor substrate 101, an insulating region 102 formed on the surface of the semiconductor substrate 101, a fin structure 120 formed on the surface of the semiconductor substrate 101, and a gate electrode structure formed on the insulating region 102 and on the fin structure 120. 130. A top portion of fin structure 120 is exposed and electrically coupled to a source contact (not shown) of finFET 100, and the other top portion of fin structure 120 is exposed and electrically coupled to a drain contact (not shown) of finFET 100, And the central portion of the semiconductor fin 121 includes the channel region of the finFET 100 . Gate electrode structure 130 serves as the gate of finFET 100 .

The semiconductor substrate 101 may be a silicon-based (Si)-based substrate, a germanium-based (Ge)-based substrate, a germanium-based silicon (SiGe) based substrate, or the like. Insulation region 102 (also referred to as shallow trench isolation (STI)) may include one or more dielectric materials, such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or other Multiple layers. The insulating region 102 may be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), or similar processes.

Fin structure 120 includes semiconductor fins 121 and fin spacers formed on sidewalls of semiconductor fins 121 (not shown for clarity). Semiconductor fins 121 may be formed from semiconductor substrate 101 or from a different semiconductor material deposited on semiconductor substrate 101 . In the latter case, the different semiconductor materials may include silicon germanium, III-V compound semiconductor materials, or the like.

The gate electrode structure 130 includes a gate electrode layer 131, a gate dielectric layer 132, a gate spacer layer 133, and a mask layer 136. In some embodiments, gate electrode layer 131 includes a polysilicon layer or a metal layer covered with a polysilicon layer. In other embodiments, the gate electrode layer 131 includes a material selected from the group consisting of metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), and molybdenum nitride (MoN _x )), metal carbides (such as Tantalum carbide (TaC) and hafnium carbide (HfC)), metal-nitride-carbide (such as TaCN), metal oxides (such as molybdenum oxide (MoO _x )), metal oxynitrides (such as molybdenum oxynitride (MoO _{x )} N _y )), metal silicides (such as nickel silicide), and combinations thereof. The gate electrode layer 131 may also be a metal layer covered with a polysilicon layer.

Gate dielectric layer 132 may include silicon oxide (SiO _x ), which may be formed by thermal oxidation of semiconductor fins 121 . In other embodiments, gate dielectric layer 132 is formed by a deposition process. Suitable materials for forming gate dielectric layer 132 include silicon oxide, silicon nitride, oxynitride, metal oxides (such as HfO ₂ , HfZrO _x , HfSiO _x , HfTiO _x , HfAlO _x ), and combinations and multilayers thereof. . Gate spacer layers 133 are formed on sidewalls of the gate electrode layer 131 and each may include a nitride portion 134 and/or an oxide portion 135 as shown. In some embodiments, mask layer 136 may be formed over gate electrode layer 131 as shown, and may include silicon nitride.

Figure 2 is a cross-sectional view of a finFET 100 according to an embodiment of the present disclosure. The cross-sectional view shown in Figure 2 is taken at section A-A in Figure 1 . As shown, finFET 100 includes a semiconductor fin 121 having a heavily doped region 201 , a doped extension region 202 , and a channel region 205 . Although embodiments herein are described with respect to nMOS formation, those skilled in the art will recognize that heavily doped region 201 and doped extension region 202 may be p-doped regions.

Heavily doped regions 201 form the source and drain regions of finFET 100 and include relatively high concentrations of n-dopants (eg, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li)) or p-dopants (e.g., boron (B), aluminum (Al), gallium (Ga), or indium (In)). Although region 201 may be referred to as heavily n-doped, those skilled in the art will recognize that this region may be a p-doped region and may include a relatively high concentration of p-dopant, such as boron (B). For example, in some embodiments, the dopant concentration in heavily doped region 201 may be as high as 5x10 ²¹ atoms/cm ³ . In some embodiments, heavily doped region 201 has a dopant concentration in the range of about 1×10 ²⁰ atoms/cm ³ to about 1×10 ²² atoms/cm ³ . Heavily doped region 201 can be created by any suitable doping technique. Because the heavily doped region 201 is typically not covered by the central structure of the finFET 100 when doped, line-of-sight doping techniques such as beamline ion implantation can be used. Alternatively, since a major portion of each heavily doped region 201 is typically exposed upon doping, conformal doping techniques such as plasma doping (PLAD) may be used to form the heavily doped regions 201 .

Doped extension regions 202 form the source and drain extensions of finFET 100 and include one or more n dopants. Those skilled in the art will recognize that the extension region may be a p-doped region. According to embodiments of the present disclosure, doped extension region 202 includes one or more n-dopants that serve as a diffusion barrier for the n-dopants located in heavily doped region 201 . Therefore, because the doped extension region 202 is disposed between the channel region 205 and the heavily doped region 201 , the n-dopant (such as phosphorus) located in the heavily doped region 201 cannot diffuse into the channel region 205 . With the small geometries associated with modern finFET devices, the width 133A of the gate spacer 133 (which is also close to the distance between the heavily doped regions 201) can be only a few nanometers. Thus, such n-dopant diffusion can be a serious challenge in nMOS devices such as finFET 100. In some embodiments, doped extension region 202 includes one or more heavier mass atoms (eg, Ge, Sn, etc.) that increase compressive stress in channel region 205 .

In some embodiments, the n-dopant located in heavily doped region 201 may include phosphorus. In such an embodiment, the n-dopant included in doped extension region 202 may include arsenic (As), which may act as a primary diffusion barrier to phosphorus diffusion or simply as a spatial (geometric) offset. Alternatively or additionally, in such embodiments, the n-dopant included in doped extension region 202 may include antimony (Sb), which may also serve as a partial barrier to phosphorus diffusion. In some embodiments, p-dopants included in regions 201 and 202 may independently include one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In).

In some embodiments, doped extension region 202 is formed with a thickness 202A that is less than width 133A of gate spacer layer 133 . For example, in such embodiments, thickness 202A of doped extension region 202 may be approximately 1 nanometer less than width 133A. Therefore, in such an embodiment, doped extension region 202 does not extend into channel region 205 .

Furthermore, according to embodiments of the present disclosure, the doped extension region 202 is formed through a (SEG) process. Specifically, the cavity is formed in a portion of the semiconductor fin 121 that is disposed between the gate spacer 133 and the bulk semiconductor portion of the semiconductor substrate 101 . The cavity is then filled with an n- or p-doped semiconductor material, such as a silicon material doped with arsenic (As) (eg, also referred to herein as Si:As) or a silicon material doped with boron (B) (eg, This article also refers to Si:B). Therefore, the source-drain extension for the finFET 100 is formed in the region of the semiconductor fin 121 , which is tied between the existing structure of the semiconductor fin 121 and the bulk semiconductor portion of the semiconductor substrate 101 . Additionally, the n-dopants included in doped extension region 202 may be selected to act as a diffusion barrier for the n-dopants located in heavily doped region 201 . Note that due to the presence of the gate spacer layer 133, the doped extension region 202 cannot be formed by beamline ion implantation or PLAD. Various embodiments in which doped extension region 202 may be formed in finFET 100 are described below in conjunction with FIG. 3 and FIGS. 4A-4E.

Figure 3 is a flow diagram of a manufacturing process 300 for forming nMOS finFETs in accordance with various embodiments of the present disclosure. Those skilled in the art will recognize that pMOS finFETs can be formed using similar manufacturing processes. 4A to 4E are schematic cross-sectional views of a semiconductor device (such as the finFET 100 in FIG. 1 ) corresponding to various stages of the process 300 according to various embodiments of the present disclosure. Although process 300 is shown for forming doped extension regions, process 300 may be used to form other structures on a substrate.

The process 300 begins with operation 301 , as shown in FIG. 4A , where a gate electrode structure 130 and a gate spacer layer 133 are formed on the semiconductor fin 121 . In the embodiment shown in FIG. 4A , semiconductor fins 121 are formed from a portion of semiconductor substrate 101 .

In operation 302 , an anisotropic etching process is performed on the portion of the semiconductor fin 121 disposed between the gate spacer 133 and the bulk semiconductor portion of the semiconductor substrate 101 . Thus, as shown in Figure 4B, one or more sidewall surfaces 401 in the semiconductor material of semiconductor fin 121 are exposed. As shown, sidewall surface 401 is disposed between the existing structure of finFET 100 and the bulk semiconductor portion of semiconductor substrate 101 . That is, the sidewall surface 401 is provided between the gate spacer layer 133 and the semiconductor substrate 101 . Therefore, the sidewall surface 401 is in an area of the semiconductor fin 121 that is inaccessible to conventional, surface-standard line-of-sight ion implantation techniques.

The anisotropic etch process of operation 302 may be selected to remove sufficient material from semiconductor fin 121 such that sidewall surface 401 has any suitable target length 401A. For example, in some embodiments, the anisotropic etching process of operation 302 is performed such that the sidewall surface 401 has a target length 401A of about 5 nm to about 10 nm. In other embodiments, sidewall surface 401 may have a thickness greater than 10 nm depending on the geometry of gate spacer 133, the concentration of n-dopants in heavily doped region 201, the size of channel region 205, and other factors. or target length less than 5 nm 401A. The anisotropic etching process of operation 302 may be, for example, a deep reactive-ion etch (DRIE) process, during which the gate spacer 133 and other portions of the finFET 100 are masked.

In operation 303 , as shown in FIG. 4C , an isotropic etch process is performed on sidewall surface 401 to form one or more cavities 402 in the material of semiconductor fin 121 . As shown, each cavity 402 has a surface 403 . Additionally, each cavity 402 is provided between the existing structure of the finFET 100 (ie, one of the gate spacers 133 ) and the bulk semiconductor portion of the semiconductor substrate 101 . Therefore, portions of cavity 402 are located in areas of semiconductor fin 121 that are inaccessible to line-of-sight ion implantation techniques.

The isotropic etch process of operation 303 may be selected to remove sufficient material from semiconductor fin 121 such that cavity 402 has any suitable target width 402A. For example, in some embodiments, the isotropic etch process of operation 303 is performed such that cavity 402 has a target width 402A of about 2 nm to about 10 nm. In other embodiments, sidewall surface 401 may have a diameter greater than 10 nm or less than Target width 402A of 2nm. For example, in some embodiments, target width 402A may be selected such that cavity 402 has a target width 402A that is no more than about 1 nm less than width 133A of gate spacer layer 133 .

The isotropic etching process of operation 303 may include any suitable etching process that is selective to the semiconductor material of the semiconductor fins 121 . For example, when the semiconductor fin 121 includes silicon (Si), the isotropic etching process of operation 303 may include a chemical vapor etch (CVE) process based on HCl, a CVE process based on HCl and GeH ₄ , and/ or one or more _Cl2- based CVE processes. In some embodiments, the isotropic etching process of operation 303 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 303 includes a dry etching process.

In some embodiments, optional operation 304 is performed in which a pre-deposition cleaning process or other surface preparation process is performed on surface 403 of cavity 402 . A surface preparation process may be performed to remove native oxide on surface 403 and prior to the (SEG) process performed in operation 305 Prepare surface 403 in other ways. The surface preparation process includes a dry etching process, a wet etching process, or a combination of the two.

In such embodiments, the dry etching process may include conventional plasma etching, or a remote plasma-assisted dry etching process, such as the SiCoNi ^™ etch process available from Applied Materials, Inc. of Santa Clara, California. During the SiCoNi ^™ etching process, surface 403 is exposed to H ₂ , NF ₃ , and/or NH ₃ plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, surface 403 may experience simultaneous exposure to _H2 , _NF3 , and _NH3 plasmas. The SiCoNi ^™ etch process of operation 304 can be performed in a SiCoNi pre-cleaned chamber that can be integrated into one of a variety of multi-processing platforms, including Centura ^™ , Dual ACP, Producer ^™ GT and Endura available from Applied Materials platform. The wet etching process may include a hydrofluoric (HF) acid last process, a so-called "HF last" process, in which an HF etch of surface 403 is performed such that the surface 403 is hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed in operation 304 . In some embodiments, the process includes sublimation etching for native oxide removal. Etching processes can be plasma or thermal based. The plasma process can be any suitable plasma (eg, conductive coupled plasma, inductively coupled plasma, microwave plasma).

In some embodiments, the apparatus or processing tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer, and no pre-epitaxial pre-cleaning process is used. In such embodiments, the processing tool is configured to The substrate is moved from the etching process chamber to the epitaxy chamber without exposing the substrate to atmospheric conditions.

In operation 305 , as shown in FIG. 4D , a selective epitaxial growth (SEG) process is performed on surface 403 to grow a layer of deposition material 406 , thereby forming doped extension region 202 . Specifically, deposition materials include semiconductor materials, such as silicon, and n-type dopants. For example, in some embodiments, deposition material 406 includes Si:As, where the arsenic concentration in deposition material 406 is selected based on the electrical needs of finFET 100 . Note that Si:As can be deposited via (SEG) with electrically active dopant concentrations of arsenic up to about ^5x10 atoms/ ^cm3 . However, such high arsenic concentrations present in doped extension region 202 can result in increased resistivity due to the undesirable formation of AsV (arsenic-vacancy) complexes, and diffusion of arsenic into channel region 205 . Additionally, AsPV (arsenic-phosphorus-vacancy) complexes may form in doped extension region 202 , resulting in increased phosphorus diffusion into channel region 205 . Accordingly, in some embodiments, deposited material 406 includes ^an arsenic electrically active dopant concentration of no greater than about ^5x10 atoms/cm.

In some embodiments, the deposited material 406 may have a deposited thickness 406A of about 2 nm to about 10 nm. In other embodiments, the deposited material 406 may have a deposited thickness 406A thicker than 10 nm for certain configurations of the finFET 100 . In some embodiments, as shown in Figure 4D, deposition thickness 406A is selected such that deposition material 406 completely fills cavity 402. In other embodiments, deposition thickness 406A is selected such that deposition material 406 partially fills cavity 402 and covers the exposed surface of semiconductor fin 121 forming cavity 402 .

Suitable SEG processes in operation 305 may include specific processing temperatures and pressures, processing gases, and gas flows selected to promote selective growth of specific n-doped or p-doped semiconductor materials. In embodiments where the particular n-doped semiconductor material includes Si:As, the doping gas used in the SEG process of operation 305 may include AsH ₃ , As(SiH ₃ ) ₃ , AsCl ₃ , or tert-butylarsine. (tertiarybutylarsine; TBA). Other gases used in the SEG process may include dichlorosilane (DCS), HCl, SiH ₄ , Si ₂ H ₆ , and/or Si ₄ H ₁₀ . In such an embodiment, the SEG process of operation 305 may be performed in an atmospheric or subatmospheric pressure chamber, which has a low H ₂ carrier gas flow. For example, in such embodiments, the process pressure in the processing chamber performing the SEG process may be on the order of approximately 20-700 T. In such embodiments, high reactor pressure and low dilution (due to low carrier gas flow) can produce high arsenic and high dichlorosilane (H ₂ SiCl 2 or DCS) partial pressures, thus facilitating the production of high arsenic and high dichlorosilane (H 2 SiCl ₂ or DCS) partial pressures during the SEG process. Surface 403 removes chlorine (Cl) and excess arsenic. Therefore, high film growth rates and associated high arsenic integration rates are achieved, and good crystal quality can be obtained. In some embodiments, the doping gas used provides a p-doped semiconductor material. In some embodiments, the p-doped semiconductor material includes one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the doping precursor includes one or more of borane, diborane, or plasma thereof.

The SEG process of operation 305 may be performed in any suitable processing chamber, such as a processing chamber integrated into one of various multi-processing platforms, including the Producer ^™ GT, Centura ^™ available from Applied Materials, Inc. AP and Endura platforms. In such an embodiment, the SiCoNi ^™ etch process of operation 304 may be performed in another chamber of the same multi-processing platform.

In operation 306, as shown in Figure 4E, a second SEG process is performed in which heavily doped region 201 is formed. Heavily doped region 201 is formed over doped extension region 202 . Heavily doped region 201 may be formed from any suitable semiconductor material, including doped silicon, doped silicon germanium, doped silicon carbon, or the like. The one or more dopants may include any suitable n-dopant, such as phosphorus. For example, in some embodiments, heavily doped region 201 may include phosphorus-doped silicon (Si:P). Any suitable SEG process may be used to form heavily doped region 201 . The thickness and other film characteristics of the heavily doped region 201 may be selected based on the electrical requirements of the finFET 100, the size of the finFET 100, and other factors.

In some embodiments, the second SEG process is performed in the same processing chamber as the SEG process of operation 305 . Thus, doped extension region 202 may be formed in an actual preliminary deposition step during formation of heavily doped region 201 . Therefore, in such embodiments, a dedicated processing chamber is not required to form doped extension region 202, and the need for transferring the substrate from the first processing chamber (the SEG used to perform doped extension region 202) to the second processing chamber is avoided. Additional time for the second processing chamber (used to perform SEG of heavily doped region 201). Furthermore, in such embodiments, deposition material 406 is not exposed to air. Alternatively, in some embodiments, the second SEG process is performed in a different processing chamber than the SEG process of operation 305, thereby reducing the number of processing chambers exposed to harmful dopants, such as arsenic. In such an embodiment, both chambers may be integrated into the same multi-processing platform, thereby avoiding vacuum disruption and exposure of deposition material 406 to air.

Following operation 306, the remaining components of finFET 100 may be completed using conventional manufacturing techniques.

Embodiments of process 300 enable formation of doped extension regions 202 in precisely defined locations (ie, in areas of semiconductor fin 121 that are difficult to reach using conventional ion implantation techniques). Additionally, the process of forming doped extension regions 202 may be integrated into existing selective epitaxial growth steps already employed in fabricating finFETs, thereby minimizing or eliminating interference with the process flow used to form finFETs. Additionally, avoid implant damage (i.e., defects from heavy mass ion implantation, such as silicon interstitiality or even silicon amorphization), and any detrimental effects between such crystal defects and high concentrations of arsenic and/or phosphorus. interaction. As a result, there is no need for process-impacting post-implantation annealing or associated additional thermal budget. Furthermore, because no vacuum breach occurs between the deposition of doped extension region 202 and heavily doped region 201 , when performing the SEG process in operation 306 in the same processing chamber, or in a different processing chamber on the same multi-processing platform When performing the SEG process of Operation 305 in the chamber, additional material losses related to pre-cleaning are also avoided.

As is well known in the art, introducing tensile strain into the channel region of an nMOS finFET can increase charge mobility in the nMOS finFET. Additionally, as described herein, the pass adjacent semiconductor fin 121 Forming the channel region 205 from an epitaxially grown Si:As material can introduce significant tensile strain in the channel region 205 . For example, in accordance with some embodiments of the present disclosure, the n-doped extension region may be deposited at an arsenic concentration sufficient to create targeted tensile strain within the doped extension region 202 . Thus, in embodiments in which the deposited material 406 includes epitaxially grown Si:As, the doped extension region 202 is formed in the finFET 100 due to the tensile strain introduced in the channel region 205 by forming the n-doped stretch region. An additional benefit is that channel region 205 may have improved charge mobility. In some embodiments, for example, germanium (Ge), antimony (Sb), and/or tin (Sn) are doped into the p-doped extension to provide compressive stress to the channel.

In some embodiments, an optional carbon-containing layer is formed in cavity 402. In such an embodiment, the carbon-containing layer may be a liner between doped extension region 202 and heavily n-doped region 201 . One such embodiment is shown in Figure 5 .

Figure 5 is a schematic cross-sectional view of finFET 100 after forming cavity 402 in accordance with various embodiments of the present disclosure. As shown, a carbon-containing layer 501 is deposited on surface 407 of deposition material 406 . The presence of carbon (C) enhances arsenic diffusion while reducing phosphorus diffusion. Accordingly, in some embodiments, carbon-containing layer 501 includes between about 0.5% and about 1.0% carbon. In such embodiments, the carbon-containing layer 501 may further include phosphorus, for example, between about 1×10 ²⁰ atoms/cm ³ and about 5×10 ²⁰ atoms/cm ³ . Such carbon-containing layers may be grown in an atmospheric or near-atmospheric SEG chamber at a processing temperature of approximately 650°C ± 50°C. Therefore, in an embodiment in which the carbon-containing layer 501 includes Si:C:P, the formation includes Si:P (heavily n-doped region 201), Si:C:P (carbon-containing layer 501), and Si:As (heavily n-doped region 201). The three-layer structure of the mixed extension region 202). Such a three-layer structure may cause arsenic to diffuse away from the channel region 205 and toward the heavily n-doped region 201 .

In some embodiments, n-doped semiconductor material can be formed as part of the nanowire structure in regions of the nanowire structure that are not accessible via conventional ion implantation techniques. Forming such an embodiment is described below in conjunction with Figure 6 and Figures 7A to 7E.

Figure 6 is a flow diagram of a manufacturing process 600 for forming a nanowire structure 700 in accordance with various embodiments of the present disclosure. 7A to 7E are schematic cross-sectional views of the nanowire structure 700 corresponding to various stages of the process 600 according to embodiments of the present disclosure. Although process 600 is depicted as being used to form n-doped regions in a nanowire structure, process 600 may be used to form other structures on a substrate.

Process 600 begins with operation 601, as shown in FIG. 7A, in which alternating silicon layers 710 and silicon germanium (SiGe) layers are formed on a host semiconductor substrate 701. Bulk semiconductor substrate 701 may be formed from silicon, silicon germanium, or any other suitable bulk crystalline semiconductor material. Silicon layer 710 and germanium-silicon layer 720 may each be formed via a SEG process and typically include crystalline semiconductor materials.

In operation 602, as shown in FIG. 7B, the silicon layer 710 and the germanium silicon layer 720 are patterned and etched to expose the vertical sidewalls 711 on the silicon layer 710 and the vertical sidewalls 721 on the germanium silicon layer 720. In some embodiments, operation 602 includes a DRIE process.

In operation 603, as shown in FIG. 7C, germanium silicon layer 720 is selectively etched inwardly from vertical sidewalls 721 to form cavity 706. In some embodiments, a chemical vapor etching (CVE) process is used to selectively remove the silicon germanium layer 720 relative to the silicon layer 710 . For example, gaseous hydrochloric acid selective etching of SiGe relative to Si in a reduced pressure chemical vapor deposition reactor has been described. Alternatively, ex-situ HF impregnation followed by _GeH4- enhanced Si etch performed in-situ in an epitaxial reactor may be employed in operation 603.

In operation 604, as shown in Figure 7D, low dielectric constant material 704 is then conformally deposited on host semiconductor substrate 701. Low dielectric constant material 704 fills at least a portion of cavity 706 .

In operation 605, as shown in Figure 7E, low-k material 704 is patterned and etched to expose vertical sidewalls 711 on silicon layer 710 and filled cavities 706 on germanium silicon layer 720. In some embodiments, operation 605 includes a DRIE process. The filled cavities 706 form spacer layers 702 , with each spacer layer 702 being formed at an edge region 705 of the germanium silicon layer 720 .

In operation 606, portions of silicon layer 710 are selectively removed from edge region 705 to form cavity 706, as shown in Figure 7F. Silicon may be removed from edge region 705 via a CVE process, such as a CVE process that is selective for silicon relative to spacer layer 702 . In some embodiments, the CVE process may include one or more of an HCl-based CVE process, an HCl and GeH ₄ -based CVE process, and/or a Cl ₂ -based CVE process.

In operation 607, as shown in Figure 7G, n-doped silicon material 718 is grown in cavity 706 via a SEG process. In some embodiments, the n-dopant is arsenic and the n-doped silicon material includes Si:As. In such an embodiment, the SEG process of operation 605 may be substantially similar to the SEG process of operation 305 of process 300 described above.

In an alternative embodiment, spacer layer 702 may be formed by selectively oxidizing portions of germanium-silicon layer 720 rather than selectively etching portions of germanium-silicon layer 720 that are subsequently filled with low-k material 704 .

Embodiments of process 600 enable the formation of a nanowire structure 700 that includes a doped region, ie, a cavity 706 filled with n-doped silicon material 718 . Note that since the cavity 706 is disposed between the existing structure of the nanowire structure 700 and the main semiconductor portion of the semiconductor substrate 701, the doped region described above cannot be accessed by line-of-sight ion implantation techniques. Therefore, such a doped region cannot be formed by conventional techniques.

Figure 8 illustrates another embodiment of the present disclosure. Those skilled in the art will recognize that method 800 illustrated in Figure 8 may be combined with process 300 or process 600. Referring to Figure 8 and Figures 4A through 4E, method 800 begins at 801 where a semiconductor substrate is provided for processing. A semiconductor substrate has semiconductor material thereon. As used in this specification and accompanying claims, the term "providing" means placing a substrate into a position for processing. For example, the substrate may be placed within a first processing chamber for processing.

In operation 802, an anisotropic etching process is performed on the semiconductor material on the semiconductor substrate. Anisotropic etching processes expose surfaces in semiconductor materials. In some embodiments, operation 802 is not performed. The exposed surface of some embodiments is disposed between the existing structure of the semiconductor element and the bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed.

At operation 803, an isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the substrate. The side walls are recessed a distance to form a cavity. The amount of sidewall recess may vary based on, for example, isotropic etching conditions.

At operation 804, the distance to which the semiconductor material has been recessed by the isotropic etching process is determined. The recess distance may be measured by any suitable technique known to those skilled in the art. In some embodiments, the recess distance is determined by refraction.

In operation 805, a layer of deposited material is formed on the cavity surface through a selective epitaxial growth (SEG) process. Some embodiments have substrates that do not undergo a pre-cleaning process between cavity formation and SEG. In some embodiments, the substrate is not exposed to atmospheric or oxidizing conditions between forming the cavity and the SEG process.

The SEG process of some embodiments is adjusted based on recess distance by a predetermined method. For example, if a predetermined method is configured for a recess depth of 5 Å and the actual measured recess depth is 6 Å, the SEG conditions can be changed to grow enough film to make up for the difference. In some embodiments, the SEG process is tuned to perform more than one type of growth. For example, if the recess depth is greater than a predetermined limit, the SEG process may begin by depositing silicon before forming the doped deposition material.

In one or more embodiments, operations 803, 804, and 805 are integrated using advanced process control (APC). As used herein, the term "integrated" means that lateral pushing and epitaxial growth are performed in the same platform (under vacuum processing). At operation 804, the integrated metric may be used to determine the amount of recess distance. In some embodiments, integrated metrology is performed in situ. Once the recess distance has been determined by integrated metrology, the measurement results are fed to the epitaxial tool so that compensation can be performed (eg, the thickness/composition of the first epitaxial layer can thereby be adjusted). In some embodiments, advanced processing controls include one or more of scatterometry (ie, optical critical dimension (OCD) measurements), refraction, ellipsometry, or electron beam.

Referring to Figure 9, additional embodiments of the present disclosure relate to a processing tool 900 for performing the methods described herein. Figure 9 illustrates a system 900 that may be used to process substrates in accordance with one or more embodiments of the present disclosure. System 900 may be referred to as a cluster tool. System 900 includes a central transfer station 910 having a robot 912 therein. Robot 912 is shown as a single-leaf robot; however, those skilled in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. Robot 912 is configured to move one or more substrates between chambers connected to central transfer station 910 .

At least one pre-cleaning/buffering chamber 920 is connected to the central transfer station 910 . Preclean/buffer chamber 920 may include one or more of a heater, radical source, or plasma source. The preclean/buffer chamber 920 may be used as a holding area for individual semiconductor substrates or wafer cassettes for processing. The pre-clean/buffer chamber 920 may perform a pre-clean process or may preheat the substrate for processing or may simply be a staging area for processing sequences. In some embodiments, there are two pre-cleaning/buffering chambers 920 connected to the central transfer station 910.

In the embodiment shown in Figure 9, a pre-cleaning chamber 920 may be used as a pass-through chamber between the factory interface 905 and the central transfer station 910. Factory interface 905 may include one or more robots 906 for moving substrates from cassettes to pre-clean/buffer chamber 920. The robot 912 may then move the substrates from the pre-clean/buffer chamber 920 to other chambers within the system 900 .

The first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etch chamber and may be in fluid communication with one or more reactive gas sources to provide one or more streams of reactive gases to the first processing chamber 930 . Substrates may be moved to and from the deposition chamber 930 by the robot 912 passing through the isolation valve 914 .

Processing chamber 940 may also be connected to central transfer station 910. In some embodiments, processing chamber 940 includes an isotropic etch chamber and is in fluid communication with one or more reactive gas sources to provide a flow of reactive gases to processing chamber 940 to perform an isotropic etch process. Substrates may be moved to and from the deposition chamber 940 by the robot 912 passing through the isolation valve 914 .

Processing chamber 945 may also be connected to central transfer station 910. In some embodiments, processing chamber 945 is the same as processing chamber 940 are of the same type and configured to perform the same process as processing chamber 940 . This arrangement may be useful in situations where the process occurring in processing chamber 940 takes a very long time compared to the process in processing chamber 930 .

In some embodiments, processing chamber 960 is connected to central transfer station 910 and is configured to function as a selective epitaxial growth chamber. Processing chamber 960 may be configured to perform one or more different epitaxial growth processes.

In some embodiments, the anisotropic etch process occurs in the same processing chamber as the isotropic etch process. In such embodiments, processing chamber 930 and processing chamber 960 may be configured to perform etching processes on two substrates simultaneously, and processing chamber 940 and processing chamber 945 may be configured to perform selective epitaxial growth. process.

In some embodiments, each of processing chambers 930, 940, 945, and 960 is configured to perform a different portion of the processing method. For example, processing chamber 930 can be configured to perform an anisotropic etch process, processing chamber 940 can be configured to perform an isotropic etch process, and processing chamber 945 can be configured to be a metrology station or to perform first selective epitaxy. growth process, and processing chamber 960 may be configured to perform a second epitaxial growth process. Those skilled in the art will recognize that the number and arrangement of individual processing chambers on the tool may vary, and that the embodiment shown in Figure 9 represents only one possible configuration.

In some embodiments, processing system 900 includes one or more metrology stations. For example, the metrology station may be located within the pre-cleaning/buffering chamber 920, the central transfer station 910, or any separate processing chamber. The metrology station can be located anywhere within the system 900, which allows measurement of recess distance without exposing the substrate to an oxidizing environment.

At least one controller 950 is coupled to one or more of central transfer station 910 , preclean/buffer chamber 920 , processing chamber 930 , 940 , 945 , or 960 . In some embodiments, there are more than one controller 950 connected to individual chambers or stations, and a primary control processor is coupled to each of the individual processors to control system 900. Controller 950 may be one of any form of general purpose computer processor, microcontroller, microprocessor, etc. that may be used in an industrial environment to control various chambers and sub-processors.

At least one controller 950 may have a processor 952, memory 954 coupled to the processor 952, input/output components 956 coupled to the processor 952, and support circuitry 958 to communicate between the various electronic components. Memory 954 may include one or more of temporary memory (eg, random access memory) and non-transitory memory (eg, storage).

The processor's memory 954 or the computer-readable medium may be one or more of readily available memories, such as random access memory (RAM), read-only memory (ROM) ), floppy disk, hard disk, or any other form of digital storage (local or remote). Memory 954 may store a set of instructions that may be operated by processor 952 to control parameters and components of system 900 . Support circuitry 958 is coupled to CPU 952 for supporting the processor in a conventional manner. For example, circuitry may include cache memory, power supplies, clock circuits, input/output circuits, subsystems, and the like.

The process may typically be stored in memory as a software routine that, when executed by a processor, causes the processing chamber to perform the process of the present disclosure. Software routines may also be stored and/or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of this disclosure may also be executed in hardware. Thus, processes may be implemented in software and executed in hardware using a computer system, as, for example, application specific integrated circuits or other types of hardware implementations, or as a combination of software and hardware. When executed by the processor, the software routines convert a general-purpose computer into a special-purpose computer (controller) that controls chamber operations so that the process can be performed.

In some embodiments, controller 950 has one or more structures for performing independent processes or sub-processes to perform methods. The controller 950 may be connected to or configured to operate the intermediary components to perform the functions of the method. For example, the controller 950 may be connected to and configured to control one or more of a gas valve, actuator, motor, slit valve, vacuum control, etc. One or more of the controls, etc.

The controller 950 of some embodiments has one or more configurations selected from: a configuration for moving a substrate on a robot between a plurality of processing chambers and metrology stations; a configuration for performing an anisotropic etching process on a substrate. Configuration; configuration for performing an isotropic etching process on a substrate in a processing chamber; configuration for performing analysis to determine depression of semiconductor material in a metrology station; configuration for performing selective epitaxy in an epitaxial chamber A structure for a crystal growth process; a structure for adjusting the selective epitaxial growth process scheme to account for recesses in the semiconductor material; a structure for performing a bulk selective epitaxial growth process; and a structure for loading and/or unloading substrates from the system Construct.

In summary, one or more embodiments of the present disclosure provide systems and techniques for forming regions of doped semiconductor material in existing structures of semiconductor devices and forming bulk semiconductors of doped silicon-containing semiconductor substrates thereon. Set between sections. In embodiments where the semiconductor device includes a finFET device, the doped semiconductor material forms a doped source and/or drain extension that is disposed between the gate spacer of the finFET and the doped The source or drain extends between the main semiconductor portion of the semiconductor substrate.

Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic is described in connection with the embodiment. Included in at least one embodiment of the present disclosure. Accordingly, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification is not necessarily refer to the same embodiments of the present disclosure. Additionally, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the disclosure. Those skilled in the art will appreciate that various modifications and variations can be made in the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the present disclosure may include modifications and changes within the scope of the appended claims and their equivalents.

100: Fin field effect transistor 101:Semiconductor substrate 102: Insulation area 120: Fin structure 121:Semiconductor fin 130: Gate electrode structure 131: Gate electrode layer 132: Gate dielectric layer 133: Gate spacer layer 133A:Width 134:Nitride part 135: Oxide part 136:Mask layer 201:Heavily doped area 202: Doped extension region 202A:Thickness 205: Channel area 300:Process 301: Operation 302: Operation 303: Operation 304: Operation 305: Operation 306: Operation 401: Side wall surface 401A: Target length 402:Cavity 402A: Target width 403: Surface 406: Deposited Materials 406A: Deposition thickness 407: Surface 501:Carbon layer 600:Process 601: Operation 602: Operation 603: Operation 604: Operation 605: Operation 606: Operation 607: Operation 700: Nanowire structure 701:Main semiconductor substrate 702: Spacer layer

704: Low dielectric constant materials

705: Edge area

706:Cavity

710:Silicon layer

711:Vertical side wall

718:Silicon material

720: Germanium silicon layer

721:Vertical side wall

800:Method

801: Operation

802: Operation

803: Operation

804: Operation

805: Operation

900: Processing tools

905:Factory interface

906:Robot

910:Central delivery station

912:Robot

914:Isolation valve

920: Pre-clean/buffer chamber

930:Deposition chamber

940: Processing chamber

945:Processing Chamber

950:Controller

952: Processor

954:Memory

956:Input/output components

958:Support circuit

960:Processing chamber

In order that the manner in which the above-described features of the disclosure may be characterized may be understood in detail, a more particular description of the disclosure briefly summarized above may be made with reference to the embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only common embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Figure 1 is a perspective view of a fin field effect transistor (finFET) according to one or more embodiments of the present disclosure; Figure 2 is a cross-section of the finFET of Figure 1 according to one or more embodiments of the present disclosure. Figure; Figure 3 is a flow chart of a manufacturing process for forming finFETs according to one or more embodiments of the present disclosure;

4A to 4E illustrate schematic cross-sectional views of semiconductor devices corresponding to various stages of the process of FIG. 3 according to one or more embodiments of the present disclosure;

Figure 5 is a schematic cross-sectional view of the finFET of Figure 1 after forming a cavity in accordance with one or more embodiments of the present disclosure;

Figure 6 is a flow chart of a manufacturing process for forming a nanowire structure according to one or more embodiments of the present disclosure;

Figures 7A to 7G are schematic cross-sectional views of the nanowire/nanosheet structure of Figure 7 corresponding to various stages of the process of Figure 6 in accordance with one or more embodiments of the present disclosure;

Figure 8 is a flow diagram of a manufacturing process for forming a semiconductor device according to one or more embodiments of the present disclosure; and

Figure 9 illustrates a schematic diagram of a processing system for performing any embodiments of the present disclosure.

100: Fin field effect transistor (finFET)

101:Semiconductor substrate

130: Gate electrode structure

131: Gate electrode layer

132: Gate dielectric layer

133: Gate spacer layer

133A:Width

134:Nitride part

135: Oxide part

136:Mask layer

406: Deposited Materials

407: Surface

501:Carbon layer

Claims (16)

A method of forming a semiconductor device, the method includes the following steps: performing an anisotropic etching process on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material, the surface being on an existing surface of the semiconductor device. disposed between a structure and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed; performing an isotropic etching process on an exposed sidewall to dispose between the existing structure and the bulk semiconductor portion of the semiconductor substrate The semiconductor material is recessed a distance to form a cavity; determining the distance that the semiconductor material has been recessed after isotropic etching; forming a deposited material on a surface of the cavity via a selective epitaxial growth (SEG) process a layer, the semiconductor substrate does not undergo a pre-cleaning process between forming the cavity and the SEG; the SEG process is adjusted based on the distance that the semiconductor material has been recessed; and through a selective epitaxial growth (SEG) process A doped region is formed on the layer of deposited material, wherein the doped region includes one or more of the following: phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li), Boron (B), aluminum (Al), gallium (Ga) and indium (In), the doped region has a dopant in a range of about 1x10 ²⁰ atoms/cm ³ to about 1x10 ²² atoms/cm ³ concentration, wherein the isotropic etching process and the SEG process are performed in a single platform under vacuum processing. The method of claim 1, wherein the isotropic etching occurs in a first processing chamber, and the method further includes the step of: moving the substrate from the first processing chamber to a second processing chamber room for this SEG process. The method of claim 1, further comprising the step of epitaxially growing a portion of the semiconductor material prior to forming the layer of deposited material. The method of claim 1, wherein the distance at which the semiconductor material has been recessed is determined by refraction. The method of claim 1, wherein the isotropic etching process includes an etching process that is selective to the semiconductor material. The method of claim 5, wherein the isotropic etching process includes a chemical vapor etching process, and the chemical vapor etching process includes exposing the exposed sidewall to at least one of HCl, GeH ₄ , or Cl ₂ . The method of claim 1, wherein forming the layer of deposited material includes filling the cavity with the deposited material. The method as described in request 1 further includes the following steps In a step, before forming the layer of deposited material, a carbonaceous material is deposited on the surface of the cavity, wherein the carbonaceous material includes a silicon carbon phosphorus (SiCP) material. The method of claim 8, wherein the SiCP material includes carbon in the range of about 0.1 to 2.0 atomic % and phosphorus in the range of about 1×10 ²⁰ atoms/cm ³ to 1×10 ²¹ atoms/cm ³ . The method of claim 1, wherein performing the isotropic etching process on the exposed sidewall to form the cavity in the semiconductor material includes the following steps: removing the semiconductor material until a phosphorus-doped layer is exposed. A portion of the semiconductor material that is a hybrid host semiconductor material. The method of claim 1, wherein the deposition material includes an n-type dopant, the n-type dopant includes arsenic (As), and the selective epitaxial growth (SEG) process includes the following steps: The surface _of the cavity is exposed to at least one of _AsCl3 , TBA, or _AsH3 and at least one of dichlorosilane (DCS), HCl, _{SiH4 , Si2H6} , or _Si4H10 . The method of claim 11, wherein the step of forming the layer of deposited material includes the step of filling the cavity with an arsenic-doped material, the arsenic-doped material having sufficient properties to create a targeting within the deposited material. Tensile strain of arsenic concentration. The method of claim 1, wherein the deposition material includes a p-type dopant, the p-type dopant includes boron (B), and the selective epitaxial growth (SEG) process includes the following steps: The surface of the cavity is exposed to one or more of borane, diborane, or plasma of borane or diborane. The method of claim 1, wherein the layer of additional deposition material is formed without exposing the layer of deposition material formed on the surface of the cavity to air. A method of forming a semiconductor device, the method comprising the following steps: positioning a semiconductor substrate with a semiconductor material thereon in a first processing chamber; performing an anisotropic etching process on the semiconductor material to expose the semiconductor material a surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed; performing an isotropic etching process on an exposed sidewall to remove the The semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate is recessed a distance to form a cavity; and the semiconductor substrate is removed from the first processing chamber without exposing the semiconductor substrate to oxidizing conditions. moving the chamber to a second processing chamber; determining a distance by which the semiconductor material has been recessed after isotropic etching; and forming a layer of deposited material on a surface of the cavity using a selective epitaxial growth (SEG) process in the second processing chamber, The semiconductor substrate does not undergo a pre-clean process between forming the cavity and SEG, which takes into account the distance by which the semiconductor material has been recessed after isotropic etching. A processing tool for forming a semiconductor device, the processing tool comprising: a central transfer station, a plurality of processing chambers are arranged around the central transfer station; a robot, within the central transfer station, configured to process the plurality of processing chambers moving a substrate between processing chambers; a first processing chamber connected to the central transfer station, the first processing chamber configured to perform an isotropic etching process; a metrology station within the processing tool and the robot has access to the metrology station configured to determine a distance of a recess of semiconductor material on a substrate from the isotropic etching process; a second processing chamber connected to the central transfer station, The second processing chamber is configured to perform a selective epitaxial growth (SEG) process; and a controller connected to the central transfer station, the robot, the third One or more of a processing chamber, the metrology station, or the second processing chamber, the controller having one or more configurations selected from the following: for moving the plurality of processing chambers and the metrology station. A first configuration of a substrate on the robot; a second configuration for performing an isotropic etching process on a substrate in the first processing chamber; and performing an analysis to determine the a third configuration of the recesses of the semiconductor material; or a fourth configuration for performing a selective epitaxial growth process in the second processing chamber, the selective epitaxial growth process being tuned for the This depression in the semiconductor material.