TWI811910B - Isolated switching converter with secondary side modulation and control method - Google Patents

Abstract

It is disclosed an isolated switching converter and the control circuit and control method thereof. The switching converter has a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding and an isolated circuit. The control method including: generating a pulse frequency modulation signal based on a feedback signal indicative of an output voltage; coupling to the secondary switch and generating a valley pulse signal by detecting one or more valleys of a resonant voltage; generating a target valley number based on the pulse frequency modulation signal, the valley pulse signal and a last-cycle valley number and providing a valley enable signal corresponding to the target valley number; generating a primary on enable signal based on the valley enable signal, the pulse frequency modulation signal and the valley pulse signal; sending the primary on enable signal to an input terminal of the isolation circuit and generating a synchronous signal electrically isolated from the primary on enable signal; and generating a primary control signal to control the primary switch based on the synchronous signal.

Description

Isolated switching converter and controller and control method thereof

The present invention relates to electronic circuits, and in particular to a quasi-resonance controlled isolated switching converter and its controller and control method.

Isolated switching power supplies typically include a transformer with a primary and secondary winding to provide isolation. The primary switch tube is coupled to the primary winding and controls the energy stored in the primary winding to be transferred to the secondary winding. The secondary switch tube is coupled to the secondary winding and serves as a synchronous rectifier tube to replace the traditional rectifier diode to reduce losses and improve the efficiency of the isolated switching power supply. Figure 1 is a waveform diagram of the existing synchronous rectification technology, in which Vds is the drain-source voltage of the secondary switch tube, Isec is the current flowing through the secondary winding, and DRVS is the control signal of the secondary switch tube. Vds is compared to two threshold voltages, such as -70 mV and -500mV respectively. As shown in Figure 1, when the body diode of the secondary switch tube is turned on so that Vds is less than -500mV, the secondary switch tube is turned on; when the primary switch tube is turned on so that Vds is greater than -70mV, the secondary switch tube is turned on. is turned off. However, this can easily cause the primary switch tube and the secondary switch tube to be turned on at the same time (shoot through), reducing the efficiency of the switching power supply and even causing damage to the switching power supply. In addition, in high-frequency applications, the switching action of the switching tube will produce switching losses and electromagnetic interference, which further affects the efficiency of the isolated switching power supply.

In view of one or more problems existing in the prior art, the purpose of the present invention is to provide an isolated switching converter and its controller and control method that can effectively avoid shoot-through and/or improve efficiency and avoid electromagnetic interference. According to an embodiment of the present invention, a controller is used for an isolated switching converter. The switching converter includes a transformer with a primary winding and a secondary winding, a primary switching tube coupled to the primary winding, and a switching transistor coupled to the secondary winding. The secondary switch tube, the controller includes: a valley detection circuit, coupled to the secondary switch tube to detect the waveform of the resonant voltage of the switching converter, and output a valley pulse signal indicating the valley of the resonant voltage; a pulse frequency modulation circuit, receiving a feedback signal representing the output signal of the switching converter, generating a pulse frequency modulation signal; a primary turn-on enable circuit, wherein when the converter operates in a quasi-resonant mode, the primary turn-on enable circuit is based on the pulse frequency modulation signal and the valley pulse signal , the primary turn-on enable signal is output at the output end. When the switching converter operates in the current continuous mode, the primary turn-on enable circuit outputs the pulse frequency modulation signal as the primary turn-on enable signal at the output end; the primary turn-off detection circuit, Detect whether the primary switch tube is turned off and generate a primary turn-off detection signal; a zero-crossing detection circuit detects whether the current flowing through the secondary switch tube crosses zero and generate a zero-crossing detection signal; and a secondary logic circuit is coupled to the primary The shutdown detection circuit, the zero-crossing detection circuit and the primary turn-on enable circuit receive the primary turn-off detection signal, the zero-crossing detection signal and the primary turn-on enable signal, and generate a secondary control signal to control the secondary switch tube; the isolation circuit has An input terminal that receives the primary turn-on enable signal and generates a synchronization signal electrically isolated from the primary turn-on enable signal at the output terminal; and a primary logic circuit coupled to the output terminal of the isolation circuit to receive the synchronization signal and generate a primary primary logic circuit based on the synchronization signal. Control signal to control the primary switching tube. A controller for an isolated switching converter according to an embodiment of the present invention. The switching converter includes a transformer with a primary winding and a secondary winding, a primary switching tube coupled to the primary winding, and a switching transistor coupled to the secondary winding. The secondary switch tube and isolation circuit, the controller includes: a valley detection circuit, coupled to the secondary switch tube to detect the waveform of the resonant voltage of the switching converter, and output a valley pulse signal indicating the valley of the resonant voltage; the pulse frequency modulation power supply circuit, which receives a feedback signal representing the output signal of the switching converter and generates a pulse frequency modulation signal; the valley selection circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal. , the second input terminal receives the trough pulse signal, the trough selection circuit generates the target trough number based on the pulse frequency modulation signal and the trough number of the previous cycle, and provides a trough enable signal in response to the target trough number at the output end; the primary is turned on The enabling circuit has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal, the second input terminal receives the valley pulse signal, and the third input terminal receives The valley enable signal, based on the frequency modulation signal, the valley pulse signal and the valley enable signal, generates a primary turn-on enable signal at the output end and sends it to the input end of the isolation circuit; the primary turn-off detection circuit detects whether the primary switch tube is turned off. Generate a primary turn-off detection signal; a zero-crossing detection circuit detects whether the current flowing through the secondary switch tube crosses zero and generate a zero-crossing detection signal; a secondary logic circuit coupled to the primary turn-off detection circuit and the zero-crossing detection circuit to receive the primary turn-off detection signal and the zero-crossing detection signal, and generate a secondary control signal based on the primary turn-off detection signal and the zero-crossing detection signal to control the secondary switch; and a primary logic circuit coupled to the output end of the isolation circuit To receive a synchronization signal that is electrically isolated from the primary turn-on enable signal, and generate a primary control signal based on the synchronization signal to control the primary switch tube. An isolated switching converter according to an embodiment of the present invention includes the controller as described above. According to a control method of an isolated switching converter according to an embodiment of the present invention, the switching converter includes a transformer with a primary winding and a secondary winding, a primary switching tube coupled to the primary winding, and a secondary switching tube coupled to the secondary winding. Switch tube and isolation circuit, the control method includes: receiving a feedback signal representing the output signal of the switching converter, generating a pulse frequency modulation signal related to the feedback signal; coupling to the secondary switch tube to detect the resonant voltage waveform of the switching converter , generate a trough pulse signal representing the resonant voltage trough; generate a target trough number based on the pulse frequency modulation signal and the trough number of the previous cycle, and provide a trough enable signal in response to the target trough number; based on the trough enable signal, pulse The frequency modulation signal and the valley pulse signal generate a primary turn-on enable signal; the primary turn-on enable signal is sent to the isolation circuit to generate a synchronization signal electrically isolated from the primary turn-on enable signal; and based on the synchronization signal, a primary control signal is generated to Control the primary switching tube. In the embodiment of the present invention, quasi-resonant control is introduced, the primary turn-on enable signal is generated based on the pulse frequency modulation signal and the valley pulse signal, and the valley conduction of the primary switch tube is controlled through a synchronization signal electrically isolated from the primary turn-on enable signal. Switching losses and electromagnetic interference are greatly reduced. At the same time, the secondary switch tube is controlled based on the primary turn-on enable signal and the primary turn-off detection circuit, and the primary switch tube is controlled based on the synchronization signal electrically isolated from the primary turn-on enable signal, which can accurately control the primary switch tube and the secondary switch. There is no need to turn off the secondary switch tube after the primary switch tube is turned on to turn on and off the tube, effectively avoiding shoot-through.

Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described here are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that these specific details need not be employed in order to practice the invention. In other instances, well-known circuits, materials or methods have not been described in detail in order to avoid obscuring the present invention. Throughout this specification, reference to "one embodiment," "an embodiment," "an example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in the invention. In at least one embodiment. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and/or subcombination. Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. It will be understood that when an "element" is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Identical drawing numbers indicate identical elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The invention can be applied to any isolated converter. In the following detailed description, for the sake of simplicity, only a flyback converter is taken as an example to explain the specific operating principle of the present invention. FIG. 2 is a block diagram of an isolated switching converter 200 according to an embodiment of the present invention. As shown in FIG. 2 , the isolated switching converter 200 includes a transformer T1, a primary switch MP, a secondary switch MS, and a controller. The transformer T1 has a primary winding and a secondary winding, wherein the primary winding and the secondary winding each have a first end and a second end, the first end of the primary winding receives the input voltage Vin, and the first end of the secondary winding provides a DC output voltage. Vo, the second terminal is coupled to the secondary reference ground. The primary switch MP is coupled between the second end of the primary winding and the primary reference ground. The secondary switch MS is coupled between the second end of the secondary winding and the load. However, those skilled in the art know that the secondary switch MS can also be coupled between the first end of the secondary winding and the load. In the embodiment shown in FIG. 2 , the controller of the isolated switching converter 200 introduces quasi-resonant control. In quasi-resonant control, the switching converter operates in the non-current continuous mode. When the current flowing through the energy storage element (transformer T1) drops to zero, the parasitic capacitor between the energy storage element and the primary switch MP begins to resonate, and the resonant voltage waveform Result. When the resonant voltage across the primary switch MP is at its minimum value, the primary switch MP is turned on (usually called valley conduction), thereby reducing the switching loss and electromagnetic interference of the switching converter 200 . The controller includes a valley detection circuit 201, a pulse frequency modulation circuit 202, a primary turn-on enable circuit 203, a primary turn-off detection circuit 204, a zero-crossing detection circuit 205, a secondary logic circuit 206, an isolation circuit 207 and a primary logic circuit 208 . In some embodiments, the controller and the secondary switch MS are integrated in the same chip. In the isolation switching converter 200 shown in FIG. 2, the waveform of the resonant voltage is detected by the valley detection circuit 201 located on the secondary side of the transformer. In one embodiment, the valley detection circuit 201 is coupled to the secondary switch MS to detect the waveform of the resonant voltage and output a valley pulse signal Valley_Pulse representing the valley of the resonant voltage. The pulse frequency modulation circuit 202 generates a pulse frequency modulation signal PFM based on the feedback signal representative of the output voltage Vo of the switching converter 200 . The primary turn-on enable circuit 203 receives the mode indication signal CCM, the valley pulse signal Valley_Pulse and the pulse frequency control signal PFM, and provides the primary turn-on enable signal PRON at the output end. When the mode indication signal CCM is valid, the switching converter 200 operates in the current continuous mode, the primary turn-on enable circuit 203 allows the pulse frequency modulation signal PFM to pass, and the primary turn-on enable signal PRON is output at the output end. When the mode indication signal CCM is invalid and the switching converter 200 operates in the quasi-resonant mode, the primary turn-on enable circuit 203 outputs the primary turn-on enable signal PRON at the output end based on the pulse frequency modulation signal PFM and the valley pulse signal Valley_Pulse. The primary turn-off detection circuit 204 detects whether the primary switch MP is turned off and generates the primary turn-off detection signal PROFF. The primary turn-off detection circuit 204 can determine whether the primary switch MP is turned off based on electrical parameters such as the drain-source voltage of the secondary switch MS, the current flowing through the secondary switch MS, and the voltage across the secondary winding. The primary turn-off detection circuit 204 can also obtain a signal indicating whether the primary switch MP is turned off from the primary side through other methods. The zero-crossing detection circuit 205 detects whether the current flowing through the secondary switch MS crosses zero, and generates a zero-crossing detection signal ZCD. The secondary logic circuit 206 has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is coupled to the primary turn-off detection circuit 204 to receive the primary turn-off detection signal PROFF, and the second The input terminal is coupled to the output terminal of the zero-crossing detection circuit 205 to receive the zero-crossing detection signal ZCD, and the third input terminal is coupled to the primary turn-on enable circuit 203 to receive the primary turn-on enable signal PRON. The secondary logic circuit 206 generates a secondary control signal CTRLS at the output end to control the secondary switch MS based on the primary turn-off detection signal PROFF, the zero-crossing detection signal ZCD, and the primary turn-on enable signal PRON. The isolation circuit 207 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the primary turn-on enable circuit 203 to receive the primary turn-on enable signal PRON. Based on the primary turn-on enable signal PRON, the isolation circuit 207 generates a synchronization signal SYNC at the output end that is electrically isolated from the primary turn-on enable signal PRON. Isolation circuit 207 may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device. In other embodiments, isolation circuit 202 may be provided external to the controller integrated circuit. The primary logic circuit 208 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the isolation circuit 207 to receive the synchronization signal SYNC. Based on the synchronization signal SYNC, the primary logic circuit 208 generates a primary control signal CTRLP at the output end to control the primary switch MP. Under quasi-resonant control, the secondary logic circuit 206 turns off the secondary switch MS when the zero-crossing detection circuit 205 detects that the current flowing through the secondary switch MS crosses zero. In the current continuous mode, the secondary logic circuit 206 turns off the secondary switch MS based on the rising edge of the primary turn-on enable signal PRON. At the same time, the secondary switch MP is turned on based on the primary turn-on enable signal PRON. Regardless of the quasi-resonant control in the non-current continuous mode or the current continuous mode, the isolated switching converter 200 shown in Figure 2 does not need to turn off the secondary switch MS after the primary switch MP is turned on, which is avoided in principle. Direct access. In some embodiments, in order to ensure that the primary switch MP is turned on after the secondary switch MS is turned off, the delay circuit is coupled between the primary turn-on enabling circuit 203 and the isolation circuit 207, or the isolation circuit 207 and the primary between logic circuits 208. FIG. 3 is a block diagram of an isolated switching converter 300 according to an embodiment of the present invention. Similar to the switching converter 200 shown in Figure 2, the switching converter 300 includes a transformer T1, a primary switch MP, a secondary switch MS, a valley detection circuit 301, a pulse frequency modulation circuit 302, and a primary turn-on enabling circuit. 303. Primary turn-off detection circuit 304, zero-crossing detection circuit 305, secondary logic circuit 306, isolation circuit 307 and primary logic circuit 308. Among them, the pulse frequency modulation circuit 302 includes an error amplification circuit 3021, a modulation signal generation circuit 3022 and a first comparison circuit 3023. The error amplification circuit 3021 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the feedback signal FB representing the output signal (for example, output voltage, output current, output power) of the switching converter, and the second The input terminal receives the reference signal VREF. The error amplifier circuit 3021 generates a compensation signal COMP at the output end based on the difference between the feedback signal FB and the reference signal VREF. The modulation signal generation circuit 3022 generates a modulation signal VM, which may be a sawtooth wave signal, a triangle wave signal, or other suitable signals. The first comparison circuit 3023 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the error amplifier circuit 3021 to receive the compensation signal COMP, and the second input terminal is coupled to the modulation signal COMP. The signal generation circuit 3022 receives the modulation signal VM. The first comparison circuit 3023 compares the compensation signal COMP with the modulation signal VM, and generates a pulse frequency modulation signal PFM at the output end. In addition, the switching converter 300 further includes a second comparison circuit 309 . The second comparison circuit 309 has a first input terminal, a second input terminal and an output terminal. The first input terminal receives the primary current sampling signal ISENP representing the current flowing through the primary switch MP, and the second input terminal receives the first threshold voltage. VTH1. The second comparison circuit 309 compares the primary current sampling signal ISENP with the first threshold voltage VTH1 and generates a second comparison signal CMPO2 at the output end. The primary logic circuit 308 is coupled to the output end of the second comparison circuit 309 to receive the second comparison signal CMPO2, and generates the primary control signal CTRLP to control the primary switch MP based on the second comparison signal CMPO2 and the synchronization signal SYNC. The first threshold voltage VTH1 may be a constant value, or may change with the change of the isolation signal SYNC. In one embodiment, the switching converter 300 further includes a threshold generation circuit 310 . The threshold generation circuit 310 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the isolation circuit 307 to receive the synchronization signal SYNC, and the output terminal is coupled to the second input terminal of the second comparison circuit 309 . The threshold generation circuit 310 generates the first threshold voltage VTH1 at the output end based on the synchronization signal SYNC. In some embodiments, in order to limit the switching frequency of the switching converter 300, the frequency limiting circuit 3024 is coupled between the output terminal of the first comparison circuit 3023 and the modulation signal generating circuit 3022. The frequency limiting circuit 3024 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first comparison circuit 3023 to receive the pulse frequency modulation signal PFM, and the output terminal is coupled to the modulation signal generating circuit 3022 to provide frequency limiting. Signal FLMT. The frequency limiting circuit 3024 limits the frequency of the modulation signal VM and the frequency of the pulse modulation signal PFM through the frequency limiting signal FLMT, thereby further limiting the maximum switching frequency of the primary switch MP. FIG. 4 is a schematic circuit diagram of an isolated switching converter 400 according to an embodiment of the present invention. As shown in FIG. 4 , the valley detection circuit 401 includes a comparator COM1 and a single pulse generation circuit 4011 . The non-inverting input terminal of the comparator COM1 receives the drain voltage VSRD of the secondary switch MS, the inverting input terminal receives the second threshold voltage VTH2, and the output terminal is coupled to the input terminal of the single pulse generating circuit 4011. In the single pulse generating circuit 4011 The output terminal provides the valley pulse signal Valley_Pulse. The pulse frequency modulation circuit 402 includes an error amplification circuit 4021, a modulation signal generation circuit 4022, a first comparison circuit 4023 and a frequency limiting circuit 4024. Among them, the error amplification circuit 4021 includes an error amplifier EA. The inverting input terminal of the error amplifier EA receives the feedback signal FB representing the output voltage Vo, the non-inverting input terminal receives the reference signal VREF, and the output terminal is coupled to the first comparison circuit 4023 to provide the compensation signal COMP. The modulation signal generating circuit 4022 includes a capacitor C1, a switch S1 and a current source IS1. The capacitor C1 has a first terminal and a second terminal, wherein the first terminal is coupled to the first comparison circuit 4023 to provide the modulation signal VM, and the second terminal is coupled to the secondary reference ground. The switch S1 has a first terminal, a second terminal and a control terminal. The first terminal is coupled to the first terminal of the capacitor C1, the second terminal is coupled to the secondary reference ground, and the control terminal is coupled through the frequency limiting circuit 4024. to the output terminal of the first comparison circuit 4023. The current source Is1 has an input terminal and an output terminal, wherein the input terminal is coupled to the secondary reference ground and the output terminal is coupled to the first terminal of the capacitor C1. In one embodiment, the modulation signal generation circuit 4023 further includes a Zener diode ZD1. The cathode of the Zener diode ZD1 is coupled to the first terminal of the capacitor C1, and the anode is coupled to the secondary reference ground. The first comparison circuit 4023 includes a comparator COM2. The non-inverting input end of the comparator COM2 is coupled to the modulation signal generation circuit 4022 to receive the modulation signal VM, the inverting input end is coupled to the error amplifier circuit 4021 to receive the compensation signal COMP, and the output end is coupled to the primary turn-on enable circuit. 403 to provide a pulse frequency modulation signal PFM. The primary turn-on enable circuit 403 includes a D flip-flop 4031, an OR gate OR1 and an AND gate AND1. The D flip-flop 4031 has an input terminal, a clock terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the valley detection circuit 401 to receive the valley pulse signal Valley_Pulse, and the clock terminal is coupled to the output terminal of the pulse frequency modulation circuit 402 To receive the pulse frequency modulation signal PFM, the output terminal is coupled to the first input terminal of the OR gate OR1. The second input terminal of the OR gate OR1 receives the mode indication signal CCM, and the output terminal of the OR gate OR1 is coupled to the first input terminal of the AND gate AND1. The second input terminal of the AND gate AND1 receives the pulse frequency modulation signal PFM, and the output terminal is coupled to the isolation circuit 407 and the secondary logic circuit 406 to provide the primary turn-on enable signal PRON. Primary off detection circuit 404 includes comparator COM3. The non-inverting input terminal of the comparator COM3 receives the drain voltage VSRD of the secondary switch MS, the inverting input terminal receives the third threshold voltage VTH3, and the output terminal is coupled to the secondary logic circuit 406 to provide the primary turn-off detection signal PROFF. Zero-crossing detection circuit 405 includes comparator COM4. The non-inverting input terminal of the comparator COM4 is coupled to receive the fourth threshold voltage VTH4, the inverting input terminal receives the secondary current sampling signal ISENS representing the current flowing through the secondary switch MS, and the output terminal is coupled to the secondary logic circuit 406 to provide Zero detection signal ZCD. In other embodiments, when the zero-crossing detection circuit 405 detects that the drain voltage VSRD of the secondary switch MS changes from negative voltage to positive voltage, the generated zero-crossing detection signal ZCD changes from low level to high level. Turn off the secondary switch. The secondary logic circuit 406 includes an OR gate OR2 and a flip-flop FF2. The OR gate OR2 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the zero-crossing detection circuit 405 to receive the zero-crossing detection signal ZCD, and the second input terminal is coupled to the primary turn-on enable The circuit 403 receives the primary turn-on enable signal PRON. The flip-flop FF2 has a setting terminal, a resetting terminal and an output terminal, wherein the setting terminal is coupled to the output terminal of the primary turn-off detection circuit 404 to receive the primary turn-off detection signal PROFF, and the resetting terminal is coupled to the output terminal of the OR gate OR2, The output terminal is coupled to the gate of the secondary switch MS to provide the secondary control signal CTRLS. Primary logic circuit 408 includes flip-flop FF1. The flip-flop FF1 has a setting terminal, a resetting terminal and an output terminal. The setting terminal is coupled to the output terminal of the isolation circuit 407 to receive the synchronization signal SYNC, and the resetting terminal is coupled to the output terminal of the second comparison circuit 409 to receive the second comparison. The output terminal of the signal CMPO2 is coupled to the gate of the primary switch MP to provide the primary control signal CTRLP. The second comparison circuit 409 includes a comparator COM5. The non-inverting input terminal of the comparator COM5 receives the primary current sampling signal ISENP, the inverting input terminal is coupled to the threshold generation circuit 410 to receive the first threshold voltage VTH1, and the output terminal is coupled to the primary logic circuit 408 to provide the second comparison signal CMPO2. FIG. 5 is an operation waveform diagram of the isolated switching converter 400 shown in FIG. 4 according to an embodiment of the present invention. As shown in Figure 5, during the turn-off period of the secondary switch MS, when the drain voltage VSRD is greater than the second threshold VTH2, the valley detection circuit 401 provides the valley pulse signal Valley_Pulse. The number of pulses of the valley pulse signal Valley_Pulse depends on the resonance. The number of troughs in the voltage waveform. When the mode indication signal CCM is low level, the switching converter 400 operates in the quasi-resonant mode. When the next valley pulse comes after the rising edge of the pulse frequency modulation signal PFM, the primary turn-on enable signal PRON is valid, and the primary turn-on The enable signal PRON changes from low level to high level. Almost at the same time, the synchronization signal SYNC output by the isolation circuit 407 also changes from low level to high level, the flip-flop FF1 is set, the primary control signal CTRLP changes from low level to high level, and the primary switch MP is turned on. . The current flowing through the primary switch MP increases, and the primary current sampling signal ISENP also increases. When the primary current sampling signal ISENP increases to the first threshold voltage VTH1, the flip-flop FF1 is reset, the primary control signal CTRLP changes from high level to low level, and the primary switch MP is turned off. After the primary switch MP is turned off, the drain voltage VSRD of the secondary switch MS changes from a positive voltage to a negative voltage, the drain voltage VSRD decreases to the third threshold VTH3, the flip-flop FF2 is set, and the secondary control signal CTRLS changes from low level to high level, and the secondary switch MS is turned on. The transformer current is transferred from the primary to the secondary, the current flowing through the secondary switch MS begins to decrease, and the secondary current sampling signal ISENS also decreases. Once it is detected that the secondary current sampling signal ISENS decreases to the fourth threshold voltage VTH4, for example, when it crosses zero, the flip-flop FF2 is reset, the secondary control signal CTRLS changes from high level to low level, and the secondary switch MS is turned off. When the current flowing through the primary and secondary is zero, the energy storage element and the parasitic capacitor of the switching tube begin to resonate, generating a resonant voltage. The waveform of the resonant voltage is detected by the valley detection circuit 401 on the secondary side, generating a valley pulse. SignalValley_Pulse. The above steps are repeated until the mode indication signal CCM changes to high level. When the mode indication signal CCM changes from low level to high level, the switching converter 400 enters the current continuous mode, and the primary turn-on enable circuit 403 allows the pulse frequency modulation signal PFM to be output as the primary turn-on enable signal PRON. The secondary switch MS is also turned off at the rising edge of the primary turn-on enable signal PRON. When the rising edge of the primary turn-on enable signal PRON comes, almost at the same time, the synchronization signal SYNC output by the isolation circuit 407 also changes from low level to high level, and the primary control signal CTRLP changes from low level to high level. The primary switch MP is turned on. When the primary current sampling signal ISENP increases to the first threshold voltage VTH1, the primary switch MP is turned off. After the primary switch MP is turned off, the drain voltage VSRD of the secondary switch MS changes from a positive voltage to a negative voltage, and the secondary switch MS is turned on. The above steps are repeated until the mode indication signal CCM changes from high level to low level. FIG. 6 is a schematic circuit diagram of an isolated switching converter 500 according to an embodiment of the present invention. Similar to the switching converter 400 shown in FIG. 4 , the switching converter 500 includes a transformer T1, a primary switch MP, a secondary switch MS, a valley detection circuit 501, a pulse frequency modulation circuit 502, and a primary turn-on enabling circuit. 503. Primary turn-off detection circuit 504, zero-crossing detection circuit 505, secondary logic circuit 506, isolation circuit 507, primary logic circuit 508, second comparison circuit 509 and threshold generation circuit 510. In addition, the switching converter 500 further includes a valley selection circuit 511 . The valley selection circuit 511 has a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal receives the valley pulse signal Valley_Pulse, the second input terminal receives the pulse frequency modulation signal PFM, and the valley selection circuit 511 is based on the pulse The frequency modulation signal PFM and the valley number VALLEY_LOCK(n-1) of the previous cycle generate the target valley number VALLEY_LOCK(n), and the valley enable signal VEN corresponding to the target valley number is provided at the output end. In one embodiment, the valley selection circuit 511 compares the number of valleys accumulated when the rising edge of the pulse frequency modulation signal PFM arrives with the number of valleys VALLEY_LOCK (n-1) in the previous cycle, and selects to continue to maintain or switch based on the comparison result. to another appropriate trough number. In another embodiment, the trough selection circuit 511 also has a second output terminal, and generates the mode indication signal CCM based on the value of the target trough number. Wherein, when the value of the target trough number is 0, the mode indication signal CCM is high level, indicating the current continuous mode. In the embodiment shown in FIG. 6 , the valley detection circuit 501 includes a valley comparator COM5 , a falling edge trigger circuit 5011 , a flip-flop FF3 , an AND gate AND2 and a single pulse generation circuit 5012 . Among them, the non-inverting input terminal of the valley comparator COM5 is coupled to the secondary switch MS to receive the drain voltage VSRD of the secondary switch tube, and the inverting input terminal receives the output voltage Vo of the switching converter. The valley comparator COM5 The drain voltage VSRD of the switch tube is compared with the output voltage Vo, and a valley comparison signal is generated at the output end. The flip-flop FF3 has a setting end, a resetting end and a reverse output end. The setting end receives the primary turn-on enable signal PRON, and the resetting end receives the secondary control signal CTRLS through the falling edge trigger circuit 5011. The AND gate AND2 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the valley comparator COM5 to receive the valley comparison signal, and the second input terminal is coupled to the flip-flop FF3 Reverse output terminal. The single pulse generation circuit 5012 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the AND gate AND2, and the valley pulse signal Valley_Pulse is provided at the output terminal. FIG. 7 is an operation waveform diagram of the valley detection circuit 501 shown in FIG. 6 according to an embodiment of the present invention. As shown in Figure 7, when the primary turn-on enable signal PRON is valid, the primary control signal CTRL changes from low level to high level, flip-flop FF3 is set, its reverse output terminal outputs low level, and the valley comparison signal is blocked. Covered or prohibited. When the falling edge of the secondary control signal CTRLS comes, that is, the secondary control signal CTRLS changes from high level to low level, the secondary switch MS is turned off, the flip-flop FF3 is reset, and its reverse output terminal outputs high level, allowing the valley comparison signal to be transmitted to the single pulse generation circuit 5012 through the AND gate AND2. And the single pulse generation circuit 5012 generates a valley pulse signal Valley_Pulse with a predetermined pulse width at the rising edge of the valley comparison signal. In some embodiments, in order to ensure that the primary switch MP is turned on at the valley, a delay circuit is coupled between the AND gate AND2 and the single pulse generating circuit 5012. FIG. 8 is a circuit schematic diagram of the valley selection circuit 511 according to an embodiment of the present invention. In the embodiment shown in FIG. 8 , the valley selection circuit 511 includes a first counter 5110 , a first register 5111 , a target valley number generator 5112 and a digital comparator 5113 . The first counter 5110 has a clock terminal, a reset terminal and an output terminal. The clock terminal receives the valley pulse signal Valley_Pulse, and the reset terminal receives the primary turn-on enable signal PRON. The first counter 5110 counts the number of pulses of the valley pulse signal Valley_Pulse in one cycle. Counting is carried out and the first value VALLEY_CNT is provided at the output. The first register 5111 has an input terminal, a clock terminal and an output terminal. The input terminal receives the first value VALLEY_CNT, the clock terminal receives the pulse frequency modulation signal PFM, and the output terminal generates the second value VALLEY_PFM. The target valley number generator 5112 compares the second value VALLEY_PFM with the valley number VALLEY_LOCK(n-1) of the previous cycle, and generates the target valley number VALLEY_LOCK(n) at the output end according to the comparison result. The digital comparator 5113 compares the first value VALLEY_CNT with the target valley number VALLEY_LOCK(n). When the first value VALLEY_CNT is greater than or equal to the target valley number VALLEY_LOCK(n), a valley enable signal VEN is provided at the output end. When the target valley number VALLEY_LOCK(n)=0, the mode recognition signal CCM provided by the valley selection circuit 511 changes from low level to high level, indicating that the switching converter enters the current continuous mode. In the embodiment shown in FIG. 8 , the target trough number generator 5112 includes a first multiplexer 521 , a second multiplexer 522 , a second register 523 and a subtractor 524 . In other embodiments, the target valley generator 5112 is implemented using other forms of digital circuits. When the primary switch MP is turned off, or when the rising edge of each primary turn-off detection signal PROFF comes, the target valley generator 5112 generates the target valley number VALLEY_LOCK(n), and temporarily stores it in the second register 523 . When the second value VALLEY_PFM is greater than the trough number VALLEY_LOCK(n-1) of the previous period, VALLEY_LOCK(n)=VALLEY_ LOCK(n-1)+1. In one embodiment, when the trough number VALLEY_LOCK(n-1) in the previous cycle is greater than 3 and greater than the second value VALLEY_PFM by 2, VALLEY_LOCK(n)=VALLEY_LOCK(n-1)-1. In addition, when the valley number VALLEY_LOCK(n-1) of the previous cycle is 2 or 1, and the rising edge of the pulse frequency modulation signal PFM arrives a preset time earlier than the first valley pulse, the target valley number VALLEY_LOCK (n) =VALLEY_LOCK(n-1)-1. In other cases, the target valley number VALLEY_LOCK(n) remains unchanged from the valley number VALLEY_LOCK (n-1) of the previous period. Continuing as shown in FIG. 6 , the primary turn-on enabling circuit 503 includes an AND gate AND3, an OR gate OR3 and an AND gate AND4. Among them, the AND gate AND3 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the valley pulse signal Valley_Pulse, and the second input terminal is coupled to the first output terminal of the valley selection circuit 511 to receive the valley pulse signal. Enable signal VEN. The OR gate OR3 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the AND gate AND3, and the second input terminal is coupled to the second output terminal of the valley selection circuit 511. Receive mode indication signal CCM. The AND gate AND4 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal PFM, the second input terminal is coupled to the output terminal of the OR gate OR3, and the output terminal provides a primary Turn on the enabling signal PRON. In the current continuous mode, the primary turn-on enable circuit 503 allows the pulse frequency modulation signal PFM to pass, and outputs the primary turn-on enable signal PRON at the output end. In the quasi-resonant mode, when the valley enable signal VEN is valid and the rising edge of the pulse frequency modulation signal PFM comes, the primary turn-on enable circuit 503 outputs a valid primary turn-on enable signal PRON to control the primary switch MP to turn on. FIG. 9 is an operation waveform diagram of the isolated switching converter 500 shown in FIG. 6 according to an embodiment of the present invention. When the mode indication signal CCM is low level, during each off period of the secondary switch MS, the valley detection circuit 501 generates a valley pulse signal based on the comparison result between the drain voltage VSRD of the secondary switch MS and the output voltage Vo. Valley_Pulse. The first counter 5110 counts the valley pulses in each cycle as a first value VALLEY_CNT. The first register 5111 records the first value VALLEY_CNT when the rising edge of the pulse frequency modulation signal PFM comes, and provides the second value VALLEY_PFM. According to the control principle of the target valley number generator 5112, the target valley number VALLEY_LOCK is generated. The primary switch MP is turned on according to the primary turn-on enable signal PRON corresponding to the target trough number. When the mode indication signal CCM becomes high, the pulse frequency modulation signal PFM serves as the primary turn-on enable signal PRON to control the conduction of the primary switch MP. The above-described embodiments all relate to an isolated switching converter that can operate in a current continuous mode and a quasi-resonant operation in a non-current continuous mode. Embodiments of the present invention require only slight modifications and can be used in isolated switching converters using only quasi-resonant control. An isolated flyback converter that only uses quasi-resonant control also meets the spirit and protection scope of the present invention. FIG. 10 is a method flowchart of a control method 900 for a quasi-resonant controlled isolated switching converter according to an embodiment of the present invention. The switching converter includes a transformer with a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, a secondary switch tube coupled to the secondary winding, and an isolation circuit. The control method includes steps 901 to 906. In step 901, a feedback signal representing the output signal of the switching converter is received, and a pulse frequency modulation signal related to the feedback signal is generated. In step 902, the secondary switching transistor is coupled to detect the resonant voltage waveform of the switching converter, and a valley pulse signal representing the resonant voltage valley is generated. In step 903, a target trough number is generated based on the pulse frequency modulation signal and the trough number of the previous cycle, and a trough enabling signal in response to the target trough number is provided. In one embodiment, the number of accumulated troughs when the rising edge of the pulse frequency modulation signal comes is compared with the number of troughs in the previous cycle, and the selection is continued or switched to another appropriate trough number. In step 904, a primary turn-on enable signal is generated based on the valley enable signal, the pulse frequency modulation signal and the valley pulse signal. In step 905, the primary turn-on enable signal is sent to the isolation circuit to generate a synchronization signal electrically isolated from the primary turn-on enable signal. In step 906, based on the synchronization signal, a primary control signal is generated to control the primary switch. The control method 900 further includes: detecting whether the primary switch tube is turned off, and generating a primary turn-off detection signal; detecting whether the current flowing through the secondary switch tube crosses zero, and generating a zero-crossing detection signal; and based on the primary turn-off detection signal and the zero-crossing detection signal. Detect the signal and generate a secondary control signal to control the secondary switch tube. In one embodiment, step 903 includes: receiving the valley pulse signal, counting the pulses of the valley pulse signal within one cycle, and providing a first value; recording the first value when the rising edge of the pulse frequency modulation signal comes, as the second value value; compare the second value with the trough number of the previous period, and generate the target trough number according to the comparison result; and compare the first value with the target trough number, and when the first value is greater than or equal to the target trough number, at the output end Provides valley enable signal. In the specification, relative terms such as first, second, etc. may only be used to distinguish one entity or action from another entity or action and do not necessarily or imply any such relationship between these entities or actions. Or order. Numerical sequences such as "first," "second," "third," etc., refer only to different individuals within a plurality and do not imply any order or sequence unless specifically limited by the language of the claim. The order of text in any request does not imply that the processing steps must proceed in a provisional or logical sequence consistent with that order, unless the request language specifically provides otherwise. These processing steps may be interchanged in any order without departing from the scope of the invention, as long as such interchange does not contradict the language of the claim and does not appear to be logically absurd. The above description and embodiments are merely exemplary and are not intended to limit the scope of the present invention. Variations and modifications are possible to the disclosed embodiments, and other feasible alternative embodiments and equivalent changes to elements in the embodiments will be apparent to those of ordinary skill in the art. Other changes and modifications to the embodiments disclosed in the present invention do not exceed the spirit and scope of the present invention.

200: Isolated switching converter 201: Valley detection circuit 202: Pulse frequency modulation circuit 203: Primary enable circuit 204: Primary shutdown detection circuit 205: Zero-crossing detection circuit 206: Secondary logic circuit 207:Isolation circuit 208: Primary logic circuit 300: Isolated switching converter 301: Valley detection circuit 302: Pulse frequency modulation circuit 303: Primary turn-on signal generation circuit 304: Primary shutdown detection circuit 305: Zero-crossing detection circuit 306: Secondary logic circuit 307:Isolation circuit 308: Primary logic circuit 309: Second comparison circuit 310: Threshold generation circuit 400: Isolated switching converter 401: Valley detection circuit 402: Pulse frequency modulation circuit 403: Primary enable circuit 404: Primary shutdown detection circuit 405: Zero-crossing detection circuit 406: Secondary logic circuit 407:Isolation circuit 408: Primary logic circuit 409: Second comparison circuit 410: Threshold generation circuit 500: Isolated switching converter 501: Valley detection circuit 502: Pulse frequency modulation circuit 503: Primary enable circuit 504: Primary shutdown detection circuit 505: Zero-crossing detection circuit 506: Secondary logic circuit 507:Isolation circuit 508: Primary logic circuit 509: Second comparison circuit 510: Threshold generation circuit 511: Wave valley selection circuit 521: First multiplexer 522: Second multiplexer 523: Second register 524:Subtractor 3021: Error amplifier circuit 3022: Modulation signal generation circuit 3023: First comparison circuit 3024: Frequency limiting circuit 4011:Single pulse generation circuit 4021: Error amplifier circuit 4022: Modulation signal generation circuit 4023: First comparison circuit 4024: Frequency limiting circuit 4031:D flip-flop 5011: Falling edge trigger circuit 5012:Single pulse generation circuit 5110: first counter 5111: First register 5112: Target trough number generator 5113:Digital comparator T1: Transformer MP: primary switch tube MS: secondary switch tube Vin: input voltage Vo: output voltage PFM: pulse frequency modulation signal CCM: mode indication signal Valley_Pulse: Valley pulse signal PRON: primary enable signal ZCD: Zero-crossing detection signal PROFF: primary shutdown detection signal SYNC: synchronization signal CTRLP: primary control signal FB: feedback signal VREF: reference signal VM: modulated signal COMP: compensation signal VTH1: first threshold voltage ISENP: primary current sampling signal CMPO2: second comparison signal FLMT: frequency limited signal COM1: Comparator VSRD: drain voltage VTH2: second threshold voltage EA: error amplifier C1: Capacitor IS1: current source S1: switch tube ZD1: Zener diode COM2: Comparator OR1: Or gate AND1: AND gate COM3: Comparator COM4: Comparator ISENS: secondary current sampling signal VTH4: fourth threshold voltage OR2: Or gate FF1: Trigger FF2: Trigger COM5: Comparator VTH3: third threshold VEN: Wave trough enabling signal COM5: Trough comparator FF3: Trigger AND2: AND gate AND3: AND gate OR3: OR gate AND4: AND gate VALLEY_CNT: first value VALLEY_PFM: second value

[Figure 1] is a waveform diagram of existing synchronous rectification technology; [Fig. 2] is a block diagram of an isolated switching converter 200 according to an embodiment of the present invention; [Fig. 3] is a block diagram of an isolated switching converter 300 according to an embodiment of the present invention; [Fig. 4] is a circuit schematic diagram of an isolated switching converter 400 according to an embodiment of the present invention; [Fig. 5] is an operation waveform diagram of the isolated switching converter 400 shown in Fig. 4 according to an embodiment of the present invention; [Fig. 6] is a circuit schematic diagram of an isolated switching converter 500 according to an embodiment of the present invention; [Fig. 7] is an operation waveform diagram of the valley detection circuit 501 shown in Fig. 6 according to an embodiment of the present invention; [Fig. 8] is a circuit schematic diagram of the valley selection circuit 511 shown in Fig. 6 according to an embodiment of the present invention; [Fig. 9] is an operating waveform diagram of the isolated switching converter 500 shown in Fig. 6 according to an embodiment of the present invention; [Fig. 10] is a method flow chart of a control method 900 for a quasi-resonant controlled isolated switching converter according to an embodiment of the present invention.

200: Isolated switching converter

201: Valley detection circuit

202: Pulse frequency modulation circuit

203: Primary enable circuit

204: Primary shutdown detection circuit

205: Zero-crossing detection circuit

206: Secondary logic circuit

207:Isolation circuit

208: Primary logic circuit

Claims (20)

A controller for an isolated switching converter, which includes a transformer with a primary winding and a secondary winding, a primary switching tube coupled to the primary winding, and a secondary switching tube coupled to the secondary winding. , the controller includes: a valley detection circuit, coupled to the secondary switch tube to detect the waveform of the resonant voltage of the switching converter, and output a valley pulse signal representing the valley of the resonant voltage; a pulse frequency modulation circuit, receiving a representative The feedback signal of the output signal of the switching converter generates a pulse frequency modulation signal; a primary turn-on enabling circuit, wherein when the switching converter operates in a quasi-resonant mode, the primary turn-on enabling circuit is based on the pulse frequency modulation signal and the valley pulse signal, and outputs a primary turn-on enable signal at the output end. When the switching converter operates in the current continuous mode, the primary turn-on enable circuit uses the pulse frequency modulation signal as the primary turn-on enable signal at the Output terminal output; primary turn-off detection circuit, detects whether the primary switch tube is turned off, and generates a primary turn-off detection signal; zero-crossing detection circuit, detects whether the current flowing through the secondary switch tube crosses zero, and generates zero-crossing detection signal; and a secondary logic circuit coupled to the primary turn-off detection circuit, the zero-crossing detection circuit and the primary turn-on enable circuit to receive the primary turn-off detection signal, the zero-crossing detection signal and the primary turn-on enable signal to generate a secondary control signal to control the secondary switch; An isolation circuit has an input end that receives the primary turn-on enable signal and generates a synchronization signal electrically isolated from the primary turn-on enable signal at an output end; and a primary logic circuit coupled to the output end of the isolation circuit to receive the A synchronization signal is generated, and a primary control signal is generated based on the synchronization signal to control the primary switch tube. The controller of claim 1, wherein the pulse frequency modulation circuit includes: an error amplification circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the feedback signal , the second input terminal receives the reference signal, the error amplification circuit generates a compensation signal at the output terminal based on the difference between the feedback signal and the reference signal; the modulation signal generation circuit generates a modulation signal; and the first comparison circuit, Having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the error amplifier circuit to receive the compensation signal, and the second input terminal is coupled to the modulation signal The generating circuit receives the modulation signal, the first comparison circuit compares the compensation signal with the modulation signal, and generates the pulse frequency modulation signal at the output end. As in the controller of claim 1, the primary turn-on enabling circuit includes: a D flip-flop having an input terminal, a clock terminal and an output terminal, wherein the input terminal receives the valley pulse signal, and the clock terminal receives the pulse frequency. Modulation signal; A first OR gate has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the D flip-flop, and the second input terminal receives a signal representing the operation of the switching converter. a mode indication signal of the mode; and a first AND gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first OR gate, and the second input terminal The terminal receives the pulse frequency modulation signal, and the first AND gate provides the primary turn-on enable signal at the output terminal. The controller according to claim 1, further comprising: a second comparison circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a primary signal representing the current flowing through the primary switch tube. The current sampling signal, the second input terminal receives the first threshold voltage, the second comparison circuit compares the primary current sampling signal with the first threshold voltage, and generates a second comparison signal at the output terminal; and wherein, the primary The logic circuit is further coupled to the output end of the second comparison circuit to receive the second comparison signal and generate the primary control signal based on the second comparison signal and the synchronization signal. The controller of claim 1, wherein the valley detection circuit includes: a valley comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the secondary switch The second input terminal receives the drain voltage of the secondary switch tube, and the second input terminal receives the output voltage of the switching converter. The valley comparator compares the drain voltage of the secondary switch tube with the output voltage. This output generates a valley comparison signal; The flip-flop has a setting end, a resetting end and a reverse output end, wherein the setting end receives the primary turn-on enable signal, and the resetting end receives the secondary control signal through the falling edge trigger circuit; the second AND gate has a An input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the valley comparison signal, the second input terminal is coupled to the reverse output terminal of the flip-flop; and a single pulse generation circuit having An input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the second AND gate, and the valley pulse signal is provided at the output terminal. The controller according to claim 1, further comprising: a valley selection circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal, and the second input terminal The terminal receives the trough pulse signal, the trough selection circuit generates a target trough number based on the pulse frequency modulation signal and the trough number of the previous cycle, and provides a trough enable signal corresponding to the target trough number at the output end; and The primary turn-on enable circuit also includes a third input terminal that receives the valley enable signal, and generates the primary turn-on enable signal at the output terminal based on the pulse frequency modulation signal, the valley pulse signal and the valley enable signal. . The controller as claimed in claim 6, wherein when the target valley number is 0, the switching converter enters the current continuous mode. The controller as claimed in claim 6, wherein the valley selection circuit calculates the accumulated value when the rising edge of the pulse frequency modulation signal comes. The trough number is compared with the trough number of the previous cycle, and the trough enable signal is provided when the current trough number reaches the target trough number. The controller of claim 8, wherein the valley selection circuit includes: a counter having a clock terminal, a reset terminal and an output terminal, wherein the clock terminal receives the valley pulse signal, and the reset terminal receives the primary turn-on enable signal, the counter counts the number of pulses of the valley pulse signal in one cycle, and provides a first value at the output terminal; the temporary register has an input terminal, a clock terminal and an output terminal, wherein the input terminal receives the first value A value, the clock terminal receives the pulse frequency modulation signal, and generates a second value at the output terminal; the target trough number generator compares the second value with the trough number of the previous cycle, and generates a value at the output terminal. the target trough number; and a digital comparator that compares the first value with the target trough number, and when the first value is greater than or equal to the target trough number, provides the trough enable signal at the output end. The controller as described in request item 9, wherein: when the second value is greater than the number of troughs in the previous period, the target number of troughs is equal to the number of troughs in the previous period plus 1; when the number of troughs in the previous period is greater than 3 and is greater than the second value by 2, the target trough number is equal to the trough number of the previous period minus 1; and when the trough number of the previous period is 2 or 1, and the rising edge of the pulse frequency modulation signal arrives, When arriving a preset time earlier than the first wave trough, The target trough number is equal to the trough number of the previous period minus 1. The controller of claim 6, wherein when the valley enable signal is valid and the rising edge of the pulse frequency modulation signal comes, the primary turn-on enable signal is valid and controls the primary switch to be turned on. A controller for an isolated switching converter, which includes a transformer with a primary winding and a secondary winding, a primary switching tube coupled to the primary winding, and a secondary switching tube coupled to the secondary winding. and an isolation circuit. The controller includes: a valley detection circuit coupled to the secondary switch tube to detect the waveform of the resonant voltage of the switching converter and output a valley pulse signal representing the valley of the resonant voltage; a pulse frequency modulation circuit , receiving a feedback signal representing the output signal of the switching converter to generate a pulse frequency modulation signal; the valley selection circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal. changing signal, the second input terminal receives the trough pulse signal, the trough selection circuit generates a target trough number based on the pulse frequency modulation signal and the trough number of the previous cycle, and provides a response to the target trough number at the output end The valley enabling signal; the primary turn-on enabling circuit has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal receives the pulse frequency modulation signal, and the second input terminal The terminal receives the valley pulse signal, and the third input terminal receives the valley enable signal. Based on the frequency modulation signal, the valley pulse signal and the valley enable signal, a primary turn-on enable signal is generated at the output terminal to the isolation The input terminal of the circuit; The primary turn-off detection circuit detects whether the primary switch tube is turned off and generates a primary turn-off detection signal; the zero-crossing detection circuit detects whether the current flowing through the secondary switch tube crosses zero and generates a zero-crossing detection signal; the secondary a logic circuit coupled to the primary turn-off detection circuit and the zero-crossing detection circuit to receive the primary turn-off detection signal and the zero-crossing detection signal, and generate a secondary based on the primary turn-off detection signal and the zero-crossing detection signal a control signal to control the secondary switch; and a primary logic circuit coupled to the output end of the isolation circuit to receive a synchronization signal electrically isolated from the primary turn-on enable signal, and generate a primary control signal based on the synchronization signal to control the primary switch tube. The controller as described in claim 12, wherein the valley selection circuit compares the number of valleys accumulated when the rising edge of the pulse frequency modulation signal comes with the number of valleys in the previous cycle, and selects to continue to maintain or maintain based on the comparison result. Switch to another appropriate trough, and provide the trough enabling signal when the current trough number reaches the target trough number. An isolated switching converter includes the controller described in any one of claims 1 to 13. A control method for an isolated switching converter, which includes a transformer with a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, a secondary switch tube coupled to the secondary winding, and isolation Circuit, the control method includes: receiving a feedback signal representing the output signal of the switching converter, and generating a pulse frequency modulation signal related to the feedback signal; Coupled to the secondary switch transistor to detect the resonant voltage waveform of the switching converter, and generate a valley pulse signal representing the valley of the resonant voltage; based on the pulse frequency modulation signal and the number of valleys in the previous cycle, generate a target number of valleys, And provide a trough enable signal in response to the target trough number; generate a primary turn-on enable signal based on the trough enable signal, the pulse frequency modulation signal and the trough pulse signal; send the primary turn-on enable signal into the The isolation circuit generates a synchronization signal that is electrically isolated from the primary turn-on enable signal; and based on the synchronization signal, generates a primary control signal to control the primary switch tube. The control method as described in claim 15, further includes: detecting whether the primary switch tube is turned off, and generating a primary turn-off detection signal; detecting whether the current flowing through the secondary switch tube crosses zero, and generating a zero-crossing detection signal; and Based on the primary turn-off detection signal and the zero-crossing detection signal, a secondary control signal is generated to control the secondary switch tube. According to the control method described in claim 15, the method for generating the target trough number includes: comparing the accumulated trough number when the rising edge of the pulse frequency modulation signal comes with the trough number of the previous cycle, and selecting to maintain or switch. to another appropriate trough number. The control method as described in claim 15, wherein it is provided The method of providing the valley enable signal includes: receiving the valley pulse signal, counting the pulses of the valley pulse signal within one cycle, and providing a first value; and recording the first value when the rising edge of the pulse frequency modulation signal comes. , as the second value; compare the second value with the trough number of the previous period, and generate a target trough number according to the comparison result; and compare the first value with the target trough number, when the first value is greater than or When equal to the target trough number, the trough enable signal is provided at the output end. The control method as described in claim 18, wherein: when the second value is greater than the number of troughs in the previous period, the target number of troughs is equal to the number of troughs in the previous period plus 1; when the number of troughs in the previous period is greater than 3 and is greater than the second value by 2, the target trough number is equal to the trough number of the previous period minus 1; and when the trough number of the previous period is 2 or 1, and the rising edge of the pulse frequency modulation signal arrives, When the target trough is reached a preset time earlier than the first trough, the target trough number is equal to the trough number of the previous period minus 1. The control method as described in claim 15, wherein when the target valley number is 0, the switching converter enters the current continuous mode.

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