TWI811128B - Oscillator with pvt variation suppression - Google Patents

Abstract

An oscillator with PVT variation suppression includes a voltage variation detection circuit, a temperature variation detection circuit, a process variation detection circuit, an operation unit and an oscillator. The operation unit is electrically connected to the voltage variation detection circuit, the temperature variation detection circuit and the process variation detection circuit, and the operation unit outputs an output selection control signal according to the process variation detection signal, the voltage variation detection signal and the temperature variation detection signal. A plurality of delay units of the oscillator are connected in series with each other, and each of the delay elements output a delay signal. A plurality of multiplexers of the oscillator are electrically connected to each of the delay units to receive each of the delay signals, and the multiplexers are controlled by the output selection control signal to output one of the delay signals as an oscillation signal.

Description

Oscillators that suppress process, voltage, and temperature variations

The present invention relates to an oscillator, in particular to an oscillator that suppresses process, voltage, and temperature variations.

Many electronic circuits must be equipped with an oscillator to provide a reference frequency to synchronize the various components in the electronic circuit. For example, in the processor, the oscillation signal output by the oscillator is used as a clock signal to synchronize the access and operation of data in the memory. , and for example, in the communication system, the oscillator is used as the local oscillation source to use the fixed frequency output by the local oscillation source to transmit and receive wireless signals. However, due to the continuous shrinking of the current semiconductor manufacturing process, integrated circuits integrate multiple systems on a single substrate, which makes the advanced integrated manufacturing process prone to temperature rise and voltage drop problems, resulting in the output frequency of the oscillator being affected by voltage, temperature and process variation. The expected frequency cannot be output due to the influence.

The main purpose of the present invention is to adjust the oscillator output through the voltage variation detection signal, temperature variation detection signal and process variation detection signal respectively detected by the voltage variation detection circuit, temperature variation detection circuit and process variation detection circuit The frequency of the oscillating signal can suppress voltage, temperature and process variations, and an oscillator with stable output frequency can be obtained.

An oscillator for suppressing process, voltage, and temperature variations of the present invention includes a voltage variation detection circuit, a temperature variation detection circuit, a process variation detection circuit, a computing unit, and an oscillator. The voltage variation detection circuit outputs A voltage variation detection signal, the temperature variation detection circuit outputs a temperature variation detection signal, the process variation detection circuit outputs a process variation detection signal, the computing unit is electrically connected to the voltage variation detection circuit, the temperature The variation detection circuit and the process variation detection circuit are used to receive the voltage variation detection signal, the temperature variation detection signal and the process variation detection signal, and the calculation unit according to the process variation detection signal, the voltage variation detection The measurement signal and the temperature variation detection signal output an output selection control signal. The oscillator has a plurality of delay elements and a plurality of multiplexers. The delay units are connected in series, and each of the delay elements outputs a delay signal. The multiplexers are electrically connected to the delay units to receive the delayed signals, and the multiplexers are controlled by the output selection control signal to output one of the delayed signals as an oscillation signal.

According to the present invention, the calculation unit outputs the voltage variation detection signal of the voltage variation detection circuit, the temperature variation detection signal of the temperature variation detection circuit and the process variation detection signal of the process variation detection circuit The output selection control signal Sel controls the oscillator so that the oscillator output can suppress voltage, temperature and process variation.

Please refer to FIG. 1, which is an embodiment of the present invention, a functional block diagram of an oscillator 100 that suppresses variations in process, voltage, and temperature. The oscillator 100 that suppresses variations in process, voltage, and temperature has a voltage variation detection circuit 110 . A temperature variation detection circuit 120 , a process variation detection circuit 130 , an arithmetic unit 140 and an oscillator 150 .

Please refer to Figures 1 and 2, the voltage variation detection circuit 110 is used to detect voltage variation and output a voltage variation detection signal V[4:0]. In this embodiment, the voltage variation detection circuit 110 has A delay line 111 , a controllable delay circuit 112 , a temporary storage unit 113 and a logic gate group 114 . The delay line 111 receives a clock signal clk, the delay line 111 has a plurality of delayers 111a, and the delayers 111a are used to delay the clock signal clk, and the delayers 111a output a plurality of delay signals D1~ D6, the controllable delay circuit 112 receives a power supply voltage VDD, a positive terminal control voltage Vc+, a negative terminal control voltage Vc- and the delay signal D6 output by one of the delayer 111a, the controllable delay circuit 112 according to The power supply voltage VDD, the positive terminal control voltage Vc+ and the negative terminal control voltage Vc− delay the delay signal clk to output a delayed clock signal Dclk. The temporary storage unit 113 is electrically connected to the delay line 111 and the controllable delay circuit. 112 to receive the delayed signals D1~D6 and the delayed clock signal Dclk, and the temporary storage unit 113 is triggered by the delayed clock signal Dclk to store the delayed signals D1-D6, and the voltage variation detection circuit 110 outputs the delayed signals D1-D6 as a voltage variation detection signal V[4:0].

Please refer to FIG. 3, the controllable delay circuit 112 is composed of a plurality of delay units 112a connected in series, and each delay unit 112a has a positive load 112b, a negative load 112c and an inverter 112d. The positive end load 112b receives the power supply voltage VDD and the positive end control voltage Vc+, the negative end load 112c receives the negative end control voltage Vc- and is grounded, and the inverter 112d is electrically connected to the positive end load 112b and the negative end load 112b. end load 112c and inverts the input signal. In this embodiment, the positive end load 112b has a first PMOS high voltage transistor Mp1 and a second PMOS high voltage transistor Mp2, and the sources of the first and second PMOS high voltage transistors Mp1 and Mp2 receive the The power supply voltage VDD, the gate of the first PMOS high voltage transistor Mp1 receives the positive terminal control voltage Vc+, the drain of the first PMOS high voltage transistor Mp1, the gate of the second PMOS high voltage transistor Mp2 and The drain is electrically connected to a third PMOS high voltage transistor Mp3 of the inverter 112d. The negative terminal load 112c has a first NMOS high voltage transistor Mn1 and a second NMOS high voltage transistor Mn2, the sources of the first and second NMOS high voltage transistors Mn1, Mn2 are grounded, and the first NMOS high voltage The gate of the transistor Mn1 receives the negative terminal control voltage Vc-, the drain of the first NMOS high voltage transistor Mn1, the gate and the drain of the second NMOS high voltage transistor Mn2 are electrically connected to the inverter One of 112d is a third NMOS high voltage transistor Mn3. In this embodiment, the delay unit 112a of the first bit receives the delayed signal D6, and then the delay unit 112a of the last bit outputs the delayed clock signal Dclk after being sequentially delayed by each of the delay units 112a, In addition, since the present embodiment uses the positive terminal control voltage Vc+ and the negative terminal control voltage Vc− to control the impedances of the positive terminal load 112b and the negative terminal load 112c, the delayed clock signal Dclk due to process drift can be avoided. errors, so that the detection of voltage variation can be more accurate.

Please refer to FIG. 2, the temporary storage unit 113 is electrically connected to the delay line 111 and the controllable delay circuit 112 to receive the delayed signals D1-D6 and the delayed clock signal Dclk, and the temporary storage unit 113 is delayed by the The clock signal Dclk is triggered to store the delayed signals D1-D6. In this embodiment, the temporary storage unit 113 has a plurality of temporary registers 113a, and each of the temporary registers 113a is electrically connected to each of the buffers 111a to receive and temporarily store the delays triggered by the delayed clock signal Dclk. Signals D1-D6. Since the voltage variation of the power supply voltage VDD will change the triggering time of the delayed clock signal Dclk output by the controllable delay circuit 112, the delayed signals D1 stored in the registers 113a under different voltage variations - The potentials of D6 are different, and the voltage variation of the power supply voltage VDD can be judged by the potentials of the delay signals D1-D6 stored in the registers 113a.

The logic gate group 114 has a plurality of logic gates 114a, the logic gates 114a are electrically connected to the registers 113a to receive the temporarily stored delayed signals D1-D6, and the logic gates 114a output the voltage variation detection The test signal V[4:0], in this embodiment, the logic gates 114a are mutually exclusive OR gates. Although the voltage variation of the power supply voltage VDD can be judged by the potentials of the delayed signals D1-D6 stored in the logic gates 114a, the potential changes of the delayed signals D1-D6 stored in the logic gates 114a may be relatively irregular. Preferably, in this embodiment, through the design of the delay line 111 and the delay amount of the controllable delay circuit 112, the voltage variation detection signal V[4:0] output by the logic gates 114a is different There are regular changes under the voltage variation, so that the back-end circuit can control the voltage variation.

Please refer to Figure 1, the temperature variation detection circuit 120 is used to detect temperature variation and output a temperature variation detection signal T[12:8], please refer to Figure 4, in this embodiment, the temperature variation detection The side circuit 120 has a current generator 121 , a charging and discharging circuit 122 , a window comparator 123 and an encoder 124 , and the current generator 121 is used to output an output current Io. The charging and discharging circuit 122 is electrically connected to the current generator 121 to receive the output current Io and output a charging voltage Vc. The window comparator 123 is electrically connected to the charging and discharging circuit 122 to receive the charging voltage Vc, and the window comparator 123 outputs an output voltage Vo to the charging and discharging circuit 122, and the charging and discharging circuit 122 is based on the output voltage Vo to charge or discharge. The encoder 124 is electrically connected to the window comparator 123 to receive the output voltage Vo and output the output voltage Vo as the temperature variation detection signal T[12:8].

Please refer to FIG. 5, the current generator 121 has a first current mirror 121a, a resistor 121b and a second current mirror 121c, the resistor 121b is electrically connected to the first current mirror 121a and the second current mirror 121c, The resistor 121b is used to generate the output current Io, the second current mirror 121c is electrically connected to the charging and discharging circuit 122, and the second current mirror 121c is used to map the output current Io to the charging and discharging circuit 122, preferably , the current value of the output current Io has a linear relationship with the temperature.

Please refer to FIG. 5, the charging and discharging circuit 122 has a charging current mirror 122a, a charging and discharging capacitor 122b, a charging and discharging switch 122c and a discharging current mirror 122d. The charging current mirror 122a is electrically connected to the second current mirror 121c and the charging and discharging capacitor 122b, and the charging current mirror 122a is used for mapping the current of the second current mirror 121c to the charging and discharging capacitor 122b. The charge and discharge switch 122c is electrically connected to the charge and discharge capacitor 122b and the discharge current mirror 122d, and the charge and discharge switch 122c is controlled by the output voltage Vo to turn on or off the voltage between the discharge current mirror 122d and the charge and discharge capacitor 122b. To switch the charging current mirror 122a to charge the charging and discharging capacitor 122b, or to let the charging and discharging capacitor 122b discharge through the discharging current mirror 122d, the terminal voltage of the charging and discharging capacitor 122b is output as the charging voltage Vc. In this embodiment, when the output voltage Vo is at a high potential, the charging and discharging switch 122c cuts off the electrical connection between the discharging current mirror 122d and the charging and discharging capacitor 122b to enter the charging mode, and the output voltage Vo is at a low potential. , the charge and discharge switch 122c conducts the electrical connection between the discharge current mirror 122d and the charge and discharge capacitor 122b to enter the discharge mode.

Wherein, by the design of the transistor size difference between the charging current mirror 122a and the discharging current mirror 122d, the current of the discharging current mirror 122d can be twice the current of the charging current mirror 122a. Therefore, when the When the output voltage Vo controls the charging and discharging switch 122c to cut off the connection between the discharging current mirror 122d and the charging and discharging capacitor 122b, the current of the charging current mirror 122a will charge the charging and discharging capacitor 122b to increase the charging voltage Vc. On the contrary, when the output voltage Vo controls the charging and discharging switch 122c to conduct between the discharging current mirror 122d and the charging and discharging capacitor 122b, although the charging current mirror 122a will continue to provide current, due to the current of the discharging current mirror 122d The magnitude is twice the current magnitude of the charging current mirror 122a, so that the current of the charging current mirror 122a will flow to the discharging current mirror 122d, and the charging and discharging capacitor 122b will also discharge toward the discharging current mirror 122d to make the charging voltage Vc decline.

Please refer to Figures 5 and 6, the window comparator 123 has a first comparator 123a, a second comparator 123b, a comparator switch 123c, an initial voltage switch 123d and a VWC (voltage windows comparator) inverter. to the device 123e. The first comparator 123a is electrically connected to the charging and discharging capacitor 122b to receive the charging voltage Vc and the high potential reference voltage VH for comparison and output a first comparison signal op1. The second comparator 123b is electrically connected to the charging and discharging capacitor 122b to receive the charging voltage Vc and the low potential reference voltage VL for comparison and output a second comparison signal op2. The comparator switch 123c is electrically connected to the first and second comparators 123a, 123b and the VWC inverter 123e, the comparator switch 123c is controlled by the output voltage Vo to selectively the first comparator The signal op1 or the second comparison signal op2 is sent to the VWC inverter 123e for inversion. The initial voltage switch 123d is electrically connected to the VWC inverter 123e and ground, and the VWC inverter 123e outputs the output voltage Vo. Wherein, the initial voltage switch 123d is controlled by an initial voltage control signal In, and is used to ground the VWC inverter 123e when turned on, so that the output voltage Vo output by the VWC inverter 123e is at a high potential. Wherein, when the output voltage Vo is at a high potential, the comparator switching switch 123c is switched to the first comparator 123a, so as to transmit the first comparison signal op1 to the VWC inverter 123e for inversion, relatively, When the output voltage Vo is low, the comparator switching switch 123c is switched to the second comparator 123b, so that the The second comparison signal op2 is sent to the VWC inverter 123e for inversion.

Please refer to FIG. 4 , the encoder 124 is electrically connected to the window comparator 123 to receive the output voltage Vo, and the encoder 124 outputs the temperature variation detection signal T[12:8] according to the output voltage Vo. The encoder 124 is used to convert the potential change of the output voltage Vo into a digital signal, so as to facilitate the back-end circuit to control the temperature variation.

The circuit operation of the temperature variation detection circuit 120 is as follows: the output current Io output by the current generator 121 is mapped to the charge and discharge circuit 122 so that the charge current mirror 122a and the discharge current mirror 122d generate current; the initial voltage control signal In turns on the initial voltage switch 123d, so that the output voltage Vo is at a high potential, and enters the charging mode at this time, the charging and discharging switch 122c cuts off the electrical connection between the charging and discharging capacitor 122b and the discharging current mirror 122d, and the charging current The mirror 122a charges the charging and discharging capacitor 122b to increase the charging voltage Vc. When the charging voltage Vc rises to be higher than the high potential reference voltage VH, the first comparison signal op1 rises to a high potential to make the VWC inverter 123e The output voltage Vo of the output turns to a low potential; at this time, it enters the discharge mode, and the charge and discharge switch 122c conducts the electrical connection between the charge and discharge capacitor 122b and the discharge current mirror 122d, and the charge and discharge capacitor 122b is discharged to make the The charging voltage Vc drops, and when the charging voltage Vc drops below the low potential reference voltage VL, the second comparison signal op2 rises to a low potential to make the output voltage Vo output by the VWC inverter 123e turn to a high potential, Re-enter charging mode. The repeated charging and discharging of the charging and discharging capacitor 122b causes the output voltage Vo to oscillate between high and low potentials, and since the magnitude of the output current Io can change the speed of charging and discharging, the oscillation frequency of the output voltage Vo is related to the magnitude of the output current Io It has a linear relationship, and because the output current Io has a linear relationship with the temperature, the frequency of the output voltage Vo can have a linear relationship with the temperature and the temperature variation can be measured.

Please refer to FIG. 1, the process variation detection circuit 130 is used to detect process variation and output a process variation detection signal P. In this embodiment, the process variation detection circuit 130 has an NMOS Process variation detector 131 and PMOS process variation detector 132, the process variation detection signal P includes an NMOS process variation signal PN and a PMOS process variation signal PP, the NMOS process variation detector 131 is used to detect NMOS The NMOS process variation detection signal PN is outputted for the process variation, and the PMOS process variation detector 132 is used to detect the PMOS process variation and output the PMOS process variation detection signal PP.

Please refer to FIG. 7, the NMOS process variation detector 131 has a plurality of NMOS inversion circuits 131a, a plurality of CMOS inversion circuits 131b, an AND gate 131c and a counter 131d, the NMOS inversion circuits 131a and the The CMOS reverse circuit 131b is cross-connected to form a ring oscillator unit RO, the ring oscillator unit RO outputs a process variation oscillation signal POs, and the AND gate 131c is electrically connected to the ring oscillator unit RO and the oscillator 150 to receive the process variation Oscillation signal POs and a process clock signal clkP, the AND gate 131c outputs an AND gate signal and, and the AND gate signal and is fed back as the input signal of the ring oscillator unit RO, and the counter 131d is electrically connected through an inverter The AND gate 131c receives the reverse AND gate signal and, and the counter 131d is used to count the number of surges of the AND gate signal and to output a count signal.

Wherein, since the NMOS inverting circuit 131a of the ring oscillator unit RO is affected by process variations, the oscillation times of the process variation oscillation signal POs of the ring oscillator unit RO in one cycle of the process clock signal clkP are generated change, and the process clock signal ClkP will reset the counter 131d at the signal upper edge, so that the number of pulses of the gate signal and counted by the counter 131d is the process variation oscillation signal POs in the process clock signal The number of oscillations in one period of clkP, therefore, this embodiment can measure the process corner of NMOS.

Preferably, in this embodiment, the highest two bits Ct1 and Ct2 of the counting signal are stored in two registers R1 and R2, and the data stored in the two registers R1 and R2 are output as the NMOS process The variation detection signal PN.

Please refer to FIG. 8, the PMOS process variation detector 132 has an inverter 132a, a first PMOS string 132b, a second PMOS string 132c, a first comparator 132d and a second comparator 132e. The inverter 132a receives a reset signal rP and outputs an inverted reset signal rPb. The first PMOS string 132b has a first PMOS Mp11 and a second PMOS Mp12, the first PMOS Mp11 is electrically connected to the inverter 132a and is controlled by the reverse reset signal rPb, the second PMOS Mp12 is electrically connected to the first The PMOS Mp11, and the second PMOS Mp12 receive and are controlled by the reset signal rP, and the first PMOS string 132b outputs a first potential Vp1. The second PMOS string 132c has a third PMOS Mp13 and a fourth PMOS Mp14, the third PMOS Mp13 is electrically connected to the inverter 132a and is controlled by the reverse reset signal rPb, and the fourth PMOS Mp14 is electrically connected to the first The PMOS string 132b, and the fourth PMOS Mp14 receives and is controlled by the first potential Vp1, and the second PMOS string 132c outputs a second potential Vp2. The first comparator 132d and the second comparator 132e are electrically connected to the second PMOS string 132c, the first comparator 132d receives the second potential Vp2 and a first threshold voltage Vb1 for comparison and outputs a first For the comparison signal C1, the second comparator 122e receives and compares the second potential Vp2 and a second threshold voltage Vb2 to output a second comparison signal C2.

Wherein, when the reset signal rP is at a high potential, the reverse reset signal rPb is at a low potential, the first PMOS Mp11 and the third PMOS Mp13 are turned on, and at this time the first potential Vp1 and the second potential Vp2 rise to high potential. When the reset signal rP is low, the second PMOS Mp12 and the fourth PMOS Mp14 are turned on, the first potential Vp1 is discharged to the critical voltage of the PMOS, and the second potential Vp2 is discharged to twice the critical voltage of the PMOS. Therefore, after comparing the second potential Vp2 with the first threshold voltage Vb1 and the second threshold voltage Vb2 by the first comparator 132d and the second comparator 132e, the first comparison signal can C1 and the second comparison signal C2 determine the process corner of the PMOS.

Preferably, in this embodiment, the first comparison signal C1 and the second comparison signal C2 Temporarily stored in the two registers R3 and R4, the data stored in the two registers R3 and R4 are output as the PMOS process variation detection signal PP.

Please refer to FIG. 1 , the NMOS process variation detection signal PN and the PMOS process variation detection signal PP are sent to an encoder 160 to be recoded into 3-bit process variation detection signals P[7:5].

Please refer to FIG. 1, the computing unit 140 is electrically connected to the voltage variation detection circuit 110, the temperature variation detection circuit 120 and the process variation detection circuit 130 to receive the voltage variation detection signal V[4:0] , the temperature variation detection signal T[12:8] and the process variation detection signal, and the computing unit 140 according to the process variation detection signal P[7:5], the voltage variation detection signal V[4: 0] and the temperature variation detection signal T[12:8] output an output selection control signal Sel. In this embodiment, the computing unit 140 is an FPGA chip, and the output selection control signal Sel is a 6-bit digital signal. In other embodiments, the computing unit 140 can be other microprocessors. This limit.

Please refer to Figures 1 and 9, the oscillator 150 has a plurality of delay elements 151, a plurality of multiplexers 152 and a decoder 153, the decoder 153 receives the 6-bit output selection control signal Sel and decodes it for 64-bit. The delay units 151 are connected in series, and each delay unit 151 outputs a delay signal. Each of the multiplexers 152 is electrically connected to each of the delay units 151 to receive each of the delayed signals, and the multiplexers 152 are controlled by the 64-bit output selection control signal Sel decoded by the decoder 153 to output one of them. A delayed signal is an oscillating signal Os. In this embodiment, each of the delay elements 151 is a dual-input and dual-output delay device, therefore, the multiplexers 152 form a group of two, and the multiplexers in the same group are electrically connected to each of the multiplexers. The positive terminal output and the negative terminal output of the delay element, and the multiplexers in the same group are controlled by the output selection control signal Sel of the same bit.

In this embodiment, there are 64 groups of these multiplexers 152, which are the 0th bit and the 63rd bit from right to left, and the 63rd bit of these multiplexers 152 receive high potential and low potential respectively. The 64-bit The output selection control signal Sel selects and turns on the multiplexers 152 of the 63rd bit to enable the delay elements 151 to oscillate. Wherein, when the selection code of the 64-bit output selection control signal Sel is larger, there are more delay elements 151 participating in the oscillation, which will make the frequency of the output oscillation signal Os slower; on the contrary, when the The smaller the selection code of the 64-bit output selection control signal Sel, the fewer the delay elements 151 involved in the oscillation, which will make the frequency of the output oscillation signal Os faster, thereby adjusting the output oscillation signal Frequency of Os.

In this embodiment, under different voltage, temperature and process variations, the quantity of the delay elements 151 participating in the oscillation can suppress the voltage, temperature and process variations, and determine the encoding rule of the output selection control signal Sel. Therefore, in actual use, let the calculation unit 140 detect signal P[7:5] according to the process variation, the voltage variation detection signal V[4:0] and the temperature variation detection signal T[12:8] The output selection control signal Sel can make the oscillating signal Os output by the oscillator 150 suppress voltage, temperature and process variations, and achieve a set frequency.

According to the voltage variation detection signal V[4:0] of the voltage variation detection circuit 110 and the temperature variation detection signal T[12:8] of the temperature variation detection circuit 120 by the computing unit 140 in the present invention And the process variation detection signal P[7:5] of the process variation detection circuit 130 outputs the output selection control signal Sel to control the oscillator 150 so that the oscillator 150 can suppress voltage, temperature and process variation.

The scope of protection of the present invention should be defined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with this technology without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .

100: Oscillators that suppress process, voltage, and temperature variations

110: Voltage variation detection circuit

111: Delay line

111a: delayer

112: Controllable delay circuit

112a: delay unit

112b: Positive terminal load

112c: Negative terminal load

112d: Inverter

113: temporary storage unit

113a: scratchpad

114: logic gate group

114a: logic gate

120: Temperature variation detection circuit

In: initial voltage control signal

121: Current generator

121a: the first current mirror

121b: resistance

121c: second current mirror

122: Charge and discharge circuit

122a: charging current mirror

122b: charging and discharging capacitor

122c: Charge and discharge switch

122d: Discharge current mirror

123: window comparator

123a: first comparator

123b: second comparator

123c: Comparator switch

123d: Initial voltage switch

123e: VWC inverter

124: Encoder

130: Process variation detection circuit

131: NMOS process variation detector

131a: NMOS reverse circuit

131b: CMOS reverse circuit

131c: and gate

131d: counter

132:PMOS Process Variation Detector

132a: Inverter

132b: the first PMOS string

132c: the second PMOS string

132d: first comparator

132e: second comparator

140: Operation unit

150: Oscillator

151: delay element

152: multiplexer

153: Decoder

160: Encoder

RO: ring oscillator unit

VDD: power supply voltage

P[7:5]: process variation detection signal

PN: NMOS process variation detection signal

PP: PMOS process variation detection signal

V[4:0]: voltage variation detection signal

T[12:8]: temperature variation detection signal

Sel: output selection control signal

Os: Oscillating signal

Vb1: the first threshold voltage

Vb2: the second threshold voltage

clk: clock signal

D1~D6: delay signal

Vc+: Positive terminal control voltage

Vc-: negative terminal control voltage

Dclk: delayed clock signal

Mp1: the first PMOS high voltage transistor

Mp2: The second PMOS high voltage transistor

Mp3: The third PMOS high voltage transistor

Mn1: the first NMOS high voltage transistor

Mn2: the second NMOS high voltage transistor

Mn3: the third NMOS high voltage transistor

Io: output current

Vc: charging voltage

Vo: output voltage

VH: high potential reference voltage

op1: the first comparison signal

VL: low potential reference voltage

op2: the second comparison signal

clkP: process clock signal

POs: process variation oscillation signal

rP: reset signal

rPb: reverse reset signal

Vp1: the first potential

Vp2: second potential

C1: The first comparison signal

C2: The second comparison signal

and: and gate signal

Mp11: First PMOS

Mp12: Second PMOS

Mp13: The third PMOS

Mp14: Fourth PMOS

R1~R4: temporary register

Figure 1: According to an embodiment of the present invention, a functional block diagram of an oscillator that suppresses process, voltage, and temperature variations. Fig. 2: According to an embodiment of the present invention, a circuit diagram of a voltage variation detection circuit. Fig. 3: According to an embodiment of the present invention, a circuit diagram of a controllable delay circuit.

Fig. 4: According to an embodiment of the present invention, a functional block diagram of a temperature variation detection circuit.

Fig. 5: a circuit diagram of the temperature variation detection circuit according to an embodiment of the present invention.

Fig. 6: A circuit diagram of a window comparator according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of an NMOS process variation detector according to an embodiment of the present invention.

Fig. 8: A circuit diagram of a PMOS process variation detector according to an embodiment of the present invention.

Fig. 9: A circuit diagram of an oscillator according to an embodiment of the present invention.

100: Oscillators that suppress process, voltage, and temperature variations

110: Voltage variation detection circuit

120: Temperature variation detection circuit

130: Process variation detection circuit

131: NMOS process variation detector

132:PMOS Process Variation Detector

140: Operation unit

150: Oscillator

Os: Oscillating signal

Vc+: Positive terminal control voltage

Vc-: negative terminal control voltage

clk: clock signal

VH: high potential reference voltage

VL: low potential reference voltage

In: initial voltage control signal

clkP: process clock signal

Vb1: the first threshold voltage

Vb2: the second threshold voltage

rP: reset signal

PN: NMOS process variation detection signal

PP: PMOS process variation detection signal

P[7:5]: process variation detection signal

T[12:8]: temperature variation detection signal

V[4:0]: voltage variation detection signal

Sel: output selection control signal

Claims (9)

An oscillator that suppresses process, voltage, and temperature variations, which includes: a voltage variation detection circuit that outputs a voltage variation detection signal; a temperature variation detection circuit that outputs a temperature variation detection signal; a process variation detection A circuit that outputs a process variation detection signal, wherein the process variation detection circuit has an NMOS process variation detector and a PMOS process variation detector, and the process variation detection signal includes an NMOS process variation signal and a PMOS process variation signal signal, the NMOS process variation detector is used to detect the NMOS process variation and output the NMOS process variation detection signal, and the PMOS process variation detector is used to detect the PMOS process variation and output the PMOS process variation detection signal; an operation A unit electrically connected to the voltage variation detection circuit, the temperature variation detection circuit and the process variation detection circuit to receive the voltage variation detection signal, the temperature variation detection signal and the process variation detection signal, and the The computing unit outputs an output selection control signal according to the process variation detection signal, the voltage variation detection signal and the temperature variation detection signal; and an oscillator with a plurality of delay elements and a plurality of multiplexers, the delay units connected in series, and each of the delay elements outputs a delay signal, each of the multiplexers is electrically connected to each of the delay units to receive each of the delay signals, and these multiplexers are controlled by the output selection control signal to output one of them A delayed signal is an oscillating signal. An oscillator for suppressing variations in process, voltage, and temperature as claimed in item 1, wherein the temperature variation detection circuit has a current generator, a charging and discharging circuit, and a window comparator, and the current generator is used to output an output current, The charging and discharging circuit is electrically connected to the current generator to receive the output current and output a charging voltage, the window comparator is electrically connected to the charging and discharging circuit to receive the charging voltage, and the window comparator outputs an output voltage to the charge and discharge circuit, the charge and discharge circuit according to the input The output voltage is charged or discharged, wherein the temperature variation detection circuit outputs the output voltage as a temperature variation detection signal. An oscillator for suppressing process, voltage, and temperature variations as claimed in claim 2, wherein the current generator has a first current mirror, a resistor, and a second current mirror, and the resistor is electrically connected to the first current mirror and the second A current mirror, the resistor is used to generate the output current, the second current mirror is electrically connected to the charging and discharging circuit, and the second current mirror is used to map the output current to the charging and discharging circuit. An oscillator that suppresses variations in manufacturing process, voltage, and temperature as claimed in claim 3, wherein the charging and discharging circuit has a charging current mirror, a charging and discharging capacitor, a charging and discharging switch, and a discharging current mirror, and the charging current mirror is electrically connected to the The second current mirror, the charge and discharge capacitor is electrically connected to the charge current mirror, the charge and discharge switch is electrically connected to the charge and discharge capacitor and the discharge current mirror, and the charge and discharge switch is controlled by the output voltage to turn on or off the discharge current The electrical connection between the mirror and the charging and discharging capacitor is used to switch the charging current mirror to charge the charging and discharging capacitor or to let the charging and discharging capacitor discharge through the discharging current mirror, and the terminal voltage of the charging and discharging capacitor is the charging voltage. Such as the oscillator for suppressing process, voltage and temperature variation of claim 4, wherein the window type comparator has a first comparator, a second comparator, a comparator switching switch, an initial voltage switch and a VWC (voltage windows comparator) inverter, the first comparator is electrically connected to the charging and discharging capacitor to receive the charging voltage and a high potential reference voltage for comparison and output a first comparison signal, the second comparator is electrically connected to the charging and discharging The capacitor receives the charging voltage and a low potential reference voltage for comparison and outputs a second comparison signal. The comparator switching switch is electrically connected to the first and second comparators and the VWC inverter. The comparator switching switch Controlled by the output voltage to selectively transmit the first comparison signal or the second comparison signal to the VWC inverter, the initial voltage switch is electrically connected to the VWC inverter and ground, and the VWC inverter outputs the output voltage. An oscillator for suppressing process, voltage, and temperature variations as claimed in claim 1, wherein the temperature variation detection circuit has an encoder, the encoder is electrically connected to the window comparator to receive the output voltage, and the encoder is based on the The output voltage outputs the temperature variation detection signal. An oscillator for suppressing process, voltage, and temperature variation as claimed in claim 1, wherein the NMOS process variation detector has a plurality of NMOS inverting circuits, a plurality of CMOS inverting circuits, an AND gate and a counter, and the NMOS inverting circuits The circuit and the CMOS reverse circuits are cross-connected to form a ring oscillation unit, the ring oscillation unit outputs a process variation oscillation signal, and the gate is electrically connected to the ring oscillation unit to receive the process variation oscillation signal and a process time pulse signal, the AND gate outputs an AND gate signal, and the AND gate signal is fed back as the input signal of the ring oscillator unit, and the counter is electrically connected to the AND gate to receive the AND gate signal, and the counter is used to count the AND gate signal. The number of bursts of the gate signal is output as the NMOS process variation detection signal. An oscillator for suppressing process, voltage, and temperature variations as claimed in item 1, wherein the PMOS process variation detector has an inverter, a first PMOS string, a second PMOS string, a first comparator, and a second A comparator, the inverter receives a reset signal and outputs an inverted reset signal, the first PMOS string has a first PMOS and a second PMOS, the first PMOS is electrically connected to the inverter and received The reverse reset signal is controlled, the second PMOS is electrically connected to the first PMOS, and the second PMOS receives the reset signal and is controlled by it, the first PMOS string outputs a first potential, and the second PMOS The string has a third PMOS and a fourth PMOS, the third PMOS is electrically connected to the inverter and is controlled by the reverse reset signal, the fourth PMOS is electrically connected to the first PMOS string, and the fourth The PMOS receives the first potential and is controlled by it, the second PMOS string outputs a second potential, the first comparator and the second comparator are electrically connected to the second PMOS string, the first comparator receives the first Two potentials and a first threshold voltage are compared to output a first comparison signal, and the second comparator receives the second potential and a second gate The threshold voltage is compared to output a second comparison signal, and the PMOS process variation detector outputs the first comparison signal and the second comparison signal as the PMOS process variation detection signal. An oscillator for suppressing process, voltage, and temperature variations as claimed in item 1, wherein the voltage variation detection circuit has a delay line, a controllable delay circuit, a temporary storage unit and a logic gate group, and the delay line receives a clock signal, the delay line has a plurality of delayers, these delayers are used to delay the clock signal, and these delayers output a plurality of delay signals, the controllable delay circuit receives a power supply voltage, a positive terminal control voltage , a negative terminal control voltage and the delayed signal output by one of the delayers, the controllable delay circuit delays the delayed signal according to the power supply voltage, the positive terminal control voltage and the negative terminal control voltage to output a delayed clock pulse signal, the temporary storage unit is electrically connected to the delay line and the controllable delay circuit to receive the delayed signals and the delayed clock signal, and the temporary storage unit is triggered by the delayed clock signal to store the delayed signals, the The logic gate group is electrically connected to the temporary storage unit to receive the temporarily stored delayed signals, and the logic gate group outputs the temporarily stored delayed signals as the voltage variation detection signal.

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