TWI748451B - Semiconductor device manufacturing process for forming a plurality of phase-isolated base layers on the same wafer and its semiconductor device - Google Patents

Abstract

The present invention is a semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer and the semiconductor device thereof. First, a plurality of device regions and isolation regions are planned on a wafer, and then, on the wafer and corresponding to each In the device area, a device layer and an interconnection wire layer are sequentially built, and then an etching process is performed on the isolation area of the wafer, so that each of the device areas forms an independent base layer, so that each base layer The layers and their corresponding component layers and interconnection wire layers respectively form semiconductor devices. In this way, since each semiconductor device has its own independent base layer, there will be no negative influence on each other during subsequent operations.

Description

Semiconductor device manufacturing process for forming a plurality of phase-isolated base layers on the same wafer and its semiconductor device

The present invention relates to a semiconductor manufacturing process and a semiconductor device thereof, and particularly refers to a semiconductor manufacturing process in which a plurality of isolated base layers are formed on the same wafer.

In the past few decades, the semiconductor industry has developed at an amazing speed. Many of its major innovations have also supported many industries, such as e-commerce, finance, medical... etc. The current semiconductor products can be roughly divided into integrated circuits (IC), There are three types of discrete components and optoelectronic semiconductors. Among them, the integrated circuit is a circuit design (including circuits and electronic components) that is fabricated on a silicon chip to enable it to process information. For example, memory ICs, micro-components , Logic IC, analog IC... etc.; discrete components refer to semiconductor-related components in general circuit design, such as transistors, diodes, thyristors... etc.; optoelectronic semiconductors refer to the use of electrons and photons in semiconductors The materials and components designed by the conversion effect, such as light-emitting components, light-receiving components, composite components and photovoltaic special components...etc.

Here is an integrated circuit for description. The current manufacturing process of an integrated circuit is roughly a subsequent step. First, according to the required functions of the chip, the circuit diagram is first designed, and then the photolithography and lithography imaging methods are used to The circuit diagram is imprinted on the wafer through the mask. After that, the staff will continue to add ions to the wafer to control the conductivity by implanting impurities into the silicon structure, and then fabricate transistors and diodes on it. Body... and other electronic components. In addition, the staff will make multiple connections on each electronic component (for example, pour copper into the groove on the wafer) to electrically connect the electronic components to each other according to the circuit structure. The corresponding semiconductor device is formed, and finally, the wafer that has completed the aforementioned process is cut into a plurality of dies, and then each die is mounted on the corresponding lead frame, and an insulating plastic body or ceramic shell is packaged on the outside, namely The required chip can be formed.

However, the inventor found that in the existing manufacturing process, if multiple semiconductor devices are fabricated on the same wafer, they often use the integrated wafer (ie, the substrate) as the ground or reference voltage. However, generally speaking, the wafer is usually weakly conductive and not completely insulated. When each semiconductor device is in different positions in the circuit, for example, in the case of a half-bridge drive circuit, it includes a high-side driver (high-side driver). ), low-side drivers, and voltage/level shifts (level shift)... and other semiconductor devices. If these semiconductor devices all share the same base layer, then in actual use, the reference of each semiconductor device The voltage value will be affected by other semiconductor devices.

In addition, in order to provide semiconductor devices with faster speed and lower power consumption, some companies have developed SOI (Silicon On Insulator) wafers, which are mainly embedded between the top surface of the wafer and the base silicon at the bottom. A layer of high-temperature insulating material is hereby briefly intervened in the current SOI wafer manufacturing process as follows: (1) SIMOX: A large amount of oxygen ions (O+) are injected into the silicon wafer in a high-energy manner, so that the high-energy implanted oxygen ions can be distributed under the surface of the silicon wafer, and then undergo high-temperature annealing (anneal ) To make the aforementioned implanted oxygen ions and silicon chemically react to form an oxide layer (ie, high-temperature insulating material) under the surface of the wafer, and a silicon single crystal layer above the oxide layer, forming the so-called Silicon structure on the insulating layer; in addition, if the thickness of the silicon single crystal layer above the oxide layer cannot reach the desired thickness, an epitaxial silicon layer can be grown on the silicon single crystal layer by CVD; Finally, the CMP method is used to smooth the surface of the wafer to increase the surface smoothness and improve the characteristics of the device. (2) BESOI: It is formed by combining two silicon wafers (Device Wafer and Handle Wafer). First, a layer of epitaxial silicon is grown on top of the device wafer to serve as an etching stop. Layer (etch stop layer), and through high-temperature oxidation on the operating wafer, an oxide layer (ie, high-temperature insulating material) is generated. In addition, using Vender Walls force, the device wafer and The wafers are manipulated for chaining, and thermal annealing is used to strengthen the chaining of the two wafers. After that, mechanical extrusion and etching are used to remove the excess silicon layer on the device wafer, and finally annealing and grinding are performed. Equal steps to produce a smooth, clean and impurity-free wafer surface. (3) Smart-Cut: It is also formed by combining two wafers (the first wafer and the second wafer). Among them, the first wafer is used as a substrate, and the second wafer is used to provide silicon For the thin film layer, first, the second wafer is grown with an oxide layer (that is, high-temperature insulating material) using a thermal oxidation method, and then hydrogen ions are used for ion distribution, and then the second wafer and the first wafer Hydrophilic bonding (hydrophilic bonding) is carried out, and after the thermal reaction of 400°C to 600°C, the second wafer will be broken from the position of ion implantation due to hydrogen ions, and the fracture surface will be broken. A silicon single crystal layer is formed between it and the oxide layer. Finally, a high temperature environment of 1100 ℃ is used to strengthen the chemical bond of the produced silicon single crystal layer to improve the quality of the silicon single crystal layer. At the same time, the surface is polished.

In summary, the bottom-up structure of SOI wafers continues to be "silicon single crystal layer-high temperature insulating material (oxide layer)-silicon single crystal layer." Electronic components and corresponding wiring. However, the inventor found that the manufacturing process of SOI wafers is extremely complicated and the production cost is high. In particular, SOI wafers need to be processed at high temperatures (such as over 600 ℃, generally 900 ℃ ~ 1100 ℃), so they need to be resistant. High-temperature materials are used to form the aforementioned high-temperature insulating materials (oxide layers). The high-temperature treatment process consumes a lot of resources and has high requirements for related machines, resulting in high production costs for the industry. Therefore, how to effectively improve the aforementioned problems This is one of the important issues that the present invention intends to solve.

In order to improve the aforementioned problems, the inventor relied on years of practical experience, and after many experiments and tests, finally designed a semiconductor device manufacturing process of the present invention that forms a plurality of phase-isolated base layers on the same wafer. The semiconductor device is expected to provide the industry with a better production process through the present invention.

One objective of the present invention is to provide a semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer. At each component area, a component layer and an interconnection wire layer are constructed in sequence, wherein the interconnection wire layer enables a plurality of electronic components in the component layer to be electrically connected to each other according to circuit requirements. An etching process is performed on the wafer corresponding to each of the isolation regions. The etching process is to etch from the bottom surface of the wafer upwards until it completely penetrates the wafer and the interconnection wire layer, so that each of the device regions is formed independently. A base layer for each base layer and its corresponding device layer and each interconnection wire layer to form semiconductor devices. Thus, since each semiconductor device has its own independent base layer, in the process of subsequent operations , Will not cause a negative impact on each other.

Another object of the present invention is to provide a semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer. First, a plurality of device regions and isolation regions are planned on a wafer, and then, on the wafer Corresponding to each component area, a component layer and an interconnection wire layer are constructed in sequence, wherein the interconnection wire layer enables a plurality of electronic components in the component layer to be electrically connected to each other according to circuit requirements, and then An etching process is performed on the wafer corresponding to each of the isolation regions. The etching process is to etch from the top surface of the interconnection wire layer downward until it penetrates the interconnection wire layer, and part of the wafer is etched from its top surface. The wafer is recessed downward, and a thinning process is performed on the wafer to reduce the thickness of the wafer until each of the device regions forms an independent base layer, so that each base layer and its corresponding device layer and Each interconnection wire layer forms an independent semiconductor device. In this way, through the process of the present invention, each semiconductor device can have its own independent base layer.

Another object of the present invention is to provide a semiconductor device with a plurality of isolated base layers formed on the same wafer, which is manufactured by the aforementioned semiconductor device manufacturing process, and includes a base layer, a component layer and an interconnection A wire layer, wherein the component layer and the interconnection wire layer are provided on the top surface of the base layer, and the interconnection wire layer enables a plurality of electronic components in the component layer to form electrical connections with each other according to circuit requirements, the The semiconductor device is characterized in that it does not contain high-temperature insulating materials and only has a single silicon single crystal layer as the base layer.

In order to facilitate your reviewer to have a further understanding and understanding of the purpose, technical features and effects of the present invention, the following examples are provided in conjunction with the diagrams. The detailed description is as follows:

The present invention is a semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer and the semiconductor device thereof. In a first embodiment, please refer to Figures 1 and 2, the wafer 1 (Wafer, or A plurality of device regions 11 and isolation regions 12 can be planned on the silicon wafer (as in step (S101)). Moreover, the top surface of the wafer 1 corresponds to the position of each device region 11, and one A device layer 13 (such as step (S102)), wherein the device layer 13 is a combination of a plurality of electronic components (such as transistors, capacitors, etc.), and the electronic components It is made by microfabrication, and the thickness of the device layer 13 is between 10 microns and 300 microns. After that, an interconnection wire layer 14 ( interconnect layer) (such as step (S103)), the interconnection wire layer 14 enables a plurality of electronic components in the component layer 13 to be electrically connected to each other according to circuit requirements. In particular, the present invention adopts The diagram only shows the sequence of each structure, and the forming method of the element layer 13 and the interconnection wire layer 14 is a conventional method of the current integrated circuit, so it will not be repeated, but those who have general knowledge of the present invention After mastering the technical features mentioned later, the aforementioned component layer 13 and interconnection wire layer 14 can be completed according to product requirements.

Continuing, please refer to Figures 1 and 2. In the first embodiment, after the corresponding component layers 13 and interconnection wire layers 14 have been built on the wafer 1, it can A first supporting layer 15 is provided above the interconnecting wire layer 14 (as in step (S104)), wherein the first supporting layer 15 can be made of conductive material, insulating material, light-transmitting material, or non-light-transmitting material, etc., and It will not cause the component layer 133 and the interconnection wire layer 14 to operate incorrectly (such as a short circuit), but not limited to this. In other embodiments of the present invention, according to product and manufacturing requirements, the industry can also omit the configuration The first support layer 15, or the wafer 1, the component layer 13 and the interconnection wire layer 14 are attached to a support structure, for example, the wafer 1, the component layer 13 and the interconnection layer are passed through wax. The wire layer 14 is adhered to the polishing jig. At this time, the above-mentioned polishing jig is the first support layer 15 referred to in the present invention.

Please refer to FIGS. 1 and 3 again. In the first embodiment, an etching process (such as dry etching) is performed on the wafer 1 corresponding to the position of each isolation region 12 (such as step (S105) )), the etching process is to etch from the bottom surface of the wafer 1 upwards (according to the direction of the drawing in Figure 2) until it completely penetrates the wafer 1 and the interconnection wire layer 14, and, although the first In an embodiment, after the etching process is completed, each of the isolation regions 12 will form a groove 12A, but it is not limited to this. In other embodiments of the present invention, after the etching process is completed, the adjacent An insulating material (such as spin-on glass (SOG) material, polymer colloid, glass powder, insulating metal oxide... etc.) is filled between each base layer 11A and each interconnection wire layer 14. In addition, in other embodiments of the present invention, before performing the etching process, a thinning process can be performed on the wafer 1 to reduce the thickness of the wafer 1 and thereby improve the efficiency of the subsequent etching process.

Continuing, please refer to Fig. 4 again. After the aforementioned etching process, each device region 11 will form an independent substrate layer 11A (substrate), so that each substrate layer 11A and its corresponding device layer 13 , Each interconnection wire layer 14 respectively forms a semiconductor device so as to have its own ground or reference voltage. For example, take the half-bridge drive circuit in Figure 5, which is composed of a plurality of semiconductor devices, where the reference voltage of the high-side driver is usually the output voltage (Pout) The reference voltage of the low-side driver and the voltage/level shift is usually ground (GND). In this way, through the overall process of the present invention, it can be on the same wafer 1 A plurality of independent base layers 11A are formed. Therefore, the circuit architecture (such as the aforementioned high-side driver, low-side driver, and voltage/level converter) on each semiconductor device can have its own ground during subsequent operations. Or at the reference voltage without affecting each other.

In order to enable each semiconductor device to be electrically connected with other electronic components or other semiconductor devices, in the first embodiment, please refer to FIG. 4 again. After the etching process is completed, the semiconductor device can be opened. Hole process. The hole-opening process will form an upper channel 161 in the first support layer 15. The upper channel 161 corresponds to the interconnection wire layer 14. Then, the upper channel 161 is filled with a conductive material to form a The upper contact portion 162 (pad), in this way, the semiconductor device can perform a wire bonding process with other electronic components and other semiconductor devices through the corresponding upper contact portion 162. However, in other embodiments of the present invention, when the first support layer 15 is of a temporary nature and will be removed, the interconnection wire layer 14 can also be provided with a corresponding first support layer 15 before the first support layer 15 is provided. The contact portion 160 (as shown in Figure 2) is required for wire bonding, wherein the contact portion 160 or the upper contact portion 162 is used to electrically connect to the corresponding component layer 13, so that the component Layer 13 can receive/transmit power or signals. In addition, after the etching process is completed or when the packaging process is performed, the two interconnection wire layers 14 on the left side of Figure 4 can be electrically connected to each other, and the two interconnection wire layers 14 on the right side of Figure 4 are the same It can be electrically connected to each other, therefore, only two contact parts 160 or upper contact part 162 are drawn in FIGS. 2 and 4.

In addition, in addition to the arrangement of the upper contact portion 162, the present invention can also adopt the Through Silicon Via (TSV) method. In the second embodiment of the present invention, please refer to FIG. 6 as shown in FIG. After the etching process is completed, a hole-opening procedure can be performed on the semiconductor device. The hole-opening procedure will form a lower channel 164 in the base layer 11A. The lower channel 164 corresponds to the device layer 13. The channel 164 is filled with a conductive material to form the lower contact portion 165, so that the semiconductor device can perform a wire bonding process with other electronic components and other semiconductor devices through the corresponding lower contact portion 165. Furthermore, when the first support layer 15 is of a temporary nature and needs to be removed, please refer to FIG. 7. After the etching process is completed, a second support will be provided on the bottom surface of each base layer 11A. After the layer 17 is removed, the first supporting layer 15 can be removed to form the state as shown in FIG. 8.

In the third embodiment of the present invention, referring to FIGS. 9 and 10, a plurality of device regions 21 and isolation regions 22 can be planned on the wafer 2 first (as in step (S201)), which is particularly mentioned here The "device area" referred to in the present invention refers to the part that will eventually form the base layer, and the "isolation area" referred to in the present invention refers to the part that will be etched in the end, which will be described first. On the top surface of the wafer 2 and corresponding to the position of each of the device regions 21, a device layer 23 can be built separately (as in step (S202)). After that, a mutual device layer 23 is provided on the wafer 2 and each device layer 23. Connect the wire layer 24 (as in step (S203)). Also, different from the steps of the first embodiment, please refer to FIG. 11. After the interconnection wire layer 24 is completed, an etching process is performed on the location of the wafer 2 corresponding to each isolation region 22 (such as Step (S204)), the etching process is to etch from the top surface of the interconnection wire layer 24 downwards, until the interconnection wire layer 24 is penetrated, and a part of the wafer 2 is recessed from the top surface thereof to form a groove 22A (as shown in Figure 11). In addition, before/after the etching process, corresponding contact parts 260 can be provided on the interconnection wire layer 24 according to product requirements.

Continuing, please refer to Figures 8, 11, and 12 to perform a thinning process (such as step (S205)) on the wafer 2 to reduce the thickness of the wafer 2. As shown in Figure 12, the The imaginary frame portion of the wafer 2 is the thinned area 22B, and the thinned area 22B can at least cover the partial groove 22A, so that each device area 21 can form an independent base layer 21A, so that each base layer 21A and its corresponding element layer 23 and interconnection wire layer 24 can form semiconductor devices, respectively. In addition, in the third embodiment, please refer to FIG. 11 again. After the etching process is completed, an insulating material can be filled into the groove 22A, so that the adjacent base layer 21A and the interconnection wire The layers 24 are separated by an insulating material, but it is not limited to this, and the industry can omit the foregoing steps. Furthermore, before the thinning process, a first support layer 25 can be provided above each interconnection wire layer 24, and then a hole-opening process can be performed to form an upper layer in the first support layer 25. The upper channel 261 corresponds to the interconnection wire layer 24. Then, the upper channel 261 is filled with a conductive material to form an upper contact portion 262, and the thinning process is finally performed. If the first supporting layer 25 is also of temporary nature, after the thinning process is completed, a second supporting layer can be provided on the bottom surface of the base layer 21A as in the first embodiment before removing the First support layer 25.

In summary, through the overall manufacturing process of the present invention, the industry can install multiple semiconductor devices (such as photodiodes, MOSFETs, etc.) on the same wafer, and connect them in series. After the photodiodes, they are electrically connected to the corresponding metal oxide half field effect transistors, and the corresponding metal oxide half field effect transistors can be driven by the accumulated photovoltaic (photovoltaic) voltage of the photodiodes. The foregoing circuit structure is sufficient. Through the process of the present invention, each semiconductor device can have an independent base layer as a ground or reference voltage without affecting each other, effectively improving the convenience of production and application. Therefore, the industry only needs to The finished wafer product is cut into bare die and packaged, and then the required wafer can be formed. In addition, compared with the SOI wafer process, the semiconductor device formed by the process of the present invention does not contain high-temperature insulating materials (that is, related materials that require an oxide layer that can withstand high temperature processing above 600 degrees Celsius). ), and there is only a single silicon single crystal layer as the base layer 11A, 21A, and does not have two silicon single crystal layers like an SOI wafer. Therefore, in the case of exempting high-temperature processing and high-temperature insulating materials Next, the present invention can obviously effectively reduce the overall production cost.

According to, the above are only the preferred embodiments of the present invention. However, the scope of rights claimed by the present invention is not limited to this. Anyone familiar with the art can use the technical content disclosed in the present invention. The equivalent changes that are easily considered should all fall within the scope of protection of the present invention.

[Learning] none [this invention] 1, 2: Wafer 11, 21: component area 11A, 21A: base layer 12, 22: Isolation area 12A, 22A: groove 13, 23: component layer 14, 24: Interconnect wire layer 15, 25: the first support layer 160, 260: Contact part 161, 261: Upper channel 162, 262: Upper contact part 164: Down Channel 165: Lower contact 17: The second support layer 22B: Thinned area S101~S105, S201~S205: steps

Figure 1 is a flowchart of the first embodiment of the present invention; Figure 2 is a schematic diagram of the structure formed by steps S101 to S103 of the first embodiment of the present invention; Figure 3 is a schematic diagram of the structure formed in step S104 of the first embodiment of the present invention; FIG. 4 is a schematic diagram of the structure formed in step S105 of the first embodiment of the present invention; Figure 5 is a schematic diagram of the half-bridge drive circuit; Figure 6 is a schematic diagram of the structure of the lower contact portion in the second embodiment of the present invention; Figure 7 is a schematic view of the structure of the second supporting layer in the first embodiment of the present invention; Figure 8 is a schematic view of the structure after the first supporting layer is removed in the first embodiment of the present invention; Figure 9 is a flowchart of the third embodiment of the present invention; Figure 10 is a schematic diagram of the structure formed by steps S201 to S203 of the third embodiment of the present invention; FIG. 11 is a schematic diagram of the structure formed in step S204 of the third embodiment of the present invention; and Figure 12 is a schematic diagram of the structure formed in step S205 of the third embodiment of the present invention.

S101~S105: Steps

Claims (10)

A semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer includes: planning a plurality of device regions and isolation regions on a wafer; respectively building a plurality of device regions and isolation regions on the top surface of the wafer and corresponding to each device region Place a component layer; on the wafer and each component layer will be provided with an interconnection wire layer, the interconnection wire layer is to make a plurality of electronic components in the component layer to form electrical connections with each other according to circuit requirements; A first support layer is provided above the interconnection wire layer; and an etching process is performed on the wafer corresponding to each isolation area. The circle and the interconnection wire layer make each of the element regions form an independent base layer, so that each base layer and its corresponding element layer and each interconnection wire layer respectively form a semiconductor device. The semiconductor device manufacturing process according to claim 1, wherein after the etching process is completed, an opening process is performed to form an upper channel in the support layer, and the upper channel corresponds to the interconnection wire layer, and then, The upper channel is filled with conductive material to form an upper contact part. The semiconductor device manufacturing process according to claim 1, wherein after the etching process is completed, an opening process is performed to form a lower channel in the base layer, and the lower channel corresponds to the interconnection wire layer. The lower channel is filled with conductive material to form a lower contact part. The semiconductor device manufacturing process according to claim 1, wherein after the etching process is completed, a second supporting layer is provided on the bottom surface of each base layer, and then the first supporting layer is removed. The semiconductor device manufacturing process according to any one of claims 1 to 4, wherein after the etching process is completed, an insulating material is filled between each adjacent base layer and each interconnection wire layer. The semiconductor device manufacturing process according to any one of claims 1 to 4, wherein before performing the etching process, a thinning process is performed on the wafer to reduce the thickness of the wafer. A semiconductor device manufacturing process for forming a plurality of isolated base layers on the same wafer includes: planning a plurality of device regions and isolation regions on a wafer; respectively building a plurality of device regions and isolation regions on the top surface of the wafer and corresponding to each device region A component layer is placed; an interconnection wire layer is provided on the top surface of the wafer and each component layer, and the interconnection wire layer enables a plurality of electronic components in the component layer to form electrical connections with each other according to circuit requirements; An etching process is performed on the wafer corresponding to each of the isolation regions. The etching process is to etch from the top surface of the interconnection wire layer downward until it penetrates the interconnection wire layer, and part of the wafer is etched from its top surface. Recessed downward; providing a first support layer above each interconnection wire layer; and performing a thinning process on the wafer to reduce the thickness of the wafer until each of the device regions forms an independent substrate Layer, so that each of the base layer, each of the corresponding element layer and each of the interconnection wire layers respectively form independent semiconductor devices. The semiconductor device manufacturing process according to claim 7, wherein after the etching process is completed, an insulating material is filled between each adjacent base layer and each interconnection wire layer. The semiconductor device manufacturing process according to claim 7 or 8, wherein after the first supporting layer is provided, the following steps are further performed: an opening procedure is performed to form an upper channel in the first supporting layer, the The upper channel corresponds to the interconnection wire layer; and After the upper channel is filled with conductive material to form an upper contact part, the thinning process is performed. The semiconductor device manufacturing process according to claim 7 or 8, wherein after the thinning process is completed, a second supporting layer is provided on the bottom surface of each base layer, and then the first supporting layer is removed.

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