TWI745797B - Monolithic integration techniques for fabricating photodetectors with transistors on same substrate - Google Patents

Abstract

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

Description

Monolithic integration technology for manufacturing photodetectors with transistors on the same substrate

The embodiments of the present disclosure are related to the design of semiconductor devices, and more specifically, to the monolithic integration of semiconductor photodetectors and transistors. Priority claim This application claims priority for the following provisional patent applications: U.S. Provisional Patent Application No. 62/083,321 filed on November 24, 2014; U.S. Provisional Patent Application No. 62/ filed on February 5, 2015 112,615; U.S. Provisional Patent Application No. 62/193,129 filed on July 16, 2015; and U.S. Provisional Patent Application No. 62/197,098 filed on July 26, 2015. This article incorporates all of them in full by reference.

Stimulated by huge amounts of data, cloud computing, and other computer networks and telecommunications applications, the demand for high-speed telecommunications components is increasing. High-speed optical transmitters and receivers (or, collectively referred to as "transceivers" in this article) capable of transmitting rates exceeding 25Gbps have attracted the attention of the general public.

Although optical receivers are becoming more and more popular; however, semiconductor photodetector (PhotoDetector, PD) manufacturing technology is often different, and sometimes even incompatible with other types of semiconductor device manufacturing technology, for example, for metal Manufacturing technology of Metal Oxide Semiconductor (MOS) transistors. Therefore, the conventional PD device is manufactured and packaged separately from other related integrated circuits (for example, a TransImpedance Amplifier (TIA) chip). Unfortunately, this separation has become a bottleneck for high-frequency communication. To overcome this limitation, it is better to manufacture the PD devices and the TIA on the same chip, which is called "monolithic integration" of PD and TIA. However, various problems accompany this monolithic integration.

It has been observed that one of the main reasons for the high-frequency bottleneck of optical transmitters mentioned above is optical devices (for example, photodetectors (PD) or sensors) and other circuits (for example In other words, there is a physical separation between a transimpedance amplifier (TIA), other amplifiers, or an analog to digital converter (ADC). A typical optical device used to receive optical signals is a PIN diode, which contains two highly-doped semiconductor layers with opposite polarities (that is, one of them is "p-type" and the other is "N-type") and a photon absorption layer (that is, "intrinsic") sandwiched between the two layers. On the other hand, an amplifier usually includes a group of transistors (for example, complementary metal oxide semiconductor (CMOS) or a combination of bipolar and CMOS technology (BiCMOS)). In the context of P-I-N PD, the term "highly doped" can usually be understood as a doping concentration above 1018 cm-3; the term "essential" can usually be understood as a doping concentration below 1017 cm-3.

As mentioned above, in order to overcome this limitation, it is better to manufacture the PD devices and the transistors (for example, TIA) on the same wafer, which is called the "monolithic" of PD and transistors. Integration". However, various problems accompany this monolithic integration. In this regard, one of the important problems of monolithic integration is the huge step height difference between PD devices (typically ranging from 500 nm to 3 μm in height) and CMOS transistors (typically about 100 nm in height). Using such a huge original step height difference between the two types of devices, when the standard middle-of-line (MOL) process is applied to the two devices to form contact plugs, these electrical The height of the MOL contact plug of the crystal must be greatly increased to match the height of these PDs. This situation is illustrated in Figure 1.

FIG. 1 shows a cross-sectional view of a conventional monolithic integrated semiconductor structure 100, which has a PD device 110 and a CMOS field-effect transistor (FET) (MOSFET) device 120 with a perpendicular incidence. The devices 110 and 120 are fabricated on a substrate 102, usually based on silicon. FIG. 1 also shows a plurality of Shallow Trench Isolation (STI) feature elements 108, which separate the PD 110 and the transistor 120. The STI is an integrated circuit characteristic element, which prevents or reduces current leakage between adjacent semiconductor devices. The STI feature elements 108 are usually formed early during the semiconductor manufacturing process, before the transistor is formed. Example key steps of the STI process include: etching a trench pattern on the top surface of the silicon substrate 102; depositing one or more dielectric materials (for example, silicon dioxide) to fill the trenches; and removing Excess dielectric. After the STI feature elements are formed on the substrate 102, the isolated "islands" (referred to as hillocks (for example, hillock 104(1) and hillock 104) (2))) The upper forming device.

In integrated circuit (IC) chip manufacturing, the process of manufacturing a semiconductor wafer is divided into multiple different stages or step groups. These stages are usually called Front-End-Of-Line (FEOL), Middle-Of-Line (MOL), and Back-End-Of-Line (BEOL). The FEOL stage generally refers to a stage used to form a device (for example, a transistor) on or in a semiconductor wafer, for example, the formation of doped regions, active regions, etc. The MOL stage is the stage where the conductor structure is connected to the FEOL devices. The BEOL stage is the final wafer processing stage. In this stage, an active area is connected to the external circuit system. It should be noted that one or more of the views of the technology introduced in this article have the ability to break the traditional boundaries between FEOL, MOL, and BEOL used to manufacture photodetectors during monolithic integration (and their associated Therefore, for the purpose of this disclosure, the FEOL phase ends when the transistor devices are formed (that is, without their contact plugs), and the BEOL phase starts from depositing the first interconnect The metal layer (M1) starts, all has nothing to do with the manufacturing progress of the light detector device.

Specifically, in a typical IC chip construction, the MOL stage bridges the FEOL stage to the BEOL stage. That is, these semiconductor devices are formed in the FEOL phase, and interconnects and windings are formed in the BEOL phase. The MOL stage usually connects FEOL and BEOL by using interconnect materials that prevent BEOL metal from diffusing into the FEOL device. Specifically, these FEOL transistor devices are usually processed with monocrystalline silicon and/or polycrystalline silicon. The BEOL interconnect lines are usually made of a plurality of metals with low resistivity; the conductor body is copper or aluminum. If copper or aluminum diffuses into these FEOL silicon-based devices, it will cause the characteristics of the transistor to be attenuated. This is the main reason for MOL connection. This connection is often made of refractory metal (e.g., tungsten) and a specific barrier layer (e.g., titanium nitride (TiN) and titanium tungsten (TiW)). Although tungsten has a higher resistivity than other metals, its ability to prevent copper diffusion while still maintaining sufficient conductivity is desirable. In addition, refractory metals generally have much higher resistance to electromigration than copper or aluminum, thereby providing better device reliability under high electrical stress.

As shown in FIG. 1, using the huge step height difference between the PD 110 and the transistor 120, the height of the MOL contact plug 130 of the transistor must be greatly increased to match the height of the PD. However, the contact plug of the device (similar to the channel between the metal interconnection layer) is usually created or excavated by using directional dry etching, and its characteristic will provide a direction towards the source/drain region of the transistor. The tapered shape is for the purpose of electrical connection. Using this tapering feature and under the assumption that the distance between the source region and the drain region of a particular semiconductor technology is usually fixed, if the height of the contact plug is too large, then the source and the drain of the transistor 120 The contact plugs of the drain will become too close to each other, or even overlap each other, for example, as shown in area 132 in FIG. 1. This presents a serious reliability problem because the region 132 can easily create an electrical short circuit between the source region and the drain region of the transistor 120.

In addition to reliability issues, under the assumption of a specific semiconductor manufacturing technology, the performance of a transistor is usually tightly coupled with its physical dimensions (including the height of its contact plugs). Therefore, very high metal contact plugs will cause higher parasitic resistance in these CMOS transistors than designed, which will negatively affect the performance of the transistor 120.

Furthermore, another problem is the additional heat requirement imposed on the CMOS FET devices when they are manufactured alongside the PD devices, which exposes the FET devices to PD-related processes. More specifically, high-speed PDs are usually made of photosensitive materials, such as Ge, GaAs, and InGaAs, which are not stable at the FEOL process temperature of a specific CMOS FET. On the other hand, the epitaxial temperature of PD photosensitive materials is usually higher than the endurance temperature of BEOL metals.

In addition to other reasons, for example, the selection of materials for silicide formation, the aforementioned temperature constraints and step height constraints also make it very difficult to select the photosensitive materials for these photosensitive materials during the monolithic integration process. Insert the point appropriately. When the technology moves toward higher-speed PDs (for example, transfer rate> 25Gbps) and more advanced CMOS technology nodes (for example, technology nodes <90nm), these problems will be exacerbated; for example, because When the length of the transistor gate becomes shorter, the source and drain will be closer to each other, causing design difficulties and reliability problems in the redundant contact plugs.

Accordingly, this article introduces various techniques to alleviate or overcome these problems associated with the monolithic integration of PDs and transistors. Examples of the various technologies introduced in this article include, but are not limited to: the height adjustment method of the bump during the shallow trench isolation (STI) configuration (or simply the modified STI method), the transistor channel priority Mode, and multi-absorbing layer mode. As further explained below, the techniques introduced in this article include the ability to individually and/or jointly solve or alleviate one or more of the traditional limitations associated with manufacturing PD and transistors on the same substrate (for example, the reliability issues discussed above) , Performance issues, and process temperature issues). Using the technology introduced, the design performance of the transistor can be maintained and the PD thickness sufficient to have good performance can be achieved without sacrificing the transistor due to the step height difference between the transistor and the PD device. The traditional dilemma of the performance and reliability of the PD or the performance of the PD.

In the following description, although a monolithic integration example between PD and CMOS transistor is used to explain various techniques that can be implemented for manufacturing PD and transistor on the same substrate; however, it is only for the purpose of explanation. However, it should be noted that the applicability of the technology introduced in this article is not limited to any particular type of PD and/or transistor. For example, at least some of the techniques described in this article can be used for BiCMOS transistors and/or waveguide-based PDs.

Furthermore, many clear details will be put forward in the following description in order to have a thorough understanding of the present disclosure. Those who are familiar with this technology will understand that even without these clear details, the technology introduced in this article can still be implemented. In other instances, well-known features (for example, specific manufacturing techniques) will not be described in detail, so as not to unnecessarily obscure the present disclosure. This description refers to "an embodiment", "one of the embodiments", or similar terms, which means that a specific feature, structure, material, or feature described is incorporated into at least one of the contents of this disclosure In one embodiment. Therefore, the terms appearing in this specification do not necessarily all denote the same embodiment. On the other hand, these references are not necessarily mutually exclusive. Furthermore, these special features, structures, materials, or features can also be combined in any suitable manner in one or more embodiments. In addition, it should be understood that the various exemplary embodiments shown in the drawings are merely illustrative examples, and are not necessarily drawn to scale.

In this article, the terms "coupled" and "connected" and their derivatives may be used to illustrate the structural relationship between devices. It should be understood that these terms are not synonymous with each other. To be precise, in a special embodiment, “connected” can be used to indicate that two or more components are in direct physical or electrical contact with each other. "Coupled" can be used to mean that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediate elements between them), and/or the two or more elements cooperate with each other or It is interaction (for example, causation).

The terms "above", "below", "between", and "above" as used herein refer to the relative positions of one of the material layers and the other material layers. In this regard, for example, one of the layers disposed "above" or "below" another layer may be in direct contact with the other layer, or there may be one or more intermediate layers. Furthermore, one of the layers arranged "between" the two layers may be in direct contact with the two layers, or there may be one or more intermediate layers. Conversely, a first layer above a second layer will contact the second layer. In addition, the relative position of one layer to the other layers assumes that the operation is performed relative to a substrate, without considering the absolute orientation of the substrate. The term "atop" means "at the top of".

Similarly, "above" and "below" are usually used in this article to describe the relative physical positions of different devices, layers, sections, parts, etc. based on the shortest distance between them and the semiconductor substrate. For example, a first layer "above" a second layer means that when measured from the substrate at the same horizontal level, the distance between the first layer and the substrate is farther than the second layer . Conversely, a first layer "below" a second layer means that when measured from the substrate at the same horizontal level, the distance between the first layer and the substrate is closer to the second layer. As used herein, “horizontal” means parallel to the planar surface of the substrate, for example, the horizontal axis 101 shown in FIG. 1.

It will be understood from the text that the term "immediately" or "directly" can be regarded as "physical contact"; for example, unless it is contrary to the text, "immediately" or "directly" is A first layer "above" a second layer means that the first layer is above the second layer and is in physical contact with the second layer.

As used herein, the "contact plug", "contact channel", or "contact" of a device refers to any substance located between the doped region of the device and the first interconnect layer of the device On the vertical wires. The term "interconnect" refers to any substantially horizontal wires between devices for signal transmission/communication between devices. The "first" interconnection layer refers to the lowest interconnection layer. Obviously, using the technology introduced in this article, the first interconnection layer is device-specific; that is, in some embodiments, even if two devices are manufactured on the same wafer, the first interconnect layer of one of the devices An interconnection layer can also be different from the first interconnection layer of another device. How to adjust the height of the bump during the shallow trench isolation configuration

FIG. 2 shows a cross-sectional view of a monolithic integrated semiconductor structure 200 incorporating one or more aspects of the disclosed technology of the present invention. The structure 200 includes a PD device 210 and a transistor device 220. Both the devices 210 and 220 are fabricated on the substrate 202. FIG. 2 also shows a plurality of shallow trench isolation (STI) features 208, which are formed on the substrate 202 by etching before the devices 210 and 220 are fabricated, thereby leaving hillocks (for example, Tubules 204(1) and 204(2)), on which devices 210 and 220 are formed.

As mentioned above, one of the problems associated with the conventional monolithic integration of PDs and transistors is the huge step height difference between PD and transistors. Accordingly, one of the viewpoints of the technology introduced in this article includes a modified STI method to reduce the step height difference. More specifically, after the STI feature elements 208 (and their corresponding bumps) are formed on the semiconductor substrate 202, an additional step is performed to adjust the bumps for the photodetector 210 (for example For example, the relative height between the hillock 204(1)) and the hillock used for the transistor 220 (for example, the hillock 204(2)), so as to compensate for the step height difference. This can be achieved by reducing the height of the humps 204(1) for the photodetector 210 (for example, by etching the humps 204(1)) or by increasing the humps 204(1) for the transistor 220 The height of 2) (for example, by growing additional substrate material on the hill 204(2)). This adjustment will be implemented until the top surface of the hill 204(1) for the photodetector 210 becomes lower than the top surface of the hill 204(2) for the transistor 220 in order to achieve the purpose of height compensation.

Furthermore, in a preferred embodiment, after the adjustment, the bump 204(1) remains higher than the bottom surface of the isolation trench STI 208. Depending on the field application, this may be better than the bottom of the tutu 204 (1) not higher than the STI 208; the example benefits of this preferred embodiment may include: (1) This structure provides better device isolation effect, Especially in PD devices, (2) this structure provides greater flexibility to control the height of the PD device, and (3) this structure reduces the STI dielectric disc during STI Chemical-Mechanical Polishing (CMP)化 (dishing).

After adjusting the height of the hills above, the transistor 220 and the PD 210 will be fabricated on their respective hills 204(2) and 204(1). Using the modified STI method introduced in this article can reduce the step height difference between the PD and the transistor.

3A to 3R show cross-sectional views of various process steps for manufacturing the semiconductor structure 200 of FIG. 2 according to some embodiments. It should be noted that although these process steps are described and/or depicted as being performed in a specific order; however, these steps can also include more or fewer steps, which can be performed sequentially or in parallel. In addition, the order of two or more steps may be changed, the implementation of two or more steps may overlap, and two or more steps may be combined into a single step. In addition, although the steps introduced herein may include specific details for manufacturing a specific embodiment (for example, the structure depicted in FIGS. 2, 4A, and 6A); however, one or more of these steps The steps can also be modified to create different embodiment variations (for example, the structures depicted in FIGS. 4B and 6B or described in other parts of this document). For the sake of simplicity, obvious corrections to the steps used to create the variant embodiments introduced herein will be omitted. For example, in one of the variants, the height of the bump 204(1) of the PD device 210 will be reduced to the same height as the bottom of the STI feature element 208, and those skilled in the art will know how to add, Remove and/or modify the steps described in this article in order to make this variation. For simplicity, well-known steps or details may be omitted.

Referring to FIGS. 3A to 3R, exemplary process steps for manufacturing the semiconductor structure 200 are described in the drawings. In step 301 (FIG. 3A ), a stop layer 201 is deposited on the substrate 202 to form the STI trenches on the substrate 202. The stop layer 201 has a pattern for defining the STI feature elements (and complementary bump feature elements). Then, the transistors and the active regions of the photodetector (the mound structures 204(2) and 204(1), respectively) are patterned and defined (for example, by using etching).

In step 302 (FIG. 3B), an isolation material (for example, oxide) 203 is deposited and ground down to the surface of the stop layer by CMP, thereby forming the STI. In step 303 (FIG. 3C), a thin oxide layer is deposited on the wafer to protect the transistor active regions (for example, the bumps 204(2)). The oxide at the top of the active area of the photodetector is then defined by lithography and removed. In step 304 (FIG. 3D), the stop layer of the photodetector is removed, and the height of the PD substrate mound (for example, the mound 204(1)) is reduced. For example, the height reduction process can be achieved by wet etching or dry etching (for example, using a chemical agent with high etching selectivity to the substrate material). The amount of height reduction will be determined based on the height difference between the transistor and the photodetector in the design. In the alternative implementation method, the tutu 204(2) is epitaxially grown to increase its height. In practice, the relative height between the hillock 204(1) and the hillock 204(2) will be adjusted.

In step 305 (FIG. 3E ), ion implantation is performed on the active regions of the photodetectors to define the well flat area 211. In step 306 (FIG. 3F), oxide 205 is deposited on the wafer to protect the photodetector area, and then a CMP planarization process is performed, which terminates at the stop layer of the transistor. In step 307 (FIG. 3G), transistors (for example, transistor 220) are formed on the tops of their respective active regions of the mound (for example, the mound 204(2)). It should be noted that step 307 marks the end of the FEOL phase. In step 308 (FIG. 3H), the mid-line oxide 207 is deposited to cover the top of the transistor, and then planarized in step 309 (FIG. 3I), the top of the active area of the photodetectors The oxide layer of is removed to expose the photodetector hills (for example, the hills 204(1)).

In step 310 (FIG. 3J), the photosensitive material 213 is selectively deposited so that it is only deposited on the active area of the photodetector. In some implementations, the photosensitive material 213 contains germanium, and a plurality of small facets are formed near the sidewalls of the hillock 204(1) during the epitaxial process. In some embodiments, a buffer material 212 is deposited before the photosensitive material 213 is deposited. The buffer material 212 is usually a material similar to or equivalent to the substrate material. In step 311 (FIG. 3K), a passivation layer 215 is formed by first depositing a blanket passivation layer, then performing top contact implantation, and doping the upper region 214 of the photosensitive layer 213 to and The doped substrate layer 211 has the opposite polarity. It should be noted that in this example, the layer 214 is formed after the passivation layer is configured, and therefore, a part of the passivation layer 215 will be doped to form the layer 214 at least partially. Next, in step 312 (FIG. 3L ), the passivation layer 215 is patterned by using lithography and dry etching processes, leaving only the passivation layer 215 on the photosensitive material 213. In an alternative example, in step 311, the upper region 214 of the photosensitive layer 213 is first doped to the opposite polarity to the doped substrate layer 211, and then in step 312, the passivation layer 215 is selected It is deposited sexually so that it is only deposited on the photosensitive material 213. The doped upper region 214 can be defined by ion implantation or by in-situ doping during the epitaxial process. Then, a photodetector hard mask layer 209 is deposited over the entire wafer. The hard mask layer 209 can be used to pattern the photodetector hills and CMP or etch-back stop layer at the level of interlayer dielectric layer planarization.

In step 313 (FIG. 3M), the photodetector ridges are patterned using typical lithography and dry etching processes. In one or more embodiments, when using this patterning technique, a plurality of photosensitive material rings 216 are left near the sidewall of the oxide, as shown in FIG. 3M. Furthermore, in some embodiments, the rings 216 can be removed, but it should be noted that the removal process may increase the cost and technical difficulty because the rings 216 and the light detector 210 Share the same structure and materials. Next, in step 314 (FIG. 3N), a passivation spacer 217 is formed at the sidewall of the photodetector hill 204(1). According to some implementations of this process technology, the sidewall spacer 217 will also be formed beside the photosensitive ring 216 near the edge of the oxide. In step 315 (FIG. 30), an interlayer dielectric 291 is deposited to fill the gap between the photodetector hill and the original oxide. Then, it is planarized by etching back or CMP. In some variations, the hard mask 209 serves as a planarization stop layer; and in some examples, another dielectric layer is then deposited on the top of the wafer to ensure that it spans the wafer There will be a uniform dielectric thickness above the photodetector hills to achieve optical purposes. In some implementations, steps 313 to 315 will be omitted, and step 316 will be implemented immediately after the top passivation layer is formed (step 311).

In step 316 (FIG. 3P), an opening 231 for the contact channel between the photodetector and the transistor is formed. It should be noted that, because there are various contact depth relationships between the two types of devices, a separate contact opening process may be required. In addition, the silicide configuration can also be implemented during or before the contact channel configuration to improve the contact resistance, thereby improving device performance. Next, in step 317 (FIG. 3Q), the metal configuration for both the transistor contact channel 230 and the PD contact channel 240 is implemented by metal deposition and CMP. In step 318 (FIG. 3R), a standard back-end metal interconnection 250 is formed. According to one or more embodiments, the communication between the two types of devices (for example, PD 210 and transistor 220) can be achieved through the first metal layer (ie, M1) or any layer above .

In one or more implementation methods, the photosensitive material 213 is or contains germanium (Ge). Exemplary materials for the substrate 202 can be silicon (Si) or silicon-on-insulator (SOI). The passivation layer 215 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric, silicon dioxide (SiO ₂ ), or any combination thereof. In some examples, the passivation spacer 217 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric, silicon dioxide (SiO ₂ ), or any combination thereof. The material used for the photodetector hard mask layer 209 can be nitride, and the material used for the interlayer dielectric 291 can be SiO ₂ . The trench isolation oxide 203 can be SiO ₂ , and the transistors (for example, the transistor 220) can be silicon-based transistors. The photodetectors (for example, PD 210) can be of a vertical incidence type, in which optical signals can be incident from the top through the dielectric layer 493 or from the bottom through the substrate 402.

In some alternative embodiments, at least a part of the semiconductor material used in the PIN structure may be different from the semiconductor substrate material; for example, the highly doped P region and the intrinsic region can be germanium-based, and highly doped The doped N region can be based on silicon (for example, the N region is defined on a silicon substrate). Furthermore, in some embodiments, the intrinsic photosensitive region of the PD 210 includes a semiconductor material stack, which includes a substrate semiconductor material with a dielectric constant smaller than the material in the intrinsic photosensitive region. In these embodiments, the thickness ratio between the substrate semiconductor material and the other semiconductor materials in the bonded intrinsic photosensitive region may be greater than 1 to 5, so that the effective capacitance will be reduced at higher operating speeds. In other words, in some embodiments with the semiconductor material stack in their photosensitive area, the thickness of the silicon layer in the stack will not be thinner than 1/5 of the germanium layer in the stack, so as to form a High-frequency wide light detector. In one example, the germanium layer is 500 nm, and the thickness of the silicon layer is greater than 100 nm.

In an alternative embodiment, the photodetector hills are located at the same level as the bottom of the STI trenches, so as to fully compensate for the step height difference between the photodetector and the transistor. possibility. However, in this alternative example, the device isolation effect (especially for PD devices) may not be as good as the embodiment shown in FIG. 2, and there may be more oxide dielectric during the STI CMP process. The problem of qualitative discriminating. Transistor channel priority mode

FIG. 4A shows a cross-sectional view of another monolithic integrated semiconductor structure 400 incorporating one or more aspects of the disclosed technology of the present invention. The structure 400 includes a PD device 410 and a transistor device 420. Both devices 410 and 420 are fabricated on the substrate 402. 4A also shows a plurality of shallow trench isolation (STI) features 408, which are formed on the substrate 402 by etching before the devices 410 and 420 are manufactured, leaving hills (for example, protrusions) The mounds 404(1) and 404(2)), on which devices 410 and 420 are formed. The structure has a plurality of transistors (for example, transistor 420) and a plurality of PDs. The transistors are located on a set of bumps specially formed for the transistors, and the PDs are located on On the other set of tutu. In other implementations, the PD humps 404(2) may have a lower height than the transistor humps 404(1) as appropriate, so as to further compensate for the step height difference between the PD 410 and the transistor 420, such as The above discussion of the modified STI method.

As mentioned above, one of the problems associated with the conventional monolithic integration of PDs and transistors is the huge step height difference between PD and transistors. It is further observed in this disclosure that, for reliability reasons, standard MOL processes (for example, tungsten configuration) are usually used to form contact plugs of the device. Specifically, because transistors are forward-biased devices, their working principle requires a relatively large amount of current to pass. If the contact plugs of these transistors are made of BEOL metal (for example, copper or aluminum), the large amount of current will cause electromigration, which may lead to device malfunction and/or shorter device life. In addition, the electromigration of the BEOL metal will also cause the characteristic degradation of the transistor. Therefore, the MOL process uses refractory metals (for example, tungsten) to form contact plugs for transistors. However, unlike transistors, photodetectors are reverse-biased devices, which means that their working principle does not require a large amount of current to pass through them.

Accordingly, one of the viewpoints of the technology introduced in this article includes a modified contact channel method. In this special way, the contact channels for these transistors will be manufactured such that: (1) Their dimensions (for example, height) will be optimized for the corresponding manufacturing technology (usually manufacturing Commercial specific) in order to achieve the purpose of performance, and (2) the use of conventional refractory metals (for example, tungsten) as the contact metal in order to achieve the purpose of reliability. Conversely, in this approach, the contact channels used for the PDs are manufactured during the post-production (BEOL) process, and in some embodiments, the BEOL interconnect metal (e.g., copper (Cu) Or aluminum (Al)) to form at least a part of the PD contact plugs. Specifically, in some embodiments, transistors are manufactured first until their MOL contact channel (for example, contact channel 430) is formed. The bodies of these PDs are then manufactured. Then, the PD contact channels (for example, the contact channels 440) are formed during the configuration of the BEOL interconnect metal layer (for example, the M1 layer). That is to say, as further explained below in conjunction with FIGS. 5A to 5Q, the transistors are first formed on the semiconductor substrate during the front-end (FEOL) manufacturing stage. Then, during the mid-line (MOL) manufacturing stage and before the photodetectors are formed on the semiconductor substrate, the contact plugs for the transistors are formed by using refractory metal. Then, the light detectors are formed on the semiconductor substrate. Then, the contact plugs for these photodetectors will be formed during the BEOL manufacturing stage.

The structure 400 introduced herein further provides a way to solve the problem of step height discussed above in conjunction with FIG. 1. The advantage is that this modified channel configuration does not require two types of devices to contact the same MOL metal layer, thereby eliminating all the problems associated with this requirement. As observed in this article, because the PD operates under a reverse bias with a very low output current, the modified contact channel configuration method using this modification will have little or no electromigration problem. In addition, the tuft adjustment technology discussed above in conjunction with Figure 2 can also be combined with this modified contact channel mode as appropriate. For example, the benefits of combining the tuft adjustment technology include providing more complete protection of the PD active area by the dielectric during the transistor manufacturing process, and providing additional step height compensation for the two devices.

FIG. 4B shows a cross-sectional view of a monolithic integrated semiconductor structure 401 as a variation of the structure 400 shown in FIG. 4A. The structure 401 has the same design concept as the structure 400, but has a different PD metal contact configuration. It does not use the first BEOL metal layer (ie, M1) to form the top contact and bottom contact of the PD. Instead, the structure 401 uses the first BEOL metal layer (M1) to form to contact the The contact channel 441 of the bottom electrode, and another metal layer above it (for example, the second BEOL metal layer (M2)) is used to form a contact channel 442 for contacting the top electrode. This modification example can be used in the case where the step height difference between the PD and the transistor is too large to perform height compensation only in the first BEOL metal layer.

5A to 5Q show cross-sectional views of various process steps for manufacturing the semiconductor structure of FIG. 4A according to some embodiments. It should be noted that although these process steps are described and/or depicted as being performed in a specific order; however, these steps can also include more or fewer steps, which can be performed sequentially or in parallel. In addition, the order of two or more steps may be changed, the implementation of two or more steps may overlap, and two or more steps may be combined into a single step. One or more of these steps can also be modified to create different embodiment variations. For simplicity, well-known steps or details may be omitted.

Referring to FIGS. 5A to 5Q, exemplary process steps for manufacturing the semiconductor structure 400 are described. In step 501 (FIG. 5A), the transistor active regions (for example, the hills 404(2)) and the PD active regions (for example, the hills 404(1)) will use standard shallow grooves A trench isolation (STI) process is defined and patterned on the substrate 402. In step 502 (FIG. 5B), the PD active area (for example, the hill 404(1)) is excavated and may be concave as appropriate (for example, for step height compensation). The upper region of the bump 404(1) is then doped to one of the electrical polarity through ion implantation, thereby forming the bottom doped layer 411 of the PD 410. In step 503 (FIG. 5C), a dielectric material 405 (for example, oxide) is deposited on the wafer to cover the devices, and then, the wafer is planarized (for example, By using a chemical-mechanical polishing (CMP) process). Preferably, the polishing process should stop on relatively high transistor hillocks (for example, hillock 404(2)), leaving the active area of PD (for example, hillock 404(1)) It will still be protected by the dielectric 405 during the subsequent transistor manufacturing steps.

In step 504 (FIG. 5D), devices for front-of-line (FEOL) transistors (for example, transistor 420) are formed in their respective active areas of the hill (for example, hill 404(2) )) at the top. In step 505 (FIG. 5E), MOL dielectric 407 is deposited to cover the transistors on the wafer, and then the wafer is planarized. In step 506 (FIG. 5F), the transistor contact channel 430 is formed using standard MOL refractory metal (for example, tungsten).

In step 507 (FIG. 5G), a dielectric material 409 is deposited to completely cover and protect the MOL metals. In step 508 (FIG. 5H), the dielectric layer on the top of the PD active regions (for example, the hillock 404(1)) is removed to expose (or "dig out") the At least part of these PD active areas. In some implementations, the area created by the opening can be larger than the final PD area, so as to achieve a relatively flat surface at the top of the PD, while removing one or more small cuts near the sidewalls of the opening. Face area (for example, small facet 960 shown in Figure 9B). As explained below, these small facet areas can be formed during the selective epitaxial growth process. In step 509 (FIG. 5I), the photosensitive material 413 is selectively deposited so that it is deposited only or at least mostly on the active area of the photodetector. Optionally, a buffer material 412 may be deposited before the photosensitive material is deposited. The buffer material 412 can be a material similar to or equivalent to the substrate material. In step 510 (FIG. 5J), the upper region of the photosensitive layer will be doped to the opposite polarity of the doped substrate layer to form the top doped region 414, thereby forming a PIN photodetector structure together 410. For example, the top doped region 414 can be defined by ion implantation or by in-situ doping during the epitaxial process.

In step 511 (FIG. 5K), a passivation layer 415 is selectively deposited so that it is deposited only on the photosensitive material 413. In other implementations, the layer 415 will be formed by first depositing a blanket passivation layer and then patterning using lithography and dry etching processes, leaving only the passivation layer on the photosensitive material 413 415. In another embodiment, the layer 414 can be formed after the passivation layer is configured. A PD hard mask layer 409 is then deposited on the wafer. The hard mask layer 409 can be used to pattern photodetector hills and CMP or etch-back stop layers at the level of interlayer dielectric layer planarization.

In step 512 (FIG. 5L), the photodetector ridges are patterned using typical lithography and dry etching processes. In some embodiments, when using this patterning technique, residual photosensitive material may remain near the sidewall of the oxide to form a ring 416, as shown in FIG. 5L. In step 513 (FIG. 5M), passivation spacers 417 are then formed at the sidewalls of the PD mound 404(1). According to some implementations of this process technology, the sidewall spacer 417 can also be formed beside the photosensitive ring 416 near the edge of the oxide. In step 514 (FIG. 5N), an interlayer dielectric 491 is deposited to fill the recessed area formed by the previous etching process. Then, planarization is performed by etchback or CMP, which stops at the PD hard mask 409. In step 515 (FIG. 50), another dielectric layer 493 is deposited on the top of the wafer to ensure a uniform dielectric thickness across the wafer and above the PD bumps to achieve The purpose of optics. In some implementations, one or more parts of steps 512 to 514 will be omitted, and step 515 will be implemented immediately after the top passivation layer is configured (step 512).

In step 516 (FIG. 5P ), a plurality of openings 431 are dug to establish contact channels for the back metal layer (M1) of the first production line. Specifically, the openings in the PD area are used to form the contact channel 440 of the PD. Obviously, the opening in the transistor region will form an additional contact channel, which will connect to the formed MOL contact channel 430 and/or serve as a local interconnection line for signal transmission between the transistors. In one or more examples, to create different contact depths for the two devices, the openings for the PDs and the openings for the transistors are patterned separately. The opening 431 is then filled with BEOL metal (for example, copper) by metal deposition in step 517 (FIG. 5Q), and then CMP is performed. In some implementations, the silicide configuration can also be implemented in PD manufacturing during or before the PD contact channel configuration (for example, step 516) to improve the contact resistance, thereby improving device performance . The PD silicide formation process and the materials used can be different from the transistor silicide formation process.

For the purpose of simplification, although not shown in FIG. 5P; however, one or more liners may also be deposited above the opening 431 before the BEOL metal is deposited. These liners have a function as a diffusion barrier for the BEOL metals (for example, copper or aluminum). Typical materials used for these linings include: titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN),... and so on. The thickness of these liners depends on the manufacturing technology, but is usually very thin; for example, in the 65nm technology node, the liner of the contact plugs may be about 2-10nm thick. It should be noted that for the purposes discussed in this article, especially for the materials used for the contact plugs, these linings will not be regarded as any part of the contact plugs.

In one or more implementation methods, the photosensitive material 413 can be GE. Exemplary materials for the substrate 402 can be Si or SOI. The passivation layer 415 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric, silicon dioxide (SiO ₂ ), or any combination thereof. The passivation separator 417 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric, SiO ₂ , or any combination thereof. The material used for the PD hard mask layer 409 can be nitride, and the material used for the interlayer dielectric 491 can be SiO ₂ . The trench isolation dielectric can be SiO ₂ , and the transistors (for example, the transistor 420) can be silicon-based transistors. The light detectors (for example, PD 410) can be of vertical incidence type. The optical signal of the vertical incidence type PD can be incident from the top through the dielectric layer 493 or from the bottom through the substrate 402. Multi-absorbing layer method

FIG. 6A shows a cross-sectional view of yet another monolithic integrated semiconductor structure 600 incorporating one or more aspects of the disclosed technology of the present invention. The structure 600 includes a PD device 610 and a transistor device 620. Both devices 610 and 620 are fabricated on the substrate 602. 6A also shows a plurality of shallow trench isolation (STI) features 608, which are formed on the substrate 602 by etching before the devices 610 and 620 are manufactured, leaving hills (for example, protrusions) Mounds 604(1) and 604(2)), on which devices 610 and 620 will be formed. It should be noted that other forms of isolation techniques can also be used, for example, including bipolar junction isolation (for example, by implanting opposite types of dopants at the boundary between the transistor and the PD).

One of the problems that comes to mind in the problems associated with the monolithic integration of PDs and transistors is the extra heat required on the CMOS FET devices when the CMOS FET devices are manufactured alongside the PD devices. , It will expose these FET devices to PD related processes. More specifically, high-speed PDs are usually made of photosensitive materials, such as Ge, GaAs, and InGaAs, which are not stable at the FEOL process temperature of a specific CMOS FET. On the other hand, the epitaxial temperature of PD photosensitive materials is usually higher than the endurance temperature of BEOL metals. These temperature constraints and step height constraints make it very difficult to select appropriate insertion points for the photosensitive materials during the monolithic integration process.

Accordingly, one of the viewpoints of the technology introduced in this article includes a modified configuration of photosensitive materials, which simultaneously solves or alleviates the two problems of the temperature limitation and the step height limitation. This special method divides the typical single-step heteroepitaxial process of photosensitive materials into multiple separate epitaxial steps. Or, more importantly, the present invention observes that the controllability of the homoepitaxial photosensitive material growth process is higher than that of the heteroepitaxial photosensitive material growth process. More specifically, because there is usually no lattice matching deviation in the homogeneous epitaxy process, the crystal nuclei involved in this process will become easier and the resulting surface will become smoother, which requires less Annealing process to improve crystal quality. Therefore, the thermal budget used to implement the growth process of the homogeneous epitaxial photosensitive material will be lower than the thermal budget used to implement the growth process of the heteroepitaxial photosensitive material. The melting point of the photosensitive material may also be lower than the melting point of the substrate material, which will cause another process limitation, which limits the design of the heteroepitaxial process for growing photosensitive materials on silicon-based substrates. After the photosensitive material epitaxial process is divided into multiple steps, only the first epitaxial step can be heteroepitaxial and all subsequent steps will become homogeneous epitaxial. Therefore, at least a part of the process for manufacturing transistors with spare parts will now be It is performed between separate epitaxial steps for growing the photosensitive material. This technique removes the conventional inherent height and/or thermal limitations imposed by the BEOL interconnect metal layer. It should be noted that for the purposes discussed in this article, a substantially homogeneous epitaxial process (for example, the growth of germanium (Ge) on a silicon germanium (SiGe) alloy) will be regarded as a homogeneous epitaxial process because of the growth here. A substantially same material in the process at the top of another material can still result in the same benefits (for example, lower processing temperature) as the homogeneous epitaxial process introduced in this article.

In at least some embodiments, the photosensitive material of the first layer of the photodetector (also referred to herein as the "seed layer") is epitaxially grown on a semiconductor substrate, and is located on the photodetector. Above the area being formed. After the seed layer photosensitive material is grown, at least one metal contact plug for the transistor can be formed. Then, after the metal contact plugs for the transistor are formed, a subsequent layer of photosensitive material can be formed to complete the manufacture of the light absorption region of the photodetector. The subsequent photosensitive material layer can be formed on the top of the seed layer, so that the photosensitive material layers can form the light absorption region of the photodetector. By avoiding a single-step epitaxial process for the photosensitive material, the advantage of this method is that it can reduce or minimize the step height difference during the monolithic integration of the PD device and the transistor device and the additional thermal budget problem.

As shown in FIG. 6A, the photosensitive area 613 is divided into two layers 613(1) and 613(2). The two layers 613(1) and 613(2) are epitaxially grown in separate stages during the manufacturing process, but jointly form a continuous photosensitive area. The first layer 613(1) is a relatively thin seed layer, which usually requires a high-temperature surface cleaning process (for example, 750 to 850 degrees Celsius, also known as "pre-baking") before epitaxial growth. The seed layer 613(1) will be inserted at a relatively early stage of the process. Because the seed layer 613(1) can be very thin (for example, 10 nm), the growth of the seed layer will not face the step height problem discussed above. As discussed in detail below in conjunction with FIGS. 7A to 7J, the seed layer 613(1) will then be covered with a dielectric, and the manufacturing process will continue with FET construction. The rest of the photosensitive material 613(2) is grown at a subsequent epitaxial step with more flexible insertion points. As described above, because this subsequent growth is homoepitaxial, there is no need for any high-temperature surface cleaning at this subsequent growth. The process temperature will be much lower than the first growth, and therefore, the subsequent growth step can be inserted at a later part of the FET process. The final height of the PD is only limited by the insertion point of the subsequent growth, and is not limited by the initial growth. In this way, the top surface of the light absorption region of the photodetector will be higher than the bottom of the metal interconnection layer of the transistor, which may not be achieved in the traditional single-step epitaxial process.

Figures 6A to 6C illustrate how different insertion point situations can result in different PD heights. In FIG. 6A, the insertion point is set after the BEOL metal 1 (M1) dielectric layer is formed, and therefore, in the structure 600, the PD height will be as high as the top surface of the M1 dielectric layer. . In contrast, in FIG. 6B, the insertion point is set after the MOL dielectric layer is formed, and therefore, in the structure 601a, the PD height can be as high as the MOL dielectric layer. In FIG. 6C, the insertion point is set before the MOL dielectric layer is formed, and therefore, in the structure 601b, the PD height is lower than the MOL dielectric layer.

It should be noted that because this special technique forms the photosensitive area at two or more different stages, this technique originally requires separate lithography and patterning processes. Therefore, if there is no further processing later, although both the first seed layer and the subsequent growth layer will achieve the same lateral pattern, the sidewalls of the interface between the first seed layer and the subsequent growth layer are still It is expected that there will be at least certain physical discontinuities. This discontinuity is due to the alignment of flaws in lithography in practice. In other words, the light absorption region of the photodetector may exhibit a physical structure with sidewall alignment deviation (or discontinuous sidewalls), which is the use of two or more separate material forming processes to grow the same photosensitive material The result performance.

In addition, alternatively, the photosensitive material can also be patterned after the multi-step deposition, and in some embodiments, it will be covered by another passivation layer. With this additional patterning step, the aforementioned physical discontinuity between the first seed layer and the second epitaxial layer can be removed.

In some embodiments, the photosensitive layer forming process is divided into more than two steps. In addition, using the technology already introduced, the final epitaxial insertion point will be set a little later, so that the PD height will become higher than at least M1, which assumes the final step of epitaxial growth and the formation of the subsequent highly doped layer The manufacturing process is tolerable by BEOL.

The same method can also be applied to the waveguide-based body-coupled PD integrated with the CMOS FET. This method is particularly advantageous when applied to waveguide-based PDs integrated with advanced technology nodes CMOS FETs, because this situation is more sensitive to step height differences and thermal budgets. It should be noted that silicon-on-insulator (SOI) substrates can also be suitable for this application, because the integrated device may contain silicon waveguides.

Using this technology, the height of the PD will become higher than the height restricted by the conventional method without causing the performance of the FET to be impaired. Therefore, this multi-step epitaxial method can solve or reduce the step height difference problem.

7A to 7J show cross-sectional views of various process steps for manufacturing the semiconductor structure of FIG. 6A according to some embodiments. It should be noted that although these process steps are described and/or depicted as being performed in a specific order; however, these steps can also include more or fewer steps, which can be performed sequentially or in parallel. In addition, the order of two or more steps may be changed, the implementation of two or more steps may overlap, and two or more steps may be combined into a single step. One or more of these steps can also be modified to create different embodiment variations. For simplicity, well-known steps or details may be omitted.

Referring to FIGS. 7A to 7J, exemplary process steps for manufacturing the semiconductor structure 600 are described in the drawings. In step 701 (FIG. 7A), the FET active area 604(2) and PD active area 604(1) are defined and patterned on the substrate 602, for example, by using standard shallow trench isolation (STI )Process. In this process, isolation materials 603 (for example, oxides) are filled into the trenches to form STI features 608. In step 702 (FIG. 7B ), the PD active region 604 (1) is first excavated and then doped to one of the electrical polarity by ion implantation, thereby forming the bottom doped layer 611 of the PD 610. Then, the area 604(1) will be covered by the dielectric material 605 again.

In step 703 (FIG. 7C), the FEOL transistor device 620 is formed on the top of the transistor active region 604(2), and the PD active region 604(1) is covered by the dielectric layer. cover. In step 704 (FIG. 7D), the PD active regions 604(1) will be excavated again, and the seed layer 613(1) of photosensitive material will be heteroepitaxially grown on the PD active regions. The thickness of the seed layer 613(1) can be in the range of 5 nm to 500 nm, depending on the technology of the FET node to be integrated. In step 705 (FIG. 7E), a standard MOL dielectric 607 is deposited on the wafer to cover the two types of devices. Next, the wafer will be planarized, and then FET contact metal formation will be performed. Used to form the FET contact channel 630. Then, the BEOL M1 dielectric layer 693 is deposited on the MOL layer.

In step 706 (FIG. 7F), the dielectric layer at the top of the PD active region 604(1) will be excavated, and a subsequent epitaxial growth of the photosensitive material will be implemented to form the second photosensitive layer 613(2) ). Then, the upper region of the photosensitive layer 613 is ion implanted or doped to the opposite polarity of the doped substrate layer to form the top doped layer 614, thereby forming a PIN photodetector.测器结构610。 Detector structure 610. Next, the top passivation layer 615 is selectively deposited on the photosensitive material 613, and a hard mask layer 609 is then deposited on the wafer. In other implementations, the layer 615 is formed by first depositing a blanket passivation layer and then patterning using lithography and dry etching processes, leaving only the passivation layer on the photosensitive material 613 615. In another embodiment, the layer 614 can be formed after the passivation layer is configured.

In step 707 (FIG. 7G), the PD mounds 604(1) will be patterned and then covered by passivation spacers 617 on the sidewalls. In step 708 (FIG. 7H), the gap between the PD bump 604(1) and the dielectric layer (they are caused by the previous patterning) is filled with another dielectric deposit 691. Next, a planarization process will be implemented, which will terminate at the PD hard mask layer 609. In step 709 (FIG. 7I), the PD bottom metal contacts 640 are formed, and then the M1 metal interconnection line 650 is formed. In step 710, the M2 dielectric layer 693 is deposited, and then the PD top metal contact 641 and the M2 metal interconnection 660 are formed. Depending on the design, the interconnect metal configuration can be used to form additional contact channels and/or to communicate between multiple devices. In some implementations, one or more parts of steps 706 to 708 will be omitted, and step 709 will be implemented immediately after the top passivation layer is configured (step 706). In some implementations, the PD bottom contact configuration (step 709) and the top contact configuration (step 710) can be implemented on the same BEOL dielectric layer, but due to their different termination points. Performed in a separate patterning process. In some implementations, the silicide configuration can also be introduced into the PD manufacturing during or before the PD contact configuration (for example, steps 709 and 710) to improve the contact resistance, thereby improving the device efficacy.

In one or more implementation methods, the photosensitive material 613 can be Ge. Exemplary materials for the substrate 602 can be Si or SOI. The passivation layer 615 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric (for example, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )), silicon dioxide (SiO ₂ ), or any combination of them. The passivation separator 617 can be amorphous Si, polycrystalline Si, nitride, high-k dielectric (for example, Al ₂ O ₃ , HfO ₂ ), SiO ₂ , or any combination thereof. The material used for the PD hard mask layer 609 can be nitride, and the material used for the interlayer dielectric 691 can be SiO ₂ . The trench isolation dielectric 603 can be SiO ₂ , and the transistors (for example, the transistor 620) can be silicon-based transistors. The photodetectors (for example, PD 610) can be of a vertical incidence type, in which optical signals can be incident from the top through the dielectric layer 693 or from the bottom through the substrate 602.

Here, the alternative description of the multi-absorptive layer method described above in conjunction with FIGS. 7A to 7J will be described in detail. This alternative description is to provide additional completeness and further understanding of the various benefits of implementing this approach.

Some embodiments of the multiple absorption layer approach include a method of fabricating a photodetector and a transistor on the same semiconductor substrate, using silicon as the top surface of the substrate. The method roughly consists of 5 steps. Step (1): forming at least a part of the transistor before the contact channel configuration of the transistor. Step (2): forming the first light absorbing layer of the light detector in the first selected area on the top of the substrate. Step (3): forming an isolation layer on the top of the first absorption layer. Step (4): removing a part of the isolation layer to expose the second selected area of the first light absorbing layer. The second selected area at least partially overlaps the first selected area. And, step (5): directly forming a second light absorbing layer on the top of the exposed first light absorbing layer. The second light absorbing layer is formed such that the two layers form a single light absorbing area of the photodetector. Therefore, the photodetector can be formed with a thicker combined absorption layer to achieve higher quantum efficiency and higher bandwidth without being limited by the step height and thermal budget during the traditional manufacturing process . Optionally, in step (5), an additional light absorbing layer can be formed by repeating step (3), step (4), and step (5).

The single light absorbing area may have sidewall alignment deviation between the first selected area and the second selected area. This sidewall alignment deviation may be a deliberate or unintentional result of separate lithography steps and etching steps. Similarly, as a result of the above method, in some embodiments, the top surface of the second light absorbing layer is higher than the top surface of the contact channel of the transistor.

According to one or more implementation methods, both the first light absorbing layer and the second light absorbing layer include germanium. The first pre-bake will be implemented before step (2) to clean the heterogeneous interface. Similarly, the second pre-bake will be implemented before step (5) to clean the homogeneous interface. During the first pre-baking, a higher temperature than the second pre-baking can be used, because the first pre-baking does not include any MOL process and BEOL process. Obviously, compared to the homogeneous growth of Ge (for example, grown on Ge), a higher pre-bake temperature may be beneficial to the heterogeneous growth of Ge (for example, grown on Si), because it is compared to removing The passivation layer that is naturally formed on the Ge surface (for example, GeO or GeO ₂ ), the passivation layer that is naturally formed on the Si surface during the manufacturing process may require a higher temperature to remove.

In some embodiments, the first light absorbing layer includes germanium, and a pre-baking temperature of 700 degrees Celsius or more is performed before step (2) to clean the interface between germanium and silicon. In some embodiments, the second light absorbing layer includes germanium, and a pre-baking temperature lower than 700 degrees Celsius is performed before step (5) to clean the homogeneous interface.

In addition, the first selected area will be smaller than the second selected area, so that any manufacturing defects will be at least partially confined in the first selected area. In other embodiments where defects are not the main consideration, the first selected area may not be smaller than the second selected area.

In several examples, the relative height difference between the top surface of the active area of the photodetector and the top surface of the active area of the transistor is formed before step (1). The premise of one or more embodiments of the present invention is that the photodetector and the transistor share at least one of the doped regions on the substrate. Furthermore, in some examples, the combined height of the light absorbing region (composed of the multiple layers) is higher than the bottom surface of the first metal interconnection layer of the transistor.

In a variation, before step (2), a spacer is formed on the sidewall of the first selected area, so that the sidewall of the first absorption layer will be passivated by the spacer. The separator can be intrinsically amorphous silicon, doped amorphous silicon, oxides, nitrides, and/or high-k dielectric materials, so that a selective epitaxy can be used during step (2). The crystal grows so that the multiple layers are mainly grown on the exposed first selected area, not on the separator.

In addition, or, before step (5), a partition may be formed on the sidewall of the second selected area, so that the sidewall of the second absorption layer may be passivated by the partition. The separator can also be essentially amorphous silicon, doped amorphous silicon, oxides, nitrides, and/or high-k dielectric materials, so that a selective The epitaxial growth is such that the multiple layers are mainly grown on the exposed second selected area, not on the separator or the passivation layer.

It should be noted that, according to some viewpoints, the remaining active area of the transistor is formed before step (4), leaving the contact channel of the photodetector to be formed after step (4). For example, the channel contact configuration for the photodetector can be implemented during the configuration of the metal interconnect layer. In some cases, the contact channel of the photodetector is entirely made of non-refractory materials (for example, BEOL metal, such as aluminum or copper) in the metal interconnection layer. Fill shape

8A to 8B are a top view and a cross-sectional view of a monolithic integrated semiconductor structure, which includes filling shapes of different sizes for PDs and transistors, and more specifically, the filling shape 810 is approximately the size of a PD , And the filling shape 820 is about the size of a transistor.

Specifically, the present invention observes that using the monolithic integration of PD and transistors, two devices with very different sizes (for example, a transistor smaller than half the size of a PD) will be manufactured on the same crystal. Round up. Furthermore, when the wafer is manufactured, there will be many manufacturing processes involving material growth (for example, photosensitive material epitaxy) and material removal (for example, CMP planarization or reactive ion etching) , The ideal situation should apply a uniform load to the wafer. However, in reality, the results of these processes are affected by the patterns that have already been manufactured on the wafer. Because of the different sizes of the PD and the transistor, the load on some parts of the wafer may be greater than some other parts, which will have a negative impact on the yield.

Accordingly, in one of the viewpoints of the present disclosure, the device layout is defined such that, in addition to the photodetector active area and the transistor active area, the layout can also include at least two different types Filling shape—photodetector filling shape 810 and transistor filling shape 820. As shown in FIG. 8B, each type of filling shape has the same process flow as its corresponding active device, except that it will not be electrically connected to any other device, thereby acting as a dummy device.

The main purpose of inserting two different filling shapes in the wafer is to achieve uniform process load for the two types of devices in the wafer. In this regard, according to at least some embodiments, each type of filling shape should reach substantially the same height as their individual active devices in order to achieve uniform load. For example, these example filling shapes 810 and 820 are based on the manufacturing process flow discussed above in conjunction with FIG. 2, which has different bump heights for PD and transistors. In this example, the transistor filling shape 820 should be formed on a surface with the same height as other "real" transistors (for example, the hillock 404(2)). Similarly, in this example, the light detector fill shape 810 should be formed on a surface (for example, the hill 404(1)) that has the same height as other "real" light detectors. Depending on the embodiment, the size and density of these shapes will be different. In some examples, the filled shapes of the light detectors are larger and less dense. Applicable light detector configuration method

9A and 9B show cross-sectional views of an additional photodetector (PD) configuration method that can apply one or more aspects of the monolithic integration technology introduced herein. Although the example PD configuration method introduced above generally includes selective epitaxy first, followed by PD active area patterning (for example, through lithography and dry etching); however, the single chip introduced in this article The integration technology can still be applied to other types of PD configuration methods. There are at least two additional PD configuration methods that can be applied, which are shown in Figure 9A and Figure 9B, respectively.

In FIG. 9A, the selective growth area is directly used as the PD active area, and therefore, there is no need to perform any additional PD active area patterning after the selective epitaxial process. Instead, a CMP process is implemented to planarize the surface. Then, a passivation layer is deposited on the top of the photosensitive material to cover the top surface of the photosensitive material. One of the benefits of this configuration method is to reduce the process complexity associated with PD active area patterning and subsequent gap filling/planarization steps.

Another applicable PD configuration method is shown in Figure 9B. In this configuration method, the selective growth area is also directly used as the PD active area. The difference between the methods in FIG. 9A and FIG. 9B lies in the post-epitaxial CMP process. In FIG. 9B, the CMP process in FIG. 9A is omitted, and the photosensitive material still retains its small faceted sidewalls. The advantage of this method is to avoid the CMP dishing problem that may occur in the method of FIG. 9A, especially when the surface dishing is formed during the CMP process in a relatively large area of PD (for example, a diameter greater than 10 μm). ) In the implementation of the CMP process. It should be noted that in some examples of the formation process without CMP, the selective growth area may also be larger than the PD active area, and the etching process similar to that shown in FIG. 5L will be implemented to remove the Some small facets in the sides. in conclusion

Unless it is contrary to physical possibility, the present invention covers: (i) the methods/steps described above can be implemented in any order and/or any combination, and (ii) the devices of individual embodiments can be combined in any manner.

It should be noted that all the embodiments described above can be combined with each other, unless otherwise mentioned above or the functions and/or structures of any such embodiments are mutually exclusive.

Although the present disclosure has been described herein with reference to specific exemplary embodiments; however, it should be confirmed that the present invention is not limited to the described embodiments. On the contrary, it can also fall within the scope of the appended application. Amendments and changes in the spirit and category are implemented. For example, in the present disclosure, although two contact channels are shown in each doped region of one or more structures; however, it is also possible to form a single continuous contact channel in these doped regions Or a ring/shoe-shaped channel to extract the carrier wave generated by light from the light-absorbing area. Accordingly, this specification and the drawings should be regarded as explanatory and not restrictive. Examples of specific embodiments

So, in summary, some example implementations of the disclosed technologies introduced in this article will be described in the numbered clauses below:

(A) How to adjust the height of the tuft during the STI configuration: 1. A method for manufacturing a photodetector and a transistor on the same substrate, the method includes: A structure with two hills is formed on a semiconductor substrate. One hill is used for the transistor and the other hill is used for the photodetector. The mound groove forms an isolation trench, and the two trenches have the same height; Adjusting the relative height between the humps for the photodetector and the humps for the transistor; and The transistor and the photodetector are formed on individual hills. 2. The method according to clause 1, where the relative height adjustment includes: Lower the height of the hill for the photodetector until the top surface of the hill for the photodetector is lower than the top surface of the hill for the transistor but higher than the bottom of the isolation trench Up to the surface. 3. The method according to Clause 2, wherein the lowering of the height of the tuft used for the photodetector includes: Depositing a protective layer on the hill for the transistor to protect it from etching; and The semiconductor substrate is etched to remove the substrate material used for the hillock of the photodetector, so as to reduce the height of the hillock for the photodetector. 4. The method according to clause 1, where the relative height adjustment includes: The height of the hills used for the transistor is increased by epitaxial growth. 5. The method according to Clause 1, wherein the formation of a structure with two humps includes: Depositing a stop layer on the semiconductor structure, which has a pattern for defining the two hills; and The semiconductor substrate is etched to create the structure with two hills. 6. According to the method in Clause 1, it further includes: An isolation oxide is deposited in the bump groove to form the isolation trench. 7. The method according to clause 6, wherein the isolation dielectric material includes silicon oxide, silicon nitride, or a combination thereof. 8. According to the method of clause 1, it further includes: During the subsequent epitaxial growth or subsequent material removal process, at least two sizes of dummy filling shapes are formed at suitable positions on the semiconductor substrate to achieve uniform process load in a wafer, wherein the One size of the dummy filling shape is exclusive to the transistor, and wherein the other size of the dummy filling shape is exclusive to the photodetector. 9. The method according to Clause 8, wherein the subsequent material removal process includes at least one of the following: a chemical mechanical polishing process or a reactive ion etching process. 10. The method according to clause 1, wherein the photodetector is a silicon-based germanium photodetector, and wherein the transistor is a silicon-based metal oxide semiconductor field effect transistor ( MOSFET). 11. The method according to Clause 1, wherein the light detector is a vertical incidence type. 12. A device comprising: A semiconductor substrate including a first surface, a second surface, and a third surface; A semiconductor transistor formed in a second surface higher than the first surface; and A semiconductor photodetector is formed in a third surface higher than the first surface but lower than the second surface, wherein the first surface lower than both the second surface and the third surface will be at An isolation trench is formed between the semiconductor photodetector and the semiconductor transistor. 13. The device according to clause 12, wherein the final height of the semiconductor photodetector is lower than the bottom surface of the lowest metal interconnection layer of the semiconductor transistor. 14. The device according to clause 12, wherein the semiconductor light detector is formed in the semiconductor substrate in a different horizontal position than the semiconductor transistor. 15. The device according to clause 12, wherein the semiconductor photodetector and the semiconductor transistor are formed on two separate hills, one of which is used for the transistor and the other is used for The photodetector, and wherein, the mound groove between the two mounds forms an isolation trench. 16. The device according to Clause 15, wherein the isolation trench is filled with at least one or more of the following: an oxide-based dielectric material or a nitride-based dielectric material 17. The device according to clause 12, wherein the photodetector includes a PIN structure having: a highly doped p-type semiconductor region; a highly doped n-type semiconductor region; and an intrinsic photosensitive semiconductor The region is located between the p-type semiconductor regions and the n-type semiconductor regions. 18. The device according to clause 17, wherein the semiconductor material used in at least a part of the P-I-N structure is different from the semiconductor substrate material. 19. The device according to clause 17, wherein the intrinsically photosensitive semiconductor region comprises a semiconductor material stack comprising a substrate semiconductor material having a first dielectric constant and a photosensitive material having a second dielectric constant, the second dielectric The electrical constant is higher than the first dielectric constant. 20. The device according to clause 19, wherein the thickness ratio between the substrate semiconductor material and other semiconductor materials in the combined intrinsic photosensitive semiconductor region is greater than 1 to 5. 21. The device according to Clause 12, which further includes: A selected number of dummy filling shapes approximately the size of the transistor, wherein the dummy filling shapes having the size of the transistor are formed in the surface at the same height as the second surface. 22. The device according to Clause 12, which further includes: A selected number of dummy filling shapes approximately the size of the photodetector, wherein the dummy filling shapes having the size of the photodetector are formed in the surface at the same height as the third surface. 23. The device according to Clause 12, wherein the photodetector is a silicon-based germanium photodetector, and wherein the transistor is a silicon-based metal oxide semiconductor field effect transistor ( MOSFET). 24. The device according to clause 12, wherein the light detector includes a mirror structure to reduce the thickness of the light absorption area of the light detector.

(B) Transistor channel priority mode: 1. A method for manufacturing a photodetector and a transistor on the same substrate, the method includes: (1) During the FEOL manufacturing stage, the transistor is formed on a semiconductor substrate; (2) During the MOL manufacturing stage and before the photodetector is formed on the semiconductor substrate, a contact plug for the transistor is formed by using a refractory material; (3) forming the photodetector on the semiconductor substrate; and (4) Only during the BEOL manufacturing stage, the contact plug for the photodetector is formed. 2. The method according to Clause 1, wherein the contact plugs for the photodetector are formed by using non-refractory materials. 3. According to the method of clause 1, it further includes: During the BEOL manufacturing stage, additional contact plugs are formed on the contact plugs for the transistor, wherein the additional contact plugs for the transistor will (a) be electrically connected to The formed contact plugs for the transistor and (b) reach the same height as the contact plugs for the photodetector. 4. The method according to Clause 3, wherein a part of the additional contact plugs is configured as an interconnection line, which provides inter-device signal transmission for the transistor. 5. The method according to clause 1, wherein the forming of the contact plug for the photodetector includes: In the first step during the BEOL manufacturing stage, the first set of contact plugs for the photodetector is formed by using a first metal material; and In the subsequent steps during the BEOL manufacturing stage, a second set of contact plugs for the photodetector is formed by using a second metal material, Wherein, the first set of contact plugs and the second set of contact plugs are used for different doped regions of the photodetector. 6. According to the method in Clause 1, it further includes: Before the formation of the transistor, a structure is formed, the structure having a hill for the transistor and a hill for the photodetector; and Adjust the relative height between the hill for the photodetector and the hill for the transistor until the top surface of the hill for the photodetector is lower than the hill for the transistor Up to the top surface. 7. The method according to Clause 1, wherein the contact plugs for the transistor are the first metal that directly contacts the formed transistor, and wherein the contacts for the transistor are The plugs are formed in a plurality of columnar arrays or strip-shaped arrays. 8. The method according to Clause 1, where the MOL stage further includes: A dielectric layer is deposited, which is the first dielectric layer covering the transistor. 9. The method according to Clause 1, wherein the contact plugs for the transistor are formed completely under the bottom surface of the first interconnection layer of the transistor and are positioned so as to be at least one of and below Electrical coupling: the gate area of the transistor, the source area of the transistor, or the drain area of the transistor. 10. The method according to clause 9, wherein the first group of contact plugs of the contact plugs for the photodetector are formed completely in the first interconnection layer of the photodetector The bottom surface is below and positioned to be electrically coupled to the first doped region of the photodetector. 11. The method according to clause 10, wherein the second group of contact plugs of the contact plugs for the photodetector are formed at least partially at the bottom of the first interconnection layer of the transistor On the surface and positioned to be electrically coupled to a second doped region of the photodetector, the second doped region has a different polarity from the first doped region. 12. The method according to Clause 1, wherein the BEOL stage further includes: Several interconnection layers are sequentially formed on the layer formed in the MOL stage. 13. The method according to clause 1, wherein the forming of the contact plug for the photodetector includes: The contact plugs for the P and N regions of the photodetector are formed by using different BEOL metals during the BEOL phase. 14. The method according to clause 1, wherein the material used to form the contact plug for the transistor includes at least one of the following: tungsten, titanium, or titanium nitride. 15. The method according to clause 1, wherein the material used to form the contact plug for the photodetector includes an interconnection metal including at least one of the following: copper or aluminum. 16. A semiconductor device comprising: A semiconductor substrate; A transistor which is formed on the semiconductor substrate; A light detector, which is formed on the semiconductor substrate; The contact plugs for the transistor, wherein the contact plugs for the transistor have at least two parts formed by a separate semiconductor material forming process, and wherein the contact plugs for the transistor The sidewalls of the contact plugs contain physical alignment deviations, which confirm the process of forming the separate semiconductor materials; and The contact plugs for the photodetector, wherein the contact plugs for the photodetector are formed by a single semiconductor material forming process. 17. The device according to clause 16, wherein the top surface of the contact plugs for the photodetector is higher than the physical alignment deviation of the sidewalls of the contact plugs for the transistor. 18. The device according to clause 16, wherein the contact plugs for the transistor comprise refractory materials formed during the mid-line (MOL) manufacturing stage. 19. The device according to Clause 16, wherein the contact plugs for the photodetector are all made of non-refractory material in the metal interconnection layer formed during the back-of-line (BEOL) manufacturing stage. Manufactured without any refractory materials from the mid-line (MOL) manufacturing stage. 20. The device according to clause 16, wherein the transistor and the photodetector are formed at different heights on the semiconductor substrate. 21. The device according to clause 16, wherein, when measured from the semiconductor substrate, the photodetector is formed on the first surface of the semiconductor substrate closer to the second surface on which the transistor is formed . 22. The device according to clause 16, wherein a lower part of at least two parts of the contact plugs for the transistor is formed completely in the first interconnection layer of the transistor The bottom surface is under and positioned to be electrically coupled to and in direct physical contact with at least one of the following: the gate region of the transistor, the source region of the transistor, or the drain region of the transistor. 23. The device according to clause 22, wherein the first group of contact plugs of the contact plugs used for the photodetector are formed completely in the first interconnection layer of the photodetector The bottom surface is below and positioned to be electrically coupled to and in direct physical contact with the first doped region of the photodetector. 24. The device according to clause 23, wherein the second group of contact plugs of the contact plugs for the photodetector are formed at least partially at the bottom of the first interconnection layer of the transistor On the surface and positioned to be electrically coupled to and in direct physical contact with the second doped region of the photodetector, the second doped region has a different polarity from the first doped region. 25. The device according to Clause 16, wherein the contact plugs and different BEOL metal layers for the P and N regions of the photodetector are of different materials. 26. The device according to clause 16, wherein the contact plug for the transistor is made of a material including at least one of the following: tungsten, titanium, or titanium nitride. 27. The device according to clause 16, wherein the material used for the contact plug of the photodetector is made of a material including interconnection metals including at least one of the following: copper or aluminum. 28. The device according to clause 16, wherein the photodetector includes a PIN structure having: a highly doped p-type semiconductor region; a highly doped n-type semiconductor region; and an intrinsic photosensitive semiconductor Region, which is located between the p-type semiconductor regions and the n-type semiconductor regions, Wherein, the intrinsic photosensitive semiconductor region includes a semiconductor material stack, which includes a substrate semiconductor material with a first dielectric constant and a photosensitive material with a second dielectric constant, the second dielectric constant being higher than the first dielectric constant . 29. The device according to clause 28, wherein the thickness ratio between the semiconductor material of the substrate and the other semiconductor materials in the intrinsic photosensitive semiconductor region of the combination is greater than 1 to 5. 30. The device according to Clause 16, which further includes: Having a selected number of dummy filling shapes approximately the size of the transistor, wherein the dummy filling shapes having approximately the size of the transistor are formed at the same height as the transistor; and A selected number of dummy filling shapes approximately the size of the photodetector, wherein the dummy filling shapes approximately the size of the photodetector are formed at the same height as the photodetector. 31. The device according to clause 16, wherein the top surface of a light absorbing material of the photodetector is higher than the bottom surface of the lowest metal interconnection layer of the transistor. 32. The device according to Clause 16, wherein the light detector includes a light absorbing region having a physical structure with sidewall alignment deviation, the sidewall alignment deviation being formed by two or more separate materials The process is to grow a result of essentially the same material. 33. The device according to clause 16, wherein the photodetector includes a mirror structure to reduce the thickness of the light absorption area of the photodetector. 34. A semiconductor device, comprising: A semiconductor substrate; A transistor which is formed on the semiconductor substrate; A light detector formed on the semiconductor substrate; and The contact plug for the light detector, Wherein, at least a part of the contact plugs used for the photodetector are located at the same horizontal level as the first interconnection layer of the transistor.

(C) Multi-absorbing layer method: 1. A method of manufacturing a photodetector and a transistor on the same substrate. The method includes: (1) A semiconductor substrate is formed on the area where the photodetector is to be formed. The first layer of light absorbing material of the photodetector is crystal grown; (2) after the first layer of light absorbing material is grown, at least one metal contact plug for the transistor is formed; and (3) in the forming After at least one layer of metal contacts the plug, a second layer of light absorbing material of the photodetector is formed, wherein the second layer of light absorbing material is formed on the top of the first layer of light absorbing material so as to have substantially the same material The two layers of light-absorbing material will form a single light-absorbing area of the photodetector. 2. The method according to clause 1, wherein the epitaxial growth of the first layer of light absorbing material is performed at a temperature suitable for epitaxial growth of the light absorbing material of the photodetector on a heterogeneous surface. 3. The method according to clause 1, wherein the forming the second layer of light-absorbing material is performed at a temperature suitable for epitaxial growth of the light-absorbing material of the photodetector on a homogeneous surface. 4. The method according to clause 1, wherein the forming of the second layer of light absorbing material is performed at a temperature lower than the temperature at which the epitaxial growth of the first layer of light absorbing material. 5. The method according to clause 1, wherein the forming of the second layer of light absorbing material is performed at a temperature lower than the temperature resistance of the formed metal contact plug for the transistor. 6. The method according to Clause 1, wherein the epitaxial growth of the first layer of light absorbing material is performed at a temperature higher than the withstand temperature of the formed metal contact plug for the transistor. 7. The method according to clause 1, wherein the epitaxial growth of the first layer of light absorbing material includes: performing surface cleaning at a temperature higher than the temperature resistance of the formed metal contact plug for the transistor Process. 8. The method according to clause 1, wherein the top surface of the second layer of light absorbing material is higher than the bottom surface of the lowest metal interconnection layer of the transistor. 9. The method according to clause 1, wherein the forming the second layer of light absorbing material includes: removing material deposited on the photodetector by a previous process to expose the first layer of light absorbing material. 10. The method according to clause 9, wherein the forming the second layer of light absorbing material further comprises: epitaxially growing the second layer of light absorbing material on the top of the first layer of light absorbing material, at least until the single light The height of the absorption region is higher than the at least one metal contact plug for the transistor. 11. The method according to clause 1, wherein the first layer of light absorbing material and the second layer of light absorbing material are formed by using separate lithography processes. 12. The method according to Clause 11, wherein the separate lithography processes leave a sidewall alignment deviation on the structure constituting the single light-absorbing region. 13. The method according to clause 1, further comprising: before forming the second layer of light absorbing material in an opening, first forming a passivation spacer on a sidewall of the opening to passivate the second layer of light Absorbing material in order to reduce the dark current of the device. 14. The method according to clause 1, further comprising: growing a passivation layer with a substrate material on the first layer or the second layer of light-absorbing material; and etching the passivation layer directionally for the purpose of A passivation separator is formed on the first layer or the second layer of light absorbing material. 15. A device comprising: a semiconductor substrate; a semiconductor transistor formed on the semiconductor substrate; and a semiconductor photodetector formed on the semiconductor substrate; wherein the semiconductor photodetector The top surface of a light absorbing material of the device is higher than the bottom surface of the lowest metal interconnection layer of the semiconductor transistor. 16. The device according to clause 15, further comprising: a passivation spacer on the first or second layer of light absorbing material. 17. The device according to clause 15, further comprising a passivation spacer on a side wall of the semiconductor photodetector, wherein the passivation spacer reduces the dark current of the device. 18. The device according to Clause 15, further comprising: contact plugs for the transistor, wherein the contact plugs for the transistor are produced during the mid-line (MOL) manufacturing stage Made of the formed refractory material; and contact plugs for the photodetector, wherein the contact plugs for the photodetector are all made during the post-production (BEOL) manufacturing stage The formed metal interconnection layer is made of non-refractory material without any refractory material from the MOL manufacturing stage. 19. The device according to clause 15, wherein the photodetector includes a PIN structure having: a highly doped p-type semiconductor region; a highly doped n-type semiconductor region; and an intrinsic photosensitive semiconductor A region, which is located between the p-type semiconductor regions and the n-type semiconductor region, wherein the intrinsically photosensitive semiconductor region includes a semiconductor material stack, which includes a substrate semiconductor material having a first dielectric constant and a second dielectric constant The photosensitive material, the second dielectric constant is higher than the first dielectric constant. 20. The device according to clause 19, wherein the thickness ratio between the substrate semiconductor material and other semiconductor materials in the combined intrinsic photosensitive semiconductor region is greater than 1 to 5. 21. The device according to clause 15, further comprising: a selected number of dummy filling shapes having approximately the size of the transistor, wherein the dummy filling shapes having approximately the size of the transistor are formed between and At the same height as the transistor; and a selected number of dummy filling shapes approximately the size of the photodetector, wherein the dummy filling shapes having approximately the size of the photodetector are formed at the same height as the photodetector At the same height as the detector. 22. The device according to clause 15, wherein the light detector includes a mirror structure to reduce the thickness of the light absorbing area. 23. A device comprising: a semiconductor substrate; a semiconductor transistor formed on the semiconductor substrate; and a semiconductor photodetector formed on the semiconductor substrate, wherein the semiconductor photodetector The device includes a light-absorbing region with a physical structure with sidewall alignment deviations, which proves to grow a substantially identical material by two or more separate material forming processes. 24. The device according to clause 23, wherein at least one set of metal contact plugs for the transistor or the photodetector is formed between the two or more separate material forming processes. 25. The device according to clause 24, wherein at least one of the two or more separate material forming processes is performed during or after the mid-line (MOL) manufacturing stage. 26. The device according to clause 23, wherein the substantially same material is a light absorbing material used in the light absorbing region of the semiconductor light detector. 27. The device according to clause 23, wherein the substantially identical material comprises germanium. 28. The device according to Clause 23, further comprising: a passivation separator located on the light absorption region to reduce dark current of the device, wherein the passivation separator material includes amorphous Si, polycrystalline Si, nitrogen Compounds, high-k dielectrics, SiO ₂ , or any combination of them. 29. The device according to Clause 23, further comprising: contact plugs for the transistor, wherein the contact plugs for the transistor are produced during the mid-line (MOL) manufacturing stage Formed of refractory material; and contact plugs for the photodetector, wherein the contact plugs for the photodetector are all made during the post-production line (BEOL) manufacturing stage The formed metal interconnection layer is made of non-refractory materials without any refractory materials from the MOL manufacturing stage. 30. The device according to clause 23, wherein the photodetector comprises a PIN structure having: a highly doped p-type semiconductor region; a highly doped n-type semiconductor region; and an intrinsic photosensitive semiconductor A region located between the p-type semiconductor regions and the n-type semiconductor region, wherein the intrinsically photosensitive semiconductor region includes a semiconductor material stack, which includes a substrate semiconductor material having a first dielectric constant and a second dielectric constant The photosensitive material, the second dielectric constant is higher than the first dielectric constant. 31. The device according to Clause 30, wherein the thickness ratio between the substrate semiconductor material and other semiconductor materials in the intrinsic photosensitive semiconductor region of the combination is greater than 1 to 5. 32. The device according to clause 23, further comprising: a selected number of dummy filling shapes having approximately the size of the transistor, wherein the dummy filling shapes having approximately the size of the transistor are formed in and At the same height as the transistor; and a selected number of dummy filling shapes approximately the size of the photodetector, wherein the dummy filling shapes having approximately the size of the photodetector are formed at the same height as the photodetector At the same height as the detector. 33. The device according to clause 23, wherein the light detector includes a mirror structure to reduce the thickness of the light absorbing area.

100: Conventional monolithic integrated semiconductor structure 101: horizontal axis 102: substrate 104(1): Tumulus 104(2): Tumulus 108: Shallow trench isolation (STI) feature element 110: Light detector (PD) device 120: Complementary Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device 130: contact plug 132: area 200: Monolithic integrated semiconductor structure 201: Stop layer 202: substrate 203: isolation material 204(1): Tuqiu 204(2): Tuqiu 205: Oxide 207: Mid-line oxide 208: Shallow trench isolation (STI) feature element 209: light detector hard mask layer 210: Light detector (PD) device 211: Well Flat Area 212: Cushioning material 213: photosensitive material 214: The upper area of the photosensitive layer 215: passivation layer 216: photosensitive material ring 217: Passivation Separator 220: Transistor device 230: Transistor contact channel 231: open 240: Photodetector (PD) contact channel 250: Metal interconnection line at the back of the production line 291: Interlayer Dielectric 400: Monolithic integrated semiconductor structure 401: monolithic integrated semiconductor structure 402: Substrate 404(1): Tumulus 404 (2): Tumulus 405: Dielectric material 407: Dielectric 408: Shallow trench isolation (STI) feature element 409: Dielectric materials 410: Photodetector (PD) device 411: bottom doped layer 412: Cushioning material 413: photosensitive material 414: Top doped area 415: passivation layer 416: photosensitive material ring 417: Passivation Separator 420: Transistor Device 430: Contact channel 431: open 432: Metal layer 440: Contact channel 441: contact channel 442: contact channel 491: Interlayer Dielectric 493: Dielectric layer 600: Monolithic integrated semiconductor structure 601a: Monolithic integrated semiconductor structure 601b: Monolithic integrated semiconductor structure 602: Substrate 603: isolation material 604(1): Tuqiu 604(2): Tuqiu 605: Dielectric material 607: Dielectric 608: Shallow trench isolation (STI) feature element 609: Hard Mask Layer 610: Light detector (PD) device 611: bottom doped layer 613(1): photosensitive material layer 613(2): photosensitive material layer 614: top doped layer 615: Top passivation layer 617: Passivation Separator 620: Transistor Device 630: Contact channel 640: bottom metal contact 641: Top metal contact 650: Metal interconnection line 660: Metal interconnection line 691: Dielectric deposits 693: Dielectric layer 810: Light detector fill shape 820: Transistor fill shape 960: small facet

One or more embodiments of the present disclosure will be illustrated in the drawings of the drawings through examples without limiting meaning, in which the same component symbols represent the same components. These drawings are not necessarily drawn to scale. 1 is a cross-sectional view of a conventional monolithic integrated semiconductor structure, which has a vertically incident photodetector (PD) and a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) field effect Transistor (Field Effect Transistor, FET). FIG. 2 shows a cross-sectional view of a monolithic integrated semiconductor structure incorporating one or more aspects of the disclosed technology of the present invention. 3A to 3R show cross-sectional views of various process steps for manufacturing the semiconductor structure of FIG. 2 according to some embodiments. FIG. 4A shows a cross-sectional view of another monolithic integrated semiconductor structure incorporating one or more aspects of the disclosed technology of the present invention. FIG. 4B shows a cross-sectional view of a monolithic integrated semiconductor structure as a variation of the structure shown in FIG. 4A. 5A to 5Q show cross-sectional views of various process steps for manufacturing the semiconductor structure of FIG. 4A according to some embodiments. FIG. 6A shows a cross-sectional view of another monolithic integrated semiconductor structure incorporating one or more aspects of the disclosed technology of the present invention. 6B to 6C show cross-sectional views of a monolithic integrated semiconductor structure as a modification of the structure shown in FIG. 6A. 7A to 7J show cross-sectional views of various process steps for manufacturing the semiconductor structure of FIG. 6A according to some embodiments. 8A to 8B show a top view and a cross-sectional view of a monolithic integrated semiconductor structure, which includes filling shapes of different sizes for PDs and transistors. 9A and 9B show cross-sectional views of an additional photodetector configuration method that can apply one or more aspects of the monolithic integration technology introduced herein.

600: Monolithic integrated semiconductor structure

602: Substrate

604(1): Tuqiu

604(2): Tuqiu

608: Shallow trench isolation (STI) feature element

610: Light detector (PD) device

613(1): photosensitive material layer

613(2): photosensitive material layer

620: Transistor Device

Claims (10)

A semiconductor device includes: a semiconductor substrate including a first surface, a second surface, and a third surface, wherein the first surface is located between the second surface and the third surface; a semiconductor transistor , Partly located on the second surface higher than the first surface; a semiconductor photodetector partly located on the third surface higher than the first surface but lower than the second surface; and an isolation trench , Which is located between the first surface, the semiconductor photodetector and the semiconductor transistor; wherein, a top of the semiconductor photodetector is lower than that of a lowest metal interconnection layer for connecting the semiconductor transistor A bottom surface. The semiconductor device according to claim 1, further comprising a first plug connected to the semiconductor transistor, and a second plug connected to the semiconductor photodetector, wherein the height of the first plug is equal to The height of the second plug is different. The semiconductor device according to claim 1, further comprising a transistor contact channel located between the semiconductor transistor and the bottom surface of the lowest metal interconnection layer. The semiconductor device according to claim 1, wherein the semiconductor substrate includes two separate hills, the semiconductor photodetector and the semiconductor transistor are respectively located on the two separate hills, and the isolation trench is located Between the two tutu. The semiconductor device according to claim 1, wherein the isolation trench is filled with at least one or more of the following: an oxide-based dielectric material or a nitride-based dielectric material. The semiconductor device according to claim 1, wherein the photodetector includes a bottom doped layer, a top doped layer, and an intrinsic photosensitive region between the bottom doped layer and the top doped layer, The bottom doped layer is located in the semiconductor substrate. The semiconductor device according to claim 6, wherein the material of the essential photosensitive region is different from the material of the semiconductor substrate. The semiconductor device according to claim 7, wherein the thickness ratio of the bottom doped layer to the intrinsic photosensitive region is greater than 1/5. The semiconductor device according to claim 6, 7 or 8, wherein the thickness of the bottom doped layer is greater than 100 nanometers. The semiconductor device according to claim 1, wherein the photodetector further comprises a photosensitive region and a passivation layer on the photosensitive region, the material of the photosensitive region is different from the material of the semiconductor substrate, and the passivation layer comprises Amorphous Si, polycrystalline Si, nitride, silicon dioxide, or combinations thereof.

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