TWI688059B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure including a circuit substrate, a first chip, a second chip, an encapsulant, a plurality of conductive connectors, and an image sensing package is provided. The first chip is disposed on the circuit substrate and electrically connected to the circuit substrate. The second chip is stacked on the first chip and electrically connected to the circuit substrate or the first chip. The encapsulant encapsulates the first chip and the second chip. The conductive connectors penetrate the encapsulant and are electrically connected to the circuit substrate. The image sensing package is disposed on the encapsulant and electrically connected to the conductive connectors. A manufacturing method of a semiconductor package is also provided.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a semiconductor packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure with a high-density packaging and a manufacturing method thereof.

In order to enable electronic products to achieve light, thin, and short designs, semiconductor packaging technology has also evolved to develop products that meet the requirements of small size, light weight, high density, and high competitiveness in the market.

The invention provides a semiconductor packaging structure and a manufacturing method thereof, which has a high density packaging (HDP) structure.

The invention provides a semiconductor packaging structure, which includes a circuit substrate, a first chip, a second chip, a sealing body, a plurality of conductive connectors and an image sensing package. The first chip is disposed on the circuit substrate and electrically connected to the circuit substrate. The second wafer is stacked on the first wafer and electrically connected to the circuit substrate or the first wafer. The sealing body encapsulates the first wafer and the second wafer. The conductive connector penetrates the sealing body and is electrically connected to the circuit board. The image sensing package is disposed on the sealing body and electrically connected to the conductive connector.

The present invention provides a method for manufacturing a semiconductor package structure, which includes the following steps. Provide circuit board. The first chip is arranged on the circuit substrate. The second wafer is arranged on the first wafer. A sealing body is formed to encapsulate the first wafer and the second wafer. A plurality of conductive connectors are formed to penetrate the sealing body. The image sensing package is arranged on the sealing body.

Based on the above, the semiconductor package structure may be a structure with high-density packaging.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only as a reference to the drawing and are not intended to imply absolute orientation.

Unless expressly stated otherwise, any method described herein is by no means intended to be interpreted as requiring that its steps be performed in a particular order.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1I are schematic cross-sectional views of a method for manufacturing a semiconductor package structure according to a first embodiment of the invention.

Referring to FIG. 1A, a circuit substrate 110 is provided. The circuit substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. The circuit substrate 110 may have a conductive pattern 112, and the electronic components on the first surface 110a and the electronic components on the second surface 110b may be electrically connected.

In this embodiment, the circuit substrate 110 may be a printed circuit board, but the invention is not limited thereto. As long as the circuit substrate 110 can carry the components formed thereon and can withstand subsequent processes.

Please refer to FIG. 1B, the first chip 120 is disposed on the first surface 110 a of the circuit substrate 110.

In this embodiment, the first wafer 120 is disposed on the first surface 110a of the circuit substrate 110 such that the back surface 120b faces the first surface 110a of the circuit substrate 110. In some embodiments, an adhesive layer 161 may be provided between the back surface 120b of the first wafer 120 and the first surface 110a of the circuit substrate 110, so that the first wafer 120 may be attached to the circuit substrate 110. The adhesive layer 161 may include, for example, a die attach film (DAF), but the invention is not limited thereto.

In this embodiment, the first active surface 120a of the first wafer 120 may have a redistribution circuit structure 185, but the invention is not limited thereto. The redistribution circuit structure 185 may be formed in a process of the first chip 120 by a process similar to chip scale package-like (CSP-like) including a plurality of chips (such as: the first chip 120 ) Wafer active surface of wafer. After that, the aforementioned wafer is diced to form a plurality of first wafers 120 with redistribution circuit structures 185.

The redistribution circuit structure 185 does not belong to the IC foundry process in the previous stage, but is a redistribution circuit structure formed in an external source assembly and test (OSAT) factory that does not belong to the original integrated circuit manufacturer. Therefore, design changes can be made according to subsequent packaging and testing requirements. That is to say, the redistribution circuit structure 185 may not be a part of the first wafer 120 in the initial layout design. In other words, in terms of structure, the redistribution circuit structure 185 may not be a circuit formed in a back-end of line (BEOL) of the first wafer 120. Therefore, the circuit of the redistribution circuit structure 185 can be adjusted or designed according to the requirements of the subsequent electrical connection, so that the first chip 120 can have more flexibility in application. In addition, the redistribution circuit structure 185 may include at least one conductive layer and at least one insulating layer formed by a general semiconductor manufacturing process. In other words, the thickness of the redistribution circuit structure 185 may be thinner than that of an interposer, circuit board, or other similar plate-like structures.

In this embodiment, the redistribution circuit structure 185 may cover a portion of the first active surface 120a of the first wafer 120 (eg, the first portion 120a1 of the first active surface 120a), but the invention is not limited thereto. For example, the first active surface 120a of the first chip 120 includes a first portion 120a1 and a second portion 120a2. The first portion 120a1 overlaps the redistribution circuit structure 185 and the second portion 120a2 does not overlap the redistribution circuit structure 185. In an embodiment, the second portion 120a2 that does not overlap the redistribution circuit structure 185 may be used for electrical connection in other ways.

In some embodiments, the first chip 120 may be a power management integrated circuit (PMIC), a micro-electro-mechanical system (MEMS), or an application-specific integrated circuit chip (Application-specific) integrated circuit (ASIC), dynamic random access memory chip (dynamic random access memory, DRAM), static random access memory chip (static random access memory, SRAM), system on chip (SoC) or other similar High Performance Computing (HPC) chip.

1C, a plurality of leads 171 are formed to electrically connect the first chip 120 to the circuit substrate 110. The material of the lead 171 may include gold, copper, aluminum, or other suitable conductive materials. The connection ends of the lead 171 and the first chip 120 (such as aluminum pads or other suitable pads; not directly shown) may be located on the second portion 120a2 of the first active surface 120a. In this way, it is possible to reduce the damage that may be caused to the redistribution circuit structure 185 during the formation of the wire 171 by wire bonding.

Please refer to FIG. 1D, the second wafer 130 is disposed on the first wafer 120. The second wafer 130 is stacked on the first wafer 120 and electrically connected to the first wafer 120 or the circuit substrate 110. The second chip 130 is, for example, a logic chip. In some embodiments, the first wafer 120 may be used to execute logic applications of the second wafer 130, however, the invention is not limited thereto. Other suitable active devices can be used as the first chip 120 and the second chip 130.

In this embodiment, the second wafer 130 is disposed on the first active surface 120a of the first wafer 120 in such a manner that the second active surface 130a faces the first active surface 120a of the first wafer 120. In some embodiments, the second wafer 130 is disposed on the first active surface 120 a of the first wafer 120 by flip-chip bonding, for example, so that the second wafer 130 is electrically connected to the first wafer 120 . For example, the second chip 130 is electrically connected to the first chip 120 through the pad 132, the conductive bump 124 and the redistribution circuit structure 185.

In this embodiment, since the first active surface 120a of the first wafer 120 and the second active surface 130a of the second wafer 130 face to face each other, the first wafer 120 and the second wafer 130 can be made The signal path is shorter, and the communication speed and transmission quality between the first chip 120 and the second chip 130 can be improved. Moreover, since the first wafer 120 and the second wafer 130 have a redistribution circuit structure 185. Therefore, the signal path between the first chip 120 and the second chip 130 can be adjusted or optimized by rerouting the circuit design of the circuit structure 185. For example, the signal time-delay between the first chip 120 and the second chip 130 can be adjusted by redistributing the circuit structure 185 without being limited to the first chip 120 and/or the first The initial circuit design of the second chip 130 makes the first chip 120 and/or the second chip 130 more flexible in application. In addition, the layout design of the wiring structure 185 can be re-distributed to provide a suitable flip chip bonding pitch between the first chip 120 and the second chip 130, and the first chip 120 also The lead 171 can be electrically connected to the circuit substrate 110 without using the redistribution circuit structure 185.

1E, a sealing body 140 is formed on the first surface 110a of the circuit substrate 110 to encapsulate the first wafer 120 and the second wafer 130. The material of the sealing body 140 may include epoxy resin, molding compound or other suitable insulating materials. The sealing body 140 may be formed by compression molding, transfer molding, or other suitable sealing processes.

1F, a plurality of through holes 142 are formed in the sealing body 140. The through hole 142 penetrates the sealing body 140. The through hole 142 may be formed by a drilling process. For example, the through hole 142 can be formed in the sealing body 140 by laser drilling, mechanical drilling or etching according to the material of the sealing body 140.

1G, a plurality of through holes 142 (shown in FIG. 1F) is filled with a conductive material to form a plurality of conductive connectors 150. The conductive connector 150 penetrates the sealing body 140 and is electrically connected to the circuit substrate 110. The conductive connecting member 150 may be composed of copper, aluminum, nickel, gold, silver, tin, a combination of the above, a copper/nickel/gold composite structure, or other suitable conductive materials. The conductive connection 150 may be formed by sputtering, evaporation, electro-less plating or electroplating.

In this embodiment, the conductive connecting member 150 may be formed by filling a conductive material in the through hole 142. In other words, the conductive connecting member 150 may be formed by a technique of through molding via (TMV).

In this embodiment, the conductive material used to fill the through hole 142 may further cover the outer surface 140 a of the sealing body 140 to form the conductive terminal 152. The conductive connector 150 is electrically connected to other electronic components through corresponding conductive terminals 152.

In some feasible embodiments, the conductive connector 150 and the conductive terminal 152 may be formed by different steps. For example, the conductive terminal 152 may be a solder ball formed by a ball placement process and/or a reflow process, but the present invention is not limited thereto.

1H, a plurality of solder balls 154 may be formed on the second surface 110b of the circuit substrate 110. For example, the structure shown in FIG. 1I can be flipped upside down. Afterwards, a solder ball 154 electrically connected to the circuit substrate 110 may be formed on the second surface 110b of the circuit substrate 110 through a ball placement process and/or a reflow process. However, the present invention does not limit the formation order of the solder balls 154, which can be determined according to the requirements of the manufacturing process.

Referring to FIG. 1I, after the step of forming a plurality of conductive connectors 150, the image sensing package 190 is disposed on the first surface 110a of the circuit substrate 110. The image sensing package 190 is electrically connected to the circuit substrate 110.

In this embodiment, the image sensing package 190 may be disposed on the intermediate board 180, and the image sensing package 190 and the conductive connection member 150 on opposite sides of the intermediate board 180 may be electrically connected to each other through the intermediate board 180. Sexual connection.

In this embodiment, since the image sensing package 190 is formed after the step of forming the plurality of conductive connectors 150, the support capability when the image sensing package 190 is formed can be enhanced. However, the present invention does not limit the formation order of the image sensing package 190, which can be determined according to the requirements of the manufacturing process.

After the above process, the fabrication of the semiconductor package structure 100 of this embodiment can be completed. The semiconductor package structure 100 includes a circuit substrate 110, a first chip 120, a second chip 130, a sealing body 140, a plurality of conductive connectors 150, and an image sensing package 190. The first chip 120 is disposed on the circuit substrate 110 and electrically connected to the circuit substrate 110. The second wafer 130 is stacked on the first wafer 120 and electrically connected to the circuit substrate 110 or the first wafer 120. The sealing body 140 encapsulates the first chip 120 and the second chip 130. The conductive connector 150 penetrates the sealing body 140 and is electrically connected to the circuit substrate 110. The image sensing package 190 is disposed on the sealing body 140 and electrically connected to the conductive connector 150.

In the semiconductor package structure 100, the first chip 120 and the second chip 130 are arranged on the first surface 110a of the circuit substrate 110, and the image sensing package 190 is arranged on the outer surface 140a of the sealing body 140 to make the semiconductor package structure 100 may be a structure with a high-density package. Furthermore, the first chip 120 and the second chip 130 can be used to process the electronic signals of the image sensing package 190, and the first active surface 120a of the first chip 120 and the second active surface 130a of the second chip 130 can be Since they are arranged in a face-to-face manner, the signal path between the first chip 120 and the second chip 130 is shortened to improve the communication between the first chip 120 and the second chip 130 The speed and transmission quality can also shorten the signal transmission distance between the image sensing package 190, the first chip 120, and/or the second chip 130, thereby improving the electrical capability and/or performance of the semiconductor package structure 100.

In some embodiments, the image sensing package 190 includes a wafer 192 having a base 192a and a photosensitive portion 192b, a blocking structure 194, and a filter layer 196. The substrate 192a may include a plurality of electronic components (not shown), which may be formed on the substrate 192a or embedded in the substrate 192a. The electronic component may be a charge-coupled device (Charge-coupled Device, CCD), a complementary metal oxide semiconductor (CMOS) transistor, a photodiode, or a combination thereof. For example, in the case where the electronic component is a CMOS transistor, the chip 192 can be regarded as a CMOS image sensor chip. The blocking structure 194 surrounds the photosensitive portion 192b, and the blocking structure 194 exposes the photosensitive portion 192b. The material of the barrier structure 194 may be epoxy resin, polymethyl methacrylate, silicone resin, silicone, polyimide, benzocyclobutene (BCB), or a combination thereof. The filter layer 196 is attached to the blocking structure 194 to cover the corresponding blocking structure 194 and the photosensitive portion 192b, so that a closed space is formed between the filter layer 196, the blocking structure 194 and the wafer 192. The filter layer 196 may be an IR cut filter (IRCF), which can block light with a wavelength greater than 700 nm (such as infrared), and only allow light with a wavelength of less than 700 nm (such as blue light) to pass through the filter layer 196, suitable for image capture under general light, such as photography or video recording.

In this embodiment, the image sensing package 190, the first chip 120 and the second chip 130 are projected on the circuit substrate 110 and overlap each other. For example, the projection of the first chip 120 on the circuit substrate 110 partially overlaps the projection of the image sensing package 190 on the circuit substrate 110. The projection of the second chip 130 on the circuit substrate 110 partially overlaps with the projection of the first chip 120 on the circuit substrate 110. The projection of the second chip 130 on the circuit substrate 110 partially overlaps the projection of the image sensing package 190 on the circuit substrate 110. In other words, the projection of the image sensing package 190 on the circuit substrate 110 overlaps the projection of the first chip 120 and the second chip 130 on the circuit substrate 110. Since the image sensing package 190, the first chip 120 and the second chip 130 are projected on the circuit substrate 110 to overlap each other, that is to say, the image sensing package 190, the first chip 120 and the second chip 130 are located in the same vertical area Therefore, the size of the semiconductor package structure 100 can be reduced.

In this embodiment, the semiconductor package structure 100 further includes at least one passive element 198 disposed on the interposer 180. Moreover, the passive element 198 may be electrically connected to the image sensing package 190 and/or the conductive connection 150 through the interposer 180. The passive element 198 is, for example, a resistor, an inductor, or a multilayer ceramic capacitor (Multi-Layer Ceramic Capacitor, MLCC). Therefore, the element density of the semiconductor package structure 100 can be further improved.

2 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the invention. In this embodiment, the semiconductor package structure 200 is similar to the semiconductor package structure 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions are omitted.

In this embodiment, the first wafer 120 is disposed on the first surface 110a of the circuit substrate 110 in such a manner that the first active surface 120a faces the first surface 110a of the circuit substrate 110. In some embodiments, the first chip 120 is disposed on the first surface 110 a of the circuit substrate 110 by flip-chip bonding, for example, so that the first chip 120 is electrically connected to the circuit substrate 110. For example, the first chip 120 is electrically connected to the circuit substrate 110 through pads (not shown) and conductive bumps (not shown).

In this embodiment, the second wafer 130 may be stacked on the first wafer 120 in such a manner that the back surface 130b faces the back surface 120b of the first wafer 120. In some embodiments, there may be an adhesive layer 262 between the back surface 120 b of the first wafer 120 and the back surface 130 b of the second wafer 130, so that the second wafer 130 can be attached to the first wafer 120. The adhesive layer 262 may include, for example, a wafer adhesive film, but the invention is not limited thereto.

In this embodiment, the second chip 130 can electrically connect the second chip 130 to the circuit substrate 110 through a plurality of leads 272. The material of the lead 272 may include gold, copper, aluminum, or other suitable conductive materials.

Generally speaking, high-performance computing chips often generate a lot of heat during operation. Therefore, in this embodiment, since the first active surface 120a of the first chip 120 faces the first surface 110a of the circuit substrate 110, heat can be dissipated by the circuit substrate 110 to improve the heat dissipation efficiency of the first chip 120 during operation , And the reliability and performance of the first chip 120 can be improved.

3 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention. In this embodiment, the semiconductor package structure 300 is similar to the semiconductor package structure 200 of the second embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions are omitted.

In this embodiment, the circuit substrate 310 is similar to the circuit substrate 110 of the previous embodiment, but the circuit substrate 310 may further have an opening 310c penetrating the first surface 310a and the second surface 310b. In addition, the first chip 120 can electrically connect the first active surface 120a of the first chip 120 and the second surface 310b of the circuit substrate 310 through a plurality of leads 371 passing through the opening 310c. The material of the lead 371 may include gold, copper, aluminum, or other suitable conductive materials.

In this embodiment, the semiconductor package structure 300 may further include a protective layer 345. The protective layer 345 may fill the opening 310c of the circuit substrate 310 and cover the first active surface 120a of the first wafer 120, the second surface 310b of the circuit substrate 310, and a plurality of leads 371 passing through the opening 310c. The material of the protective layer 345 may be the same as or similar to the material of the sealing body 140, but the invention is not limited thereto.

4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the invention. In this embodiment, the semiconductor package structure 400 is similar to the semiconductor package structure 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and descriptions are omitted.

In this embodiment, after forming a plurality of leads 471 electrically connected to the first active surface 420a of the first wafer 420 and the circuit substrate 110, a sealing body encapsulating the plurality of leads 471 and the first wafer 420 may be formed 441. Next, a second wafer 430 stacked on the first wafer 420 is disposed on the sealing body 441, and the second active surface 430a of the second wafer 430 can be electrically connected to the circuit substrate 110 through a plurality of leads 472. Thereafter, a sealing body 442 is formed to encapsulate the second wafer 430, the plurality of leads 472, and the sealing body 441 that encapsulates the first wafer 420 and the plurality of leads 471. The material or forming method of the sealing body 441 and/or the sealing body 442 may be similar to the material or forming method of the sealing body 140 described above, and therefore will not be described here.

In this embodiment, the first chip 420 is, for example, a logic chip. The second chip 430 may be a power management chip, a microelectromechanical system chip, a special application integrated circuit chip, a dynamic random access memory chip, a static random access memory chip, a system chip, or other similar high-performance computing chips. In some embodiments, the second wafer 430 may be used to execute the logic application of the first wafer 420, however, the invention is not limited thereto.

In summary, the semiconductor package structure of the present invention can be a structure with a high-density package.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 200, 300, 400: semiconductor packaging structure 110, 310: circuit board 110a, 310a: first surface 110b, 310b: second surface 310c: opening 112: conductive pattern 120, 420: the first chip 120a, 420a: the first active surface 120a1: Part One 120a2: Part Two 120b: back 124: conductive bump 130, 430: second chip 130a, 430a: second active surface 130b: back 132: Pad 140, 345, 441, 442: sealing body 140a: outer surface 142: through hole 150: conductive connector 152: conductive terminal 154: solder ball 161, 262: Adhesive layer 171, 272, 371, 471, 472: leads 180: Intermediate board 185: Redistribution circuit structure 190: Image sensing package 192: Wafer 192a: base 192b: photosensitive section 194: blocking structure 196: Filter layer 198: Passive component

1A to 1I are schematic cross-sectional views of a method for manufacturing a semiconductor package structure according to a first embodiment of the invention. 2 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the invention. 3 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention. 4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the invention.

100: Semiconductor packaging structure

110: circuit board

110a: first surface

110b: Second surface

120: First chip

120a: the first active surface

130: second chip

130a: second active surface

140: Sealing body

140a: outer surface

150: conductive connector

152: conductive terminal

154: solder ball

171: Lead

180: Intermediate board

190: Image sensing package

192: Wafer

192a: base

192b: photosensitive section

194: blocking structure

196: Filter layer

198: Passive component

Claims (7)

A semiconductor package structure includes: a circuit substrate; a first chip, which is arranged on the circuit substrate and electrically connected to the circuit substrate; a second chip, which is stacked on the first wafer and is electrically connected to the circuit substrate Or the first wafer, and the first active surface of the first wafer faces the second wafer; the redistribution circuit structure is located between the first active surface of the first wafer and the second wafer Between the second active surface and electrically connected to the first chip and the second chip, wherein the redistribution circuit structure partially covers the first active surface of the first chip; a plurality of leads, The opposite ends of the plurality of leads are electrically connected to the circuit substrate and a portion of the first active surface that is not covered by the redistribution circuit structure; a sealing body encapsulates the first chip and the A second chip, the redistribution structure and the plurality of leads; a plurality of conductive connectors penetrating the sealing body and electrically connecting the circuit substrate; and an image sensing package arranged on the sealing body And electrically connect the plurality of conductive connectors. The semiconductor packaging structure as described in item 1 of the patent application scope further includes: a plurality of leads, wherein the first chip or the second chip The lead is electrically connected to the circuit substrate. The semiconductor package structure according to item 1 of the patent application scope, wherein the image sensing package, the first chip, and the second chip are projected on the circuit substrate to overlap each other. The semiconductor package structure as described in item 1 of the patent application range, wherein the first active surface of the first chip faces the circuit substrate. The semiconductor packaging structure as described in item 4 of the patent application scope further includes a plurality of leads, wherein: the circuit substrate has a first surface, a second surface opposite to the first surface, and the first surface and An opening of the second surface; the first chip is disposed on the first surface of the circuit substrate; the plurality of leads pass through the opening; the first chip at least passes through the plurality of The lead is electrically connected to the second surface of the circuit substrate. The semiconductor package structure as described in item 1 of the patent application scope further includes: an interposer disposed between the image sensing package and the sealing body, and the image sensing package passes through the intermediary The board is electrically connected to the plurality of conductive connectors; and at least one passive element is disposed on the intermediate board. A method for manufacturing a semiconductor packaging structure, including: providing a circuit substrate; Arranging a first wafer with a rewiring structure on the circuit substrate; arranging a second wafer on the first wafer, the first active surface of the first wafer facing the second wafer, the redistribution circuit Structure, located between the first active surface of the first wafer and the second active surface of the second wafer, and electrically connected to the first wafer and the second wafer, wherein the heavy The wiring structure partly covers the first active surface of the first wafer; a plurality of leads are formed, and opposite ends of the plurality of leads are electrically connected to the circuit substrate and not to the redistribution circuit, respectively The portion covered by the structure is the first active surface; a sealing body is formed to encapsulate the first wafer, the second wafer, the rewiring structure and the plurality of leads; a plurality of conductive connectors are formed through The sealing body; and disposing an image sensing package on the sealing body.

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