TWI688047B - Semiconductor device - Google Patents

Abstract

An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

Description

Semiconductor device

The present invention relates to a semiconductor device using semiconductor elements.

Semiconductor devices such as non-dependent storage devices that can repeatedly write and erase data are convenient and have a high resistance to physical shock. For example, non-dependent storage devices can be EEPROM and flash memory Body etc. Therefore, they are mainly used in portable storage media such as USB flash drives and memory cards, RF tags of radio frequency identification (RFID) media whose data is read wirelessly, and are widely available on the market. In a semiconductor device, a transistor as a storage element is included in each memory cell. In addition, the transistor includes an electrode called a floating gate located between the gate electrode and the semiconductor film as an active layer. The accumulation of charge in the floating gate can store data.

Patent documents 1 and 2 are thin film transistors including floating gates formed on a glass substrate.

[references]

[Patent Literature 1] Japanese Published Patent Application No. H6-021478

[Patent Literature 2] Japanese Published Patent Application No. 2005-322899

In the case of forming a circuit including a large number of signal lines as a driving circuit of a semiconductor device, it is preferable to increase the number of wiring layers and form signal lines in each layer in order to reduce the area of the driving circuit. However, simply increasing the number of wiring masks when increasing the number of wiring layers is not preferred because of the increase in cost.

In particular, a semiconductor device such as a storage device includes a memory cell and a driving circuit for driving the memory cell; therefore, the size of the semiconductor device is limited by the area of the driving circuit. That is, even when the area of only the memory cell is reduced, unless the area of the drive circuit is reduced, the semiconductor device cannot be miniaturized as a whole. Therefore, when miniaturizing the semiconductor device, it is important to reduce the area of the drive circuit.

In view of the above, an object of an embodiment of the present invention is to miniaturize a semiconductor device.

Another object of an embodiment of the present invention is to reduce the area of a driving circuit of a semiconductor device including a memory cell.

An embodiment of the present invention is a semiconductor device including an element forming layer provided with at least a first semiconductor element, a first wiring provided on the element forming layer, an interlayer film provided on the first wiring, and overlapping the first wiring And a second wiring with an interlayer film in between. The first wiring, the interlayer film, and the second wiring are included in the second semiconductor element. The first wiring and the second wiring are supplied Wiring with the same potential.

Another embodiment of the present invention is a semiconductor device including an element forming layer provided with at least a first semiconductor element, a first wiring provided on the element forming layer, an interlayer film provided on the first wiring, and a first The wiring overlaps with the second wiring interposed therebetween. The first wiring, the interlayer film, and the second wiring are included in the second semiconductor element. The first wiring and the second wiring are wirings for common mode signal input.

Another embodiment of the present invention is a semiconductor device, which includes a memory cell and a driving circuit portion of the memory cell. The memory cell includes: a first transistor including a first channel formation region, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second channel formation region and a second gate Electrode, second source electrode, and second drain electrode; and, a capacitor. The second transistor is arranged to overlap at least the first transistor. The driving circuit part is provided with a semiconductor element including a first wiring and a second wiring. The first wiring is formed by the same process as the second source electrode and the second drain electrode. The second wiring overlaps the first wiring with an interlayer film therebetween, and is formed by the same process as the second gate electrode. The first wiring and the second wiring are wirings supplied with the same potential.

Another embodiment of the present invention is a semiconductor device, which includes a memory cell and a driving circuit portion of the memory cell. The memory cell includes: a first transistor including a first channel formation region, a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second channel formation region and a second gate Electrode, second source electrode, and second drain electrode; and, a capacitor. The second transistor is arranged to overlap at least the first transistor. Drive circuit part A semiconductor element including a first wiring and a second wiring is provided. The first wiring is formed by the same process as the second source electrode and the second drain electrode. The second wiring overlaps the first wiring with an interlayer film therebetween, and is formed by the same process as the second gate electrode. The first wiring and the second wiring are wirings for common mode signal input.

In the above semiconductor device, the semiconductor element may be a level shifter. The thickness of the interlayer film is preferably greater than or equal to 10 nm and less than or equal to 100 nm.

In this specification and the like, in the description of the positional relationship between components, "above" or "below" does not necessarily mean "directly on" or "respectively" Directly under." For example, the description of "gate electrode on the gate insulating film" means that there is an increased number of elements between the gate insulating film and the gate electrode.

In addition, in this specification and the like, terms such as "electrode" or "wiring" do not limit the function of the element. For example, "electrodes" can be used as part of "wiring" in some cases, and vice versa. In addition, the words "electrode" or "wiring" include the case where plural "electrodes" or "wiring" are formed in an integrated manner.

For example, when transistors with different polarities are used or when the direction of current is changed during circuit operation, the functions of "source" and "drain" can sometimes replace each other. Therefore, in this specification, the words "source" and "drain" can be used to denote the drain and the source, respectively.

Note that in this specification and the like, the term "electrically connected" includes the case where a plurality of elements are connected via "an object having any electrical function". as long as It is possible to transmit and receive electrical signals between a plurality of components connected by an object. There is no particular limitation on "an object with any electrical function". Examples of "an object having any electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and elements and electrodes and wiring having various functions.

In this specification and the like, "same potential" includes "substantially the same potential". The technical concept of the present invention is to manufacture stacked plural conductor layers (first wiring and second wiring) with a thin insulating film interposed therebetween as wiring, and to reduce the parasitic capacitance in the circuit. Therefore, "same potential" includes "substantially the same potential", for example, compared with the case where the first potential (for example, VDD) is supplied to the first wiring, the parasitic capacitance is sufficiently reduced (to one percent or less) ) And the second potential (for example, GND) supplied from the power supply line different from the first potential to the second wiring. In addition, potential shifts due to wiring resistance and the like are reasonably acceptable. Similarly, the "common mode" potential includes the "substantially common mode" potential.

According to an embodiment of the present invention, a miniaturized semiconductor device is provided.

According to another embodiment of the present invention, a semiconductor device including a memory cell and a reduced-area driving circuit is provided.

100‧‧‧ circuit

101‧‧‧Transistor

102‧‧‧Transistor

120‧‧‧Semiconductor layer

122a‧‧‧Gate insulating film

124‧‧‧Mask

126‧‧‧ Impurity zone

128a‧‧‧Gate electrode

128b‧‧‧Conductor layer

130‧‧‧ Impurity zone

132‧‧‧ Impurity zone

134‧‧‧ Channel formation area

136‧‧‧Insulation

138‧‧‧Insulation

140‧‧‧Insulation

142a‧‧‧Source electrode

142b‧‧‧Drain electrode

144‧‧‧oxide semiconductor

146‧‧‧Gate insulating film

148a‧‧‧Gate electrode

148b‧‧‧Conductor layer

150‧‧‧Insulation

154‧‧‧Wiring

156‧‧‧Wiring

160‧‧‧Transistor

162‧‧‧Transistor

162A‧‧‧Transistor

162B‧‧‧Transistor

164‧‧‧Capacitor

200‧‧‧ circuit

201‧‧‧Transistor

202‧‧‧Transistor

203‧‧‧Region

300‧‧‧ base

301‧‧‧Element formation layer

302‧‧‧ First wiring

302a‧‧‧Wiring

302b‧‧‧Wiring

303‧‧‧Second wiring

303a‧‧‧Wiring

30b‧‧‧Wiring

304‧‧‧ Third wiring

305‧‧‧The first interlayer membrane

306‧‧‧Second interlayer membrane

400‧‧‧Semiconductor substrate

401‧‧‧Insulation

404a‧‧‧oxide conductor layer

404b‧‧‧oxide conductor layer

410‧‧‧Single crystal semiconductor substrate

412‧‧‧Oxide film

414‧‧‧Easy brittle area

416‧‧‧Single crystal semiconductor layer

437‧‧‧Insulation

450a‧‧‧First crystalline oxide semiconductor layer

450b‧‧‧Second crystalline oxide semiconductor layer

453‧‧‧Oxide semiconductor layer

500‧‧‧Column decoder

501‧‧‧Column driver

502‧‧‧Memory Cell

503‧‧‧The first gate

504‧‧‧Reverse gate part

505‧‧‧The first level shifter

506‧‧‧First buffer

507‧‧‧The second gate

508‧‧‧Second level shifter

509‧‧‧Second buffer

601‧‧‧Transistor

602‧‧‧Transistor

603‧‧‧Transistor

604‧‧‧Transistor

605‧‧‧Signal line

606‧‧‧Signal line

607‧‧‧Region

700‧‧‧Signal line

702‧‧‧Reverse gate

703a‧‧‧transistor

703b‧‧‧transistor

704‧‧‧Signal line

705‧‧‧Region

706‧‧‧ interlayer membrane

707‧‧‧Chassis

708‧‧‧Chassis

709‧‧‧Display

710‧‧‧ keyboard

711‧‧‧main body

712‧‧‧Probe

713‧‧‧Display

714‧‧‧Operation keys

715‧‧‧External interface

720‧‧‧E-book reader

721‧‧‧Chassis

723‧‧‧Chassis

725‧‧‧ Display

727‧‧‧Display

731‧‧‧Hinges

733‧‧‧Operation keys

735‧‧‧Speaker

737‧‧‧Hinges

740‧‧‧Chassis

741‧‧‧Chassis

742‧‧‧Display panel

743‧‧‧Speaker

744‧‧‧ microphone

745‧‧‧Operation keys

746‧‧‧Pointing device

747‧‧‧Camera lens

748‧‧‧External connection terminal

749‧‧‧Solar battery

750‧‧‧External memory slot

761‧‧‧Main

763‧‧‧Eyepiece

764‧‧‧Operation switch

765‧‧‧Display

766‧‧‧Battery

767‧‧‧Display

770‧‧‧TV

771‧‧‧Chassis

773‧‧‧ Display

775‧‧‧Bracket

780‧‧‧remote control

800‧‧‧Signal line

802‧‧‧Reverse gate

803a‧‧‧transistor

803b‧‧‧transistor

804‧‧‧Signal line

805‧‧‧Region

900‧‧‧Inverter

901‧‧‧Transistor

902‧‧‧Transistor

903‧‧‧Transistor

904‧‧‧Transistor

905‧‧‧transistor

906‧‧‧Transistor

910‧‧‧Input signal line

911‧‧‧Reverse signal input line

912‧‧‧Output signal line

913‧‧‧Reverse signal output line

1000‧‧‧Transistor

1001‧‧‧Wiring

1002‧‧‧Wiring

1003‧‧‧Region

1006‧‧‧ interlayer membrane

1100‧‧‧Transistor

1101‧‧‧Wiring

1102‧‧‧Wiring

1103‧‧‧Region

1201‧‧‧First transistor

1202‧‧‧second transistor

1203‧‧‧Capacitor

1300‧‧‧ storey

1301‧‧‧ First transistor

1302‧‧‧second transistor

1400‧‧‧Inverter

1401‧‧‧transistor

1402‧‧‧transistor

1403‧‧‧Transistor

1404‧‧‧Transistor

1405‧‧‧transistor

1406‧‧‧Transistor

1407‧‧‧Transistor

1408‧‧‧Transistor

1410‧‧‧Input signal cable

1411‧‧‧Reverse signal input line

1412‧‧‧Output signal cable

1413‧‧‧Reverse signal output line

1500‧‧‧Transistor

1501‧‧‧Wiring

1502‧‧‧Wiring

1503‧‧‧Region

1506‧‧‧ interlayer membrane

1600‧‧‧Signal line

1601‧‧‧ circuit

1602‧‧‧Buffer

1603‧‧‧ circuit

1604‧‧‧Signal line

1605‧‧‧Signal line

2101‧‧‧Base insulating film

2102‧‧‧Embedded insulator

2103a‧‧‧semiconductor area

2103b‧‧‧essential semiconductor area

2103c‧‧‧Semiconductor District

2104‧‧‧Gate insulating film

2105‧‧‧Gate electrode

2106a‧‧‧side wall insulator

2106b‧‧‧side wall insulator

2107‧‧‧Insulator

2108a‧‧‧Source electrode

2108b‧‧‧Drain electrode

3100‧‧‧Base

3102‧‧‧Base insulating film

3104‧‧‧Protection insulating film

3106‧‧‧Oxide semiconductor film

3106a‧‧‧High resistance area

3106b‧‧‧Low resistance zone

3108‧‧‧ Gate insulating film

3110‧‧‧Gate electrode

3112‧‧‧Side wall insulation film

3114‧‧‧electrode

3116‧‧‧Interlayer insulating film

3118‧‧‧Wiring

3600‧‧‧ base

3602‧‧‧Base insulating film

3606‧‧‧Oxide semiconductor film

3608‧‧‧Gate insulating film

3610‧‧‧Gate electrode

3614‧‧‧electrode

3616‧‧‧Gate insulating film

3618‧‧‧Wiring

3620‧‧‧Protection film

In the drawings, FIG. 1A is a cross-sectional view of a semiconductor device, and FIG. 1B is a circuit diagram thereof; FIG. 2 is a circuit diagram of the semiconductor device; FIG. 3 is a circuit diagram of the semiconductor device; FIG. 4 is a cross-sectional view of the semiconductor device; 6 is a circuit diagram of a semiconductor device; FIG. 7 is a cross-sectional view of the semiconductor device; FIG. 8 is a plan view of the semiconductor device; FIG. 9 is a circuit diagram of the semiconductor device; FIG. 10 is a cross-sectional view of the semiconductor device; FIG. 12 is a circuit diagram of the semiconductor device; FIG. 13 is a cross-sectional view of the semiconductor device; FIG. 14 is a circuit diagram of the semiconductor device; FIG. 15A is a cross-sectional view of the semiconductor device, and FIG. 15B is a plan view thereof; 16G is a sectional view showing the manufacturing steps of the semiconductor device; FIGS. 17A to 17E are sectional views showing the manufacturing steps of the semiconductor device; FIGS. 18A to 18D are sectional views showing the manufacturing steps of the semiconductor device; FIGS. 19A to 19D are sectional views, FIGS. 20A to 20C are cross-sectional views showing the manufacturing steps of the semiconductor device; FIGS. 21A to 21F are embodiments of the electronic device; FIGS. 22A and 22B are cross-sectional views of the semiconductor device; FIGS. 23A to 23C are cross-sections A view showing the manufacturing steps of the semiconductor device; FIGS. 24A to 24E all show the structure of an oxide material according to an embodiment of the present invention; FIGS. 25A to 25C all show the structure of an oxide material according to an embodiment of the present invention; 26A to 26C each show the structure of an oxide material according to an embodiment of the present invention; FIG. 27 shows the dependence of the mobility obtained by calculation on the gate voltage; FIGS. 28A to 28C all show the absorption obtained by calculation Dependence of pole current and mobility with respect to gate voltage; Figures 29A to 29C show the dependence of drain current and mobility with respect to gate voltage by calculation; Figures 30A to 30C all show acquisition by calculation 31A and 31B are cross-sectional views of the structure of the transistor used for calculation; FIGS. 32A to 32C all show characteristic curves of transistors including oxide semiconductor films. Figures 33A and 33B both show the V _g -I _d characteristic curve of the transistor of the sample 1 that has undergone the BT test; Figures 34A and 34B both show the V _g -I _d characteristic curve of the transistor of the sample 2 that has undergone the BT test Figure 35 shows the XRD spectra of sample A and sample B; Figure 36 shows the relationship between the off-state current and the substrate temperature when measuring the transistor; Figure 37 shows the dependence of I _d and field-effect mobility on V _g ; 38A shows the relationship between the substrate temperature and the critical voltage, FIG. 38B shows the relationship between the substrate temperature and the field-effect mobility; FIG. 39A is a top view of the semiconductor device, FIG. 39B is a cross-sectional view thereof; and FIG. 40A is the semiconductor device The top view, FIG. 40B is a cross-sectional view thereof.

In the following, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and those skilled in the art will clearly understand that modes and details can be modified in different ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description in the following embodiments.

Note that in some cases, the location, size, range, etc. of each structure shown in the drawings and the like are not accurately displayed for the sake of simplicity. Therefore, the present invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like.

In this manual, etc., for example, "first", "second" and Serial numbers such as "third" to avoid confusion between components, these terms are not meant to limit the number of components.

(Example 1)

In this embodiment, the basic structure of a semiconductor device according to an embodiment of the present invention will be described with reference to drawings.

1A and 1B show the structure of a semiconductor device according to an embodiment of the invention. FIG. 1A shows a cross-sectional structure of a semiconductor device. Figure 1B shows the circuit configuration.

FIG. 1A shows the structure of a semiconductor device in which a layer 301 of semiconductor elements such as transistors (hereinafter referred to as an element formation layer 301), a first wiring 302, a first interlayer film 305, a second wiring 303, a first The second interlayer film 306 and the third wiring 304 are stacked on the substrate 300. The element forming layer 301 is a region where semiconductor elements such as capacitors or resistors are formed with transistors. In FIGS. 1A and 1B, the first interlayer film 305 is thinner than the second interlayer film 306. Using the conductor layer, the first wiring 302, the second wiring 303, and the third wiring 304 are all formed to have a single-layer structure or a stacked structure. In addition, by using an insulating layer, the first interlayer film 305 and the second interlayer film 306 are formed to have a single-layer structure or a stacked structure.

FIG. 1B shows the circuit configuration of the circuit 100 and the wiring position relationship in the circuit 100. The circuit 100 includes a wiring 303a provided throughout the circuit 100, a wiring 302a branched from the wiring 303a, a transistor 101, and a region 102. In the region 102, the wiring 303a and the wiring 302a overlap each other. In addition, the wiring 303a is given an input signal and is electrically connected to the cloth The wiring 302a of the line 303a is connected to the gate electrode of the transistor 101. The second wiring 303 in FIG. 1A is used to form the wiring 303a, and the first wiring 302 in FIG. 1A is used to form the wiring 302a.

In general, the semiconductor device having the cross-sectional structure in FIG. 1A has the following problems. Since the thin first interlayer film 305 is provided between the first wiring 302 and the second wiring 303, a large parasitic capacitance may be generated in a region where the first wiring 302 and the second wiring 303 overlap each other. As a result, the delay time of the signals given to the first wiring 302 and the second wiring 303 increases, and the circuit operation is thereby slowed or stopped. To avoid this adverse effect, a structure can be adopted in which only one of the first wiring 302 and the second wiring 303 is used; however, in this case, there is a problem that the circuit area is increased by one due to the number of wiring used increase.

On the other hand, when the configuration in FIG. 1B is used, an increase in the delay time of the signal can be suppressed, but a large parasitic capacitance is generated in the region 102 where the wiring 303a and the wiring 302a overlap each other. This is because the two terminals that generate capacitance are at substantially the same potential due to the electrical connection between the wiring 303a and the wiring 302a, so that the two terminals are easily charged and discharged.

Therefore, using the first wiring and the second wiring to overlap each other with a thin interlayer film (the first interlayer film 305 in FIG. 1A) provided therebetween to form a circuit results in a circuit area that is larger than using only the first wiring and the second wiring The situation of one of the two wirings is reduced. As a result, the size reduction of the semiconductor device is achieved.

By adopting the circuit configuration shown in FIG. 1B and the positional relationship of the wiring, no matter how small the thickness of the first interlayer film 305 shown in FIG. 1A is, the area where the first wiring 302 and the second wiring 303 overlap each other is Can do As part of the circuit, it is helpful to reduce the circuit area. On the other hand, in the case of using the first interlayer film 305 as the gate insulating film of the dielectric or transistor of the capacitor in the semiconductor device, the thickness of the first interlayer insulating film 305 is preferably greater than or equal to 10 nm and Less than or equal to 300 nm, more preferably greater than or equal to 10 nm and less than or equal to 100 nm, and still more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

In addition, in the configuration in FIG. 1B, the wiring 302a may be thinner than the wiring 303a. In this case, it is concerned that the wiring 302a has a higher sheet resistance than the wiring 303a and thus has a high wiring resistance. However, when the wiring 303a is used as the long wiring 302a provided throughout the circuit 100, the wiring 302a can be used only as the short wiring; therefore, the wiring resistance of the wiring 302a is reduced. Therefore, the adverse effect of wiring resistance on circuit operation can be reduced.

In the manufacturing process of the semiconductor device, the reduction in the thickness of the wiring 302a results in a reduction in the step height of the wiring 302a provided in the lower layer, and prevents the wiring 303a from being disconnected and a short circuit between the wiring 302a and the wiring 303a. Good. For example, the thickness of the wiring 302a is preferably greater than or equal to 50 nm and less than or equal to 150 nm. By setting the thickness of the wiring 302a to the above value, the wiring 302a has a high sheet resistance, and suppresses the influence of the wiring resistance of the wiring 302a on the circuit operation, and reduces the adverse influence caused by the steps of the wiring 302a in the manufacturing process.

Note that FIG. 1B shows an embodiment in which the wiring 302a and the gate electrode of the transistor 101 are electrically connected to each other in the circuit 100 and is a typical embodiment; however, the present embodiment is not limited to this. The wiring 302a may be connected to the gate electrodes of many transistors. Alternatively, the wiring 302a may be a transistor Instead of the gate electrode connected to the transistor.

Next, a semiconductor device using the circuit configuration in FIG. 2 and the positional relationship of wiring as a semiconductor device different from that in FIG. 1B will be described. Note that the cross-sectional structure in FIG. 1A is applied to the cross-sectional structure of the semiconductor device.

FIG. 2 shows the circuit configuration of the circuit 200 and the positional relationship of the wiring in the circuit 200. The circuit 200 includes a wiring 303b, a wiring 302b, transistors 201 and 202, and a region 203. In the region 203, the wiring 303b and the wiring 302b overlap each other. The wiring 303b is given a signal input to the circuit 200 and is electrically connected to the gate electrode of the transistor 201. In addition, the wiring 302b is given a signal output from the circuit 200 and is electrically connected to one of the source electrode and the drain electrode of the transistor 202. The second wiring 303 in FIG. 1A is used to form the wiring 303b, and the first wiring 302 in FIG. 1A is used to form the wiring 302b.

The wiring 303b and the wiring 302b are given a common mode signal. Here, the common mode signal means signals having the same phase. In the case where they are digital signals, they mean signals having high level periods corresponding to each other and low level periods corresponding to each other. Note that the corresponding degree of the digital signal is preferably as follows: at least part of the rise time or fall time of the signal overlap each other. In the case where the rise time or fall time of one of the signals overlaps with the rise time or fall time of the other signals, the charging and discharging of the parasitic capacitance of each wiring is suppressed so as to be compared to the rise time or fall of one of the signals When the time does not overlap with the rise time or fall time of other signals, the delay time of the signal is reduced.

As described above, in general, the semiconductor device having the cross-sectional structure in FIG. 1A has the following problems. Since only the thin first interlayer film 305 is provided between the first wiring 302 and the second wiring 303, a large parasitic capacitance may be generated in a region where the first wiring 302 and the second wiring 303 overlap each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 increases and the circuit operation slows down or stops. To avoid this adverse effect, a structure can be adopted in which only one of the first wiring 302 and the second wiring 303 is used; however, in this case, there is a problem that since the number of wirings used is reduced by one, the area of the circuit increase.

On the other hand, when the configuration in FIG. 2 is used, the increase in the delay time of the signal can be suppressed, but a large parasitic capacitance is generated in the region 203 where the wiring 303b and the wiring 302b overlap each other. This is because the common mode signal is applied to the wiring 303b and the wiring 302b, which causes the potential difference between the two terminals that generate parasitic capacitance to decrease and suppresses the charging and discharging of the two terminals.

Therefore, the wiring 303b and the wiring 302b overlap each other and the region 203 provided with the thin interlayer film (the first interlayer film 305 in FIG. 1A) in between is used as a partial circuit, resulting in a circuit area that is larger than that using only the wiring 302b and the wiring 303b The situation is reduced. As a result, the size of the semiconductor device is reduced.

Note that the structure in which the first interlayer film 305 is thinner than the second interlayer film 306 shown in FIG. 1A is used for different semiconductor devices. For example, these semiconductor devices may have a structure in which the first wiring 302 and the second wiring 303 serve as some semiconductor elements other than the semiconductor elements formed on the element formation layer 301. Specifically, these semiconductor devices have a structure in which the first wiring 302 and the second wiring 303 serve as electrodes of the capacitor. Since the dielectric of the capacitor is thin, the capacitance value increases; therefore, the first interlayer film 305 is preferably thin. When the first wiring 302 is used as the gate electrode of the transistor and the second wiring 303 is used as the source electrode and the drain electrode of the transistor, since the first interlayer film 305 is used as the gate insulating film, In this case, the first interlayer film 305 is formed to be thin. Note that the first wiring 302 may serve as a source electrode and a drain electrode, and the second wiring 303 may serve as a gate electrode. As for the transistor, a transistor having a semiconductor active region containing amorphous silicon, a transistor having a semiconductor active region containing an oxide semiconductor, and the like are used. In addition, the first wiring 302 and the second wiring 303 may be used as part of the storage element or the resistor.

By using the circuit configuration shown in FIG. 2 and the positional relationship of the wiring, no matter how small the thickness of the first interlayer film 305 shown in FIG. 1A is, the area where the first wiring 302 and the second wiring 303 overlap each other It can be used as part of the circuit, which is helpful to reduce the circuit area. On the other hand, in the case of using the first interlayer film 305 as the gate insulating film of the dielectric or transistor of the capacitor in the semiconductor device, the thickness of the first interlayer insulating film 305 is preferably greater than or equal to 10 nm and Less than or equal to 300 nm, more preferably greater than or equal to 10 nm and less than or equal to 100 nm, and still more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

Note that FIG. 2 shows an embodiment in which, in the circuit 200, the wiring 303b and the gate electrode of the transistor 201 are electrically connected to each other, and the wiring 302b and the source electrode or the drain electrode of the transistor 202 are electrically connected to each other, and is Typical embodiment; however, this embodiment is not limited to this. The wiring 303b may be connected to one of the source electrode and the drain electrode of the transistor. Wiring 302b To connect to the gate electrode of the transistor. Alternatively, the wiring 302b and the wiring 303b may be connected to gate electrodes, source electrodes, or drain electrodes of many transistors or semiconductor devices such as capacitor mechanisms, resistor mechanisms, or diodes.

Note that although the second wiring 303 in FIG. 1A is used to form the wiring 303b and the first wiring 302 in FIG. 1A is used to form the wiring 302b in this embodiment, the second wiring 303 in FIG. 1A may be used to form The wiring 302b and the first wiring 302 in FIG. 1A are used to form the wiring 303b.

Note that in FIG. 2, the wiring 303b is given to the signal input to the circuit 200; however, the present embodiment is not limited to this. The wiring 303b may be applied to one of the internal signals of the circuit 200. In addition, in FIG. 2, the wiring 302b is applied to the signal output by the circuit 200; however, the present embodiment is not limited to this. The wiring 302b may be applied to one of the internal signals of the circuit 200.

The structures, methods, etc. described in this embodiment can be combined with the structures, methods, etc. described in other embodiments as appropriate.

(Example 2)

In this embodiment, an embodiment in which the circuit configuration described in Embodiment 1 is applied to the drive circuit of the semiconductor device will be described with reference to the drawings. In this embodiment, a storage device is used as an embodiment of a semiconductor device.

<Structure and operation of memory cells>

First, the structure of the memory cell 502 included in the storage device will be explained And operation. FIG. 3 is a circuit diagram of the memory cell 502. The memory cell 502 in FIG. 3 includes a first transistor 1201, a second transistor 1202, and a capacitor 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode and the drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. The other electrode of the source electrode and the drain electrode of the second transistor 1202 is electrically connected to one of the gate electrode of the first transistor 1201 and the electrode of the capacitor 1203. The source electrode of the first transistor 1201 is electrically connected to the source line (SL), and the drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor 1203 is electrically connected to the word line (WL).

Here, a transistor including an oxide semiconductor is used as the second transistor 1202. Since the off-state current of the transistor including the oxide semiconductor is extremely low, the memory cell including the transistor can hold the stored data for a relatively long time. In other words, the update operation becomes unnecessary or the frequency of the update operation can be quite low, resulting in a reduction in power consumption of semiconductor devices including memory cells. In addition, even when power is not supplied, the stored data can still be stored for a long time. In addition, a transistor including a semiconductor material other than an oxide semiconductor is used as the first transistor 1201. Note that regarding the semiconductor material of the first transistor 1201, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like is preferably used, and a single crystal semiconductor is preferably used. For example, the first transistor 1201 including this semiconductor material can operate at a sufficiently high speed so that the stored data can be read at high speed.

FIG. 4 is a view showing a cross section of the memory cell 502. As shown in Figure 4, The memory cell 502 includes a first transistor 1301 and a second transistor 1302 arranged to overlap at least the first transistor 1301. The second transistor 1302 is disposed above the first transistor 1301, and the gate electrode of the first transistor 1301 and one of the source electrode and the drain electrode of the second transistor 1302 are electrically connected to each other. The first transistor 1301 and the second transistor 1302 in FIG. 4 correspond to the first transistor 1201 and the second transistor 1202 in FIG. 3, respectively.

The semiconductor device in FIG. 3 uses a feature capable of holding the potential of the gate electrode of the first transistor 1201 to write, store, and read as described below.

Will explain the writing and storage of data. First, the potential of the second signal line (S2) is set to the potential that turns on the second transistor 1202, so that the second transistor 1202 turns on. Therefore, the potential of the first signal line (S1) is supplied to the gate electrode of the first transistor 1201 and the capacitor 1203. That is, a predetermined potential is applied to the gate electrode (wiring) of the first transistor 1201. Here, one of the charges for supplying two different potentials (hereinafter, the charge for supplying a low potential is called charge Q _L and the charge for supplying a high potential is called charge Q _H ) is applied to the first transistor 1201 Gate electrode. Note that charges given three or more different potentials can be applied to increase storage capacity.

After that, the potential of the second signal line (S2) is set to the potential that turns off the second transistor 1202, so that the second transistor 1202 is turned off. Therefore, the charge applied to the gate electrode of the first transistor 1201 is held (stored). Since the off-state current of the second transistor 1202 is significantly small, Therefore, the potential of the gate electrode of the first transistor 1201 is maintained for a long time.

Next, the operation of data reading will be explained. By supplying an appropriate potential (reading potential) to the word line (WL), and supplying a predetermined potential (fixed potential) to the source line (SL), the potential of the bit line (BL) is fixedly held by the first transistor 1201 The amount of charge in the gate electrode varies. In general, this is because when the first transistor 1201 is an n-channel transistor, the apparent critical voltage V _{th_H is} lower than Q _{L and} applied to the first in the case where Q _{H is} applied to the gate electrode of the first transistor 1201 In the case of the gate electrode of the transistor 1201, the critical voltage _{Vth_L is considered} . Here, the apparent threshold voltage means the voltage of the word line (WL) required to turn on the first transistor 1201.

Therefore, the potential of the word line (WL) is set to the potential V _O between V _{th_H} and V _{th_L} , and thus the charge applied to the gate electrode of the first transistor 1201 is determined. For example, in the case where Q _H is applied at the time of writing, when the potential of the word line (WL) is set to V _O , since V _{O is} higher than V _{th_H} , the first transistor 1201 is turned on. On the other hand, in the case where Q _L is applied at the time of writing, when the potential of the word line (WL) is set to V _O , since V _{O is} lower than V _{th_L} , the first transistor 1201 is maintained in the off state. Therefore, by determining the potential of the bit line (BL), the stored data is read.

Note that in the case where memory cells are arranged in rows and columns to be used, only the required memory cell data needs to be read. Therefore, in the case where the data of the predetermined memory cell is read and the data of other memory cells are not read, the potential that can turn on or off the first transistor 1201 can be supplied to it regardless of the state of the gate electrode The data is not the word line (WL) of the memory cell to be read. Specifically, regardless of the state of the gate electrode, in order to turn on the first transistor 1201, a potential higher than _{Vth_L} may be supplied to the word line (WL). Regardless of the state of the gate electrode, in order to turn off the first transistor 1201, a potential lower than V _{th_L} may be supplied to the word line (WL).

Depending on the connection relationship of the memory cells 502 (for example, depending on whether the memory cells are connected in series or in parallel), it is appropriate to decide whether to supply the potential to turn on the first transistor 1201 or turn off the potential of the first transistor 1201 to the memory cell whose data is not to be read Word line (WL).

Next, the rewriting of the material will be explained. Similar to data writing or storage, data rewriting is performed. That is, the potential of the second signal line (S2) is set to the potential to turn on the second transistor 1202, thus turning on the second transistor 1202. Therefore, the potential of the first signal line (S1) (potential related to the new data) is supplied to the gate electrode of the first transistor 1201 and the capacitor 1203. After that, the potential of the second signal line (S2) is set to the potential at which the second transistor 1202 is turned off, thus turning off the second transistor 1202. Therefore, the charge related to the new data is held in the gate electrode of the first transistor 1201.

Therefore, in the semiconductor device according to the present invention, data is directly rewritten by overwriting of new data. Therefore, there is no need to use the high voltage or the like required in the flash memory to extract the charge in the floating gate, and therefore, the decrease in the operation speed due to the wipe operation is suppressed. That is, high-speed operation of the semiconductor device is realized. Furthermore, in this case, there is no problem of deterioration of the gate insulating film (tunnel insulating film) indicated in the conventional floating gate transistor. That is to say, it is possible to ignore the deterioration of the gate insulating film that is conventionally regarded as a problem due to electron injection into the floating gate. This means that the number of writes in principle does not Unlimited.

Note that the source electrode or the drain electrode of the second transistor 1202 is electrically connected to the gate electrode of the first transistor 1201, and thus has a floating gate similar to the floating gate transistor for non-dependent storage elements Of effect. Therefore, in the figure, the portion of the source electrode or the drain electrode of the second transistor 1202 electrically connected to the gate electrode of the first transistor 1201 is called a node C. When the second transistor 1202 is turned off, the node C is considered to be embedded in the insulator, and thus the charge is held in the node C. The amount of off-state current of the second transistor 1202 including the oxide semiconductor is less than or equal to one-tenth of the amount of the off-state current of the transistor including the silicon semiconductor; therefore, due to the The loss of charge accumulated in node C of the leakage current is negligible. That is, according to the second transistor 1202 including an oxide semiconductor, it is possible to realize a substantially non-dependent storage device that can store data without being supplied with power.

For example, when the off-state current of the second transistor 1202 is 10zA (1zA (Zeptoampere is 1×10 ^-21 A) or lower at room temperature (25°C) and the capacitance value of the capacitor 1203 is about At 10fF, the data can be stored for 10 ⁴ seconds or longer. Needless to say, the storage time depends on the transistor characteristics and capacitance value.

<Structure of Semiconductor Device>

5 is an embodiment of a circuit diagram of a semiconductor device. 5 is a circuit diagram of a memory cell 502 and a driving circuit driving the memory cell 502. The driving circuit in FIG. 5 includes a column decoder 500, a column driver 501, and a memory cell 502. Many column drivers 501 and many memory cells 502 are arranged in an array.

The column driver 501 includes a NAND gate portion 504, a first level shifter 505, a first buffer 506, a second NAND gate 507, a second level shifter 508, and a second buffer 509 . The NAND gate portion 504 includes a first NAND gate 503.

<Structure and operation of driving circuit part>

The operation of the drive circuit in FIG. 5 will be explained. One of the column drivers 501 is selected by the column decoder 500. The output line of the column decoder 500 is electrically connected to one of the input portions of the first NAND gate 503 and one of the input portions of the second NAND gate 507. Meanwhile, the other input portion of the first NAND gate 503 is electrically connected to the write enable signal line (WE), and the other input portion of the second NAND gate 507 is electrically connected to the read enable signal line (RE). Therefore, during the write operation, that is, when WE is active, the output of the first NAND gate 503 is active. During the read operation, that is, when the RE is active, the output of the second NAND gate 507 is active.

The output of the first NAND gate 503 is input to the first level shifter 505, and the output of the second NAND gate 507 is input to the second level shifter 508. At the same time, the write voltage (VW) is applied to the power line of the first level shifter 505, and the read voltage (VR) is applied to the power line of the second level shifter 508. Therefore, when the output of the first NAND gate 503 is active, the first level shifter 505 performs amplification so that a voltage is generated, and when the output of the second NAND gate 507 is active, the second The level shifter 508 amplifies the output of the column decoder 500 so that a read voltage is generated. The output of the first level shifter 505 is input to the memory cell 502 through the first buffer 506 and from the second signal line (S2), and the output of the second level shifter 508 passes through the second buffer 509 and The word line (WL) is input to the memory cell 502. In addition to the second signal line (S2) and the word line (WL), the bit line (BL) and the first signal line (S1) are also connected to the memory cell 502.

As shown in FIG. 3, the memory cell 502 includes a first transistor 1201 and a second transistor 1202 arranged to overlap the first transistor 1201. Here, the layer 1300 including the first transistor 130 in FIG. 4 corresponds to the element forming layer 301 in FIG. 1A. In addition, in this embodiment, the wiring of the driving circuit portion formed through the same process as the source electrode and the drain electrode of the second transistor 1202 corresponds to the first wiring 302 in FIG. 1A. The interlayer film formed by the same process as the gate insulating film of the second transistor 1202 corresponds to the first interlayer film 305 in FIG. 1A. The wiring of the driving circuit portion formed through the same process as the gate electrode of the second transistor 1202 corresponds to the second wiring 303 in FIG. 1A. In this case, by applying the structure of Embodiment 1, the wiring of the driving circuit portion formed through the same process as the source electrode and the drain electrode of the second transistor 1202 included in the memory cell 502 and through The wiring formed by the same process of the gate electrode of the second transistor 1202 can be used as a part of the circuit. Therefore, the area of the driving circuit portion is reduced.

More specifically, the circuit configuration described in Embodiment 1 is applied to the NAND gate portion 504, the first level shifter 505, and the second level offset 移器508. The circuit configuration in FIG. 1B is applied to the NAND gate portion 504, and the circuit configuration in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508.

First, the application of the circuit configuration in FIG. 1B to the NAND gate portion 504 will be explained with reference to the drawings. FIG. 6 is a circuit diagram of the NAND gate portion 504.

The circuit in FIG. 6 includes n-channel transistors 601 and 602, p-channel transistors 603 and 604, and signal lines 605 and 606.

The signal line 605 is a common signal line that drives many NAND gates (NAND gate 503 and NAND gate 507 in FIG. 5). The signal line 606 is electrically connected to the signal line 605, the gate electrode of the n-channel transistor 601, and the gate electrode of the p-channel transistor 603.

In FIG. 6, the signal line 606 and the signal line 605 correspond to the first wiring 302 and the second wiring 303 in FIG. 1A, respectively. More specifically, the signal line 606 is formed through the same process as the source electrode and the drain electrode of the second transistor 1202 included in the memory cell 502, and through the same process as the gate electrode of the second transistor 1202 The process forms the signal line 605. Therefore, the gate insulating film of the second transistor 1202 included in the memory cell 502 and the interlayer film between the signal line 606 and the signal line 605 are formed through the same process, so that the thickness of the interlayer film is reduced. The thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

The area 607 is included in FIG. 6 in which the signal line 606 and the signal line 605 overlap each other. Although the signal line 605 and the signal line 606 overlap each other A large parasitic capacitance is generated in the region 607, but the signal delay time can be suppressed. This is because the two terminals that generate parasitic capacitance are at substantially the same potential due to the electrical connection between the signal line 605 and the signal line 606, so that the two terminals are less likely to be charged and discharged.

Note that the signal line 605 may be formed through the same process as the source electrode and the drain electrode of the second transistor 1202, and the signal line 606 may be formed through the same process as the gate electrode of the second transistor 1202. In addition, it is preferable that the thickness of the wiring formed through the same process as the source electrode and the drain electrode is greater than or equal to 100 nm and less than or equal to 150 nm, and less than the thickness of the wiring formed by the same process as the gate electrode. This is because it is possible to prevent the disconnection of the step height caused by the wiring in the lower layer (first layer).

FIG. 7 shows a partial cross section of the NAND gate portion 504. The section in FIG. 7 includes the signal line 700, the NAND gate 702, and the signal line 704. The NAND gate 702 includes transistors 703a and 703b. In FIG. 7, the transistors 703 a and 703 b are formed by the same process as the first transistor 1201 included in the memory cell 502. The signal line 704 and the signal line 700 in FIG. 7 correspond to the signal line 606 and the signal line 605 in FIG. 6, respectively. The area 705 where the signal line 700 and the signal line 704 overlap each other in FIG. 7 corresponds to the area 607 in FIG. 6.

In FIG. 7, the signal line 700 is electrically connected to the signal line 704, and the signal line 704 is electrically connected to the gate electrode of the transistor 703 a and the gate electrode of the transistor 703 b in the NAND gate 702.

8 is an actual view of the top view of the NAND gate portion 504 in FIGS. 6 and 7 Example. The broken line A-A' in Fig. 8 corresponds to the cross-sectional view A-A' in Fig. 7.

The NAND gate 802 in FIG. 8 corresponds to the NAND gate 702 in FIG. 7. The signal line 800 corresponds to the signal line 700 in FIG. 7. The signal line 804 corresponds to the signal line 704 in FIG. 7. The area 805 where the signal line 800 and the signal line 804 overlap each other corresponds to the area 705 in FIG. 7. The transistor 803a and the transistor 803b in the NAND gate 802 correspond to the transistor 703a and the transistor 703b in FIG. 7, respectively.

The transistor 703a and the transistor 703b included in the NAND gate 702 correspond to the n-channel transistor 601 and the p-channel transistor 603 in FIG. 6, respectively. The signal line 700 is formed using the same wiring layer as the gate electrode of the second transistor 1302 in FIG. 4, and using the same wiring layer as the source electrode and the drain electrode of the second transistor 1302 in FIG. 4, The signal line 704 is formed. Therefore, the thickness of the signal line 700 is preferably greater than 200 nm, and the thickness of the signal line 704 is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

The area 705 is an area where the signal line 700 and the signal line 704 are provided, and the interlayer film 706 is provided therebetween. The thickness of the interlayer film 706 is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm. The interlayer film 706 is formed by the same process as the film separating the gate electrode and the source and drain electrodes of the second transistor 1302 in FIG. 4 (that is, the gate insulating film).

The signal line 700 and the signal line 704 are only separated by a thin interlayer film 706; However, even when the interlayer insulating film between the signal line 700 and the signal line 704 is thin, since the signals input to the signal line 700 and the signal line 704 are the same in the case where the circuit configuration in FIG. 6 is applied, they are not Affect each other. Therefore, even when there is an area 705 where the signal line 700 and the signal line 704 overlap each other, the signal line 700 and the signal line 704 serve as wiring.

Next, an embodiment in which the circuit configuration in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508 in FIG. 5 will be described with reference to FIG. 9. 9 is a circuit diagram of the first level shifter 505 and the second level shifter 508.

The level shifter in FIG. 9 includes n-channel transistors 901 and 902 and p-channel transistors 903, 904, 905, and 906.

When the level shifter in FIG. 9 is at a high level, the potentials of the input signal line and the inverted signal input line are power supply potentials, and when the level shifter in FIG. 9 is at a low level, the potentials of these lines are grounded. Potential. In addition, when the level shifter in FIG. 9 is at a high level, the potentials of the output signal line and the inverted signal output line are high power supply potentials VDDH, and when the level shifter in FIG. 9 is at a low level, these lines Is the ground potential. In the case of the first level shifter 505, VW is used as the high power supply potential, and, in the case of the second level shifter 508, VR is used as the high power supply potential.

In FIG. 9, one of the input signal line 910 and the output signal line 912 corresponds to the first wiring 302 in FIG. 1A, and the other line corresponds to the second wiring 303 in FIG. 1A. More specifically, one of the input signal line 910 and the output signal line 912 is controlled by the second transistor 1202 included in the memory cell 502 The source electrode and the drain electrode are formed by the same process, and the other line is formed by the same process as the gate electrode of the second transistor 1202.

Alternatively, in FIG. 9, one of the inverted signal input line 911 and the inverted signal output line 913 may correspond to the first wiring 302 in FIG. 1A and the other line corresponds to the second wiring 303 in FIG. 1A. More specifically, the inverted signal input line 911 and the inverted signal output line 913 are formed by the same process as the source electrode and the drain electrode of the second transistor 1202 included in the memory cell 502, and the other line is formed by The gate electrode of the second transistor 1202 is formed by the same process.

Therefore, the interlayer film between the input signal line 910 and the output signal line 912 and the interlayer film between the inverted input signal line 911 and the inverted output signal line 913 are controlled by the second transistor 1202 included in the memory cell 502 The gate insulating film is formed by the same process, so that the thickness of the interlayer film is reduced. The thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

Note that the input signal line 910 is the wiring through which the input signal IN is input, and the inverted input signal line 911 is the wiring through which the inverted signal INB of the input signal is input. In addition, the output signal line 912 is a wiring through which the output signal OUT is output, and the inverted signal output line 913 is a wiring through which the inverted signal OUTB of the output signal is output.

Note that when the second transistor 1302 included in the memory cell 502 is a top gate transistor, it is preferable that the first wiring 302 in FIG. 1A is composed of the source electrode and the drain electrode of the second transistor 1302 The same process of electrode The second wiring 303 is formed by the same process as the gate electrode of the second transistor 1302. This is because the source electrode and the drain electrode are thinner than the gate electrode in the second transistor 1302, so that it is possible to prevent disconnection of the second wiring due to the step height caused by the first wiring. Note that the thickness of the first wiring (the source electrode and the drain electrode of the second transistor 1302) is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

Note that FIG. 9 shows a level shifter that converts a high-level signal from a power supply potential to a high power supply potential, and an embodiment of the present invention is similarly applied to a level that converts a low-level signal from a ground potential to a low power supply potential. Offset.

FIG. 10 shows a partial cross section of the level shifter in FIG. 9. The cross section in FIG. 10 includes transistor 1000, wiring 1001, and wiring 1002. In FIG. 10, the transistor 1000 is formed by the same process as the first transistor 1201 included in the memory cell 502. In addition, the level shifter in FIG. 10 includes a region 1003 where the wiring 1001 and the wiring 1002 overlap each other. The wiring 1001 is electrically connected to one of the source electrode and the drain electrode of the transistor 1000. Although not shown, the wiring 1002 is electrically connected to the gate electrode of a transistor different from the transistor 1000.

The transistor 1000 in FIG. 10 corresponds to the transistor in the inverter 900 in FIG. 9. The wiring 1001 and the wiring 1002 respectively correspond to the inverted signal input line 911 and the inverted signal output line 913 in FIG. 9. Alternatively, the wiring 1001 and the wiring 1002 correspond to the input signal line 910 and the output signal line 912 in FIG. 9, respectively.

Fig. 11 is an implementation of the top view of the level shifter in Figs. 9 and 10 example. The broken line B-B' in Fig. 11 corresponds to B-B' in the cross-sectional view in Fig. 10.

The transistor 1100 in FIG. 11 corresponds to the transistor 1000 in FIG. 10. The wiring 1101 corresponds to the wiring 1001 in FIG. 10. The wiring 1102 corresponds to the wiring 1002 in FIG. 10. The region 1103 where the wiring 1101 and the wiring 1102 overlap each other corresponds to the region 1003 in FIG. 10.

In FIG. 10, the wiring 1001 is formed by the same process as the gate electrode of the second transistor 1302 in FIG. 4, and the wiring 1002 is formed by the source electrode and the drain electrode of the second transistor 1302 in FIG. The same process is formed. Therefore, the thickness of the wiring 1001 is preferably greater than or equal to 200 nm, and the thickness of the wiring 1002 is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

The region 1003 is a region where the wiring 1001 and the wiring 1002 are provided, and the interlayer film 1006 is provided therebetween. The thickness of the interlayer film 1006 is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm. The interlayer film 1006 is formed by the same process as the film (that is, the gate insulating film) separating the gate electrode and the source and drain electrodes of the second transistor 1302 in FIG. 4.

In the level shifter to which the circuit configuration in FIG. 2 is applied, the wiring 1001 and the wiring 1002 are separated only by the thin interlayer film described above; however, even when the interlayer film between the wiring 1001 and the wiring 1002 is thin, Since the common mode signal is input to the wiring 1001 and the wiring 1002, the adverse effects due to the parasitic capacitance can still be suppressed. So, even when there is cloth In the region 1003 where the line 1001 and the wiring 1002 overlap each other, the wiring 1001 and the wiring 1002 can still serve as wiring.

The embodiment in which the circuit configuration in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508 of the semiconductor device in FIG. 5 is not limited to the structures in FIGS. 9, 10, and 11. For example, this embodiment may be a level shifter having the structure in FIGS. 12 and 13. FIG. 12 is a circuit diagram of the first level shifter 505 and the second level shifter 508. FIG. 13 shows a partial cross section of the level shifter in FIG.

The level shifter in FIG. 2 includes an inverter 1400, n-channel transistors 1401 and 1402, and p-channel transistors 1403, 1404, 1405, and 1406. The inverter 1400 includes an n-channel transistor 1407 and a p-channel transistor 1408.

When the level shifter in FIG. 12 is at a high level, the potential of the input signal line and the inverted signal transmission line is the power supply potential, and when the level shifter in FIG. 12 is at a low level, the potential of these lines is ground Potential. In addition, when the level shifter in FIG. 12 is at a high level, the potentials of the output signal line and the inverted signal output line are high power supply potentials VDDH, and when the level shifter in FIG. 12 is at a low level, these lines Is the ground potential. That is, in the case of the first level shifter 505, VW is used as the high power supply potential, and in the case of the second level shifter 508, VR is used as the high power supply potential.

In FIG. 12, one of the input signal line 1410 and the output signal line 1412 corresponds to the first wiring 302 in FIG. 1A, and the other line corresponds to the second wiring 303 in FIG. 1A. More specifically, the input signal line 1410 and One of the output signal lines 1412 is formed through the same process as the source electrode and the drain electrode of the second transistor 1202 included in the memory cell 502, and the other line is formed through the same process as the gate electrode of the second transistor 1202 form.

Alternatively, in FIG. 12, the inverted signal input line 1411 and the inverted signal output line 1413 may correspond to the first wiring 302 in FIG. 1A, and the other line corresponds to the second wiring 303 in FIG. 1A. More specifically, the inverted signal input line 1411 and the inverted signal output line 1413 are formed by the same process as the source electrode and the drain electrode of the transistor 1202 included in the memory cell 502, and the other line is formed by the second The gate electrode of the transistor 1202 is formed by the same process.

Therefore, the interlayer film between the input signal line 1410 and the output signal line 1412 or the interlayer film between the inverted signal input line 1411 and the inverted signal output line 1413 passes through the second transistor 1202 included in the memory cell 502 The gate insulating film is formed by the same process, so that the thickness of the interlayer film is reduced. The thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

Note that the input signal line 1410 is the wiring through which the input signal IN is input, and the inverted signal input line 1411 is the wiring through which the inverted signal INB of the input signal is input. In addition, the output signal line 1412 is a wiring through which the output signal OUT is output, and the inverted signal output line 1413 is a wiring through which the inverted signal OUTB of the output signal is output.

Note that when the second transistor 1302 included in the memory cell 502 is For the top gate type transistor, preferably, the first wiring 302 in FIG. 1 is formed by the same process as the source electrode and the drain electrode of the second transistor 1302, and the second wiring 303 is formed by the second transistor The gate electrode of 1302 is formed by the same process. This is because the source electrode and the drain electrode are thinner than the gate electrode in the second transistor 1302, so that it is possible to prevent disconnection of the second wiring due to the step height caused by the first wiring. Note that the thickness of the first wiring (the source electrode and the drain electrode of the second transistor 1302) is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

Note that FIG. 12 shows a level shifter that converts a high-level signal from a power supply potential to a high-power potential, and an embodiment of the present invention is similarly applied to a position that converts a low-level signal from a ground potential to a low-power potential. Quasi-offset.

13 shows a partial cross section of the level shifter in FIG. The cross section in FIG. 13 includes transistor 1500, wiring 1501, and wiring 1502. In FIG. 13, the transistor 1500 is formed by the same process as the second transistor 1202 included in the memory cell 502. In addition, the level shifter in FIG. 13 includes a region 1503 where the wiring 1501 and the wiring 1502 overlap each other. The wiring 1501 is electrically connected to one of the source electrode and the drain electrode of the transistor 1500. Although not shown, the wiring 1502 is electrically connected to the gate electrode of a transistor different from the transistor 1500.

The transistor 1500 in FIG. 13 corresponds to the n-channel transistor 1407 in the inverter 1400 in FIG. 12. The wiring 1501 and the wiring 1502 correspond to the inverted signal input line 1411 and the inverted signal output line 1413 in FIG. 12, respectively. Alternatively, the wiring 1501 and the wiring 1502 correspond to those in FIG. 12 Input signal line 1410 and output signal line 1412.

In FIG. 13, the wiring 1501 is formed by the same process as the gate electrode of the second transistor 1302 in FIG. 4, and the wiring 1502 is formed by the same source and drain electrodes as the second transistor 1302 in FIG. 4 Process formation. Therefore, the thickness of the wiring 1501 is preferably greater than or equal to 200 nm, and the thickness of the wiring 1502 is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

The region 1503 is a region where the wiring 1501 and the wiring 1502 are provided, and the interlayer film 1506 is provided therebetween. The thickness of the interlayer film 1506 is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm. The interlayer film 1506 is formed through the same process as the film separating the gate electrode and the source and drain electrodes of the second transistor 1302 in FIG. 4 (that is, the gate insulating film).

In the level shifter to which the circuit configuration in FIG. 2 is applied, the wiring 1501 and the wiring 1502 are separated only by the above-mentioned thin interlayer film; however, even when the interlayer film between the wiring 1501 and the wiring 1502 is thin, since The common mode signal is input to the wiring 1501 and the wiring 1502, so that the adverse effect due to the parasitic capacitance can still be suppressed. As such, even when there is a region 1503 where the wiring 1501 and the wiring 1502 overlap each other, the wiring 1501 and the wiring 1502 can still serve as wiring.

Next, an embodiment in which the structure in FIG. 1A is applied to a circuit including a buffer that can also be used in the semiconductor device in FIG. 5 will be described with reference to FIG. 14. FIG. 14 shows an embodiment of a circuit including a common signal line. The same signal line is input to many circuits included in the semiconductor device, and the signal line branched from the common signal line is used as wiring in the circuit.

The circuit 1601 in FIG. 14 includes a buffer 1602 and a circuit 1603. The input electrode of the buffer 1602 is electrically connected to the signal line 1604. The signal line 1600 is a common signal line that drives many circuits including the circuit 1601, and is electrically connected to the signal line 1604. The signal line 1605 is electrically connected to the output end of the buffer 1602 and the input end of the circuit 1603.

In FIG. 14, the signal line 1604 and the signal line 1600 correspond to the first wiring 302 and the second wiring 303 in FIG. 1A, respectively. More specifically, the signal line 1604 is formed by the same process as the source electrode and the drain electrode of the second transistor 1202 included in the memory cell 502, and the signal line 1600 is formed by the same gate electrode of the second transistor 1202 The formation of the process. Similarly, the signal line 1605 corresponds to the first wiring 302 in FIG. 1A.

Therefore, the gate insulating film of the second transistor 1202 included in the memory cell 502, the interlayer film between the signal line 1600 and the signal line 1604, and the interlayer film between the signal line 1600 and the signal line 1605 go through the same process It is formed so that the thickness of the interlayer film decreases. The thickness of the interlayer film is greater than or equal to 10 nm and less than or equal to 300 nm, preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm.

Note that when the second transistor 1202 included in the memory cell 502 is a top gate transistor, it is preferable that the first wiring 302 in FIG. 1 is composed of the source electrode and the drain electrode of the second transistor 1302 The electrodes are formed in the same process, and the second wiring 303 is electrically connected to the gate of the second transistor 1302 The very same process is formed. This is because the source electrode and the drain electrode are thinner than the gate electrode in the second transistor 1302, so that it is possible to prevent disconnection of the second wiring due to the step height caused by the first wiring. Note that the thickness of the first wiring (the source electrode and the drain electrode of the second transistor 1302) is preferably greater than or equal to 100 nm and less than or equal to 150 nm.

The structures, methods, etc. described in this embodiment can be combined with any structures, methods, etc. described in other embodiments as appropriate.

(Example 3)

In this embodiment, the structure and manufacturing method of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 15A to 20C. Specifically, the structure and manufacturing method of the memory cell mounted on the storage device will be described.

<Sectional structure and planar structure of semiconductor device>

15A and 15B show structural examples of semiconductor devices. 15A shows a cross section of the semiconductor device, and FIG. 15B shows a plan view of the semiconductor device. Here, FIG. 15A corresponds to the A1-A2 and B1-B2 sections in FIG. 15B. The semiconductor device shown in FIGS. 15A and 15B includes a transistor 160 and a transistor 162, the transistor 160 includes a first semiconductor material in the lower portion, and the transistor 162 includes a second semiconductor material in the upper portion. Here, the first semiconductor material is preferably different from the second semiconductor material. For example, a semiconductor material other than an oxide semiconductor is used as the first semiconductor material, and an oxide semiconductor is used as the second semiconductor material. Examples In other words, the semiconductor material other than the oxide semiconductor may be silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide and is preferably single crystal. Alternatively, organic semiconductor materials or the like can be used. Transistors containing this semiconductor material other than oxide semiconductors can be easily operated at high speed. On the other hand, transistors containing oxide semiconductors can hold charges for a long time due to their characteristics. The semiconductor device in FIGS. 15A and 15B serves as a memory cell.

Since the technical essence of the present invention is to use a semiconductor material such as an oxide semiconductor that can sufficiently reduce the off-state current in the transistor 162, so that data can be stored, there is no need to change the material of the semiconductor device or the structure of the semiconductor device The specific structure of the semiconductor device is limited to the structure described here.

The transistor 160 in FIGS. 15A and 15B includes a channel formation region 134 provided in a semiconductor layer on the semiconductor substrate 400, and a plurality of channel impurity regions 132 (also referred to as source and drain regions) provided between the channel formation regions 134 1. The gate insulating film 122a provided on the channel forming region 134 and the gate electrode 128a provided on the gate insulating film 122 so as to overlap the channel forming region 134. Note that, for convenience, the source electrode and the drain electrode are clearly shown in the figure as a transistor. In addition, in this case, in the description of the connection relationship of the transistors, the source region and the source electrode are collectively called "source electrode", and the drain region and the drain electrode are collectively called "drain electrode". That is, in this specification, the term "source electrode" includes the source region. In addition, the term "drain electrode" includes the drain region.

In addition, the conductor layer 128b is connected to the impurity region 126 in the semiconductor layer provided on the semiconductor substrate 400. Here, the conductor layer 128b also serves as an electrical The source electrode or the drain electrode of the crystal 160. In addition, the impurity region 130 is provided between the impurity region 132 and the impurity region 126. In addition, the insulating layers 136, 138, and 140 are disposed to cover the transistor 160. Note that in order to achieve higher integration, as shown in FIGS. 15A and 15B, the transistor 160 preferably has a structure without a sidewall insulating layer. On the other hand, when the characteristics of the transistor 160 have priority, the sidewall insulating layer may be provided on the side surface of the gate electrode 128a, and the impurity region 132 may include a plurality of regions having different impurity concentrations.

The transistor 162 in FIGS. 15A and 15B includes an oxide semiconductor layer 144 provided on the insulating layer 140 and the like, a source (or drain) electrode 142a and a drain (or source) electrically connected to the oxide semiconductor layer 144 The electrode 142b, the gate insulating film 146 covering the oxide semiconductor layer 144 and the source and drain electrodes 142a and 142b, and the gate electrode 148a provided on the gate insulating film 146 and overlapping the oxide semiconductor layer 144.

Here, the oxide semiconductor layer 144 is preferably highly purified by sufficiently removing impurities such as hydrogen or sufficiently supplying oxygen. Specifically, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 ¹⁹ atoms/cm ³ or lower, preferably 5×10 ¹⁸ atoms/cm ³ or lower, more preferably 5×10 ¹⁷ atoms/ cm ³ or lower. Note that the hydrogen concentration in the oxide semiconductor layer 144 is measured with a secondary ion mass spectrometer (SIMS). In the oxide semiconductor layer 144 which is highly purified by sufficiently reducing the hydrogen concentration and which reduces the defect level in the energy gap due to oxygen deficiency by supplying sufficient oxygen, the carrier concentration is lower than 1 ×10 ¹² /cm ³ , preferably below 1×10 ¹¹ /cm ³ , more preferably below 1.45×10 ¹⁰ /cm ³ . For example, the off-state current (here, the current per micrometer (μm) of the channel length) at room temperature (25°C) is lower than or equal to 100zA (1zA (zeptoampere is 1×10 ^-21 A) , Preferably less than or equal to 10zA. In this way, by using an i-type (essential) or substantially i-type oxide semiconductor, a transistor 162 having a fairly favorable off-state current characteristic is obtained.

Although the oxide semiconductor layer 144 processed to have an island shape is used to suppress leakage currents generated between elements due to the miniaturization of the transistor 162 of FIGS. 15A and 15B, it is possible to use The structure of the oxide semiconductor layer 144. In the case where the oxide semiconductor layer is not processed to have an island shape, it is possible to prevent contamination of the oxide semiconductor layer 144 caused by etching during the manufacturing process.

The capacitor 164 in FIGS. 15A and 15B includes a drain electrode 142b, a gate insulating layer 146, and a conductor layer 148b. That is, the drain electrode 142b serves as one of the electrodes of the capacitor 164, and the conductor layer 148b serves as the other electrode of the capacitor 164. With this structure, the capacitance can be sufficiently ensured. In addition, when the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked, the insulation between the drain electrode 142b and the conductor layer 148b can be sufficiently ensured. In the case where a capacitor is not required, the capacitor 164 may be omitted.

In this embodiment, the transistor 162 and the capacitor 164 are arranged to overlap at least the transistor 160. By using this planar layout, high integration can be achieved. For example, if the smallest feature size is F, the area occupied by the memory cell is 15F ² to 25F ² .

The insulating layer 150 is provided on the transistor 162 and the capacitor 164. wiring 154 is provided in the opening formed in the gate insulating film 146 and the insulating layer 150. The wiring 154 electrically connects one memory cell to another memory cell. The wiring 154 is connected to the impurity region 126 via the source electrode 142a and the conductor layer 128b. Compared with the source region or the drain region in the transistor 160, the above structure allows the number of wirings to be reduced, and the source electrode 142a in the transistor 162 is connected to different wirings. Therefore, the integration degree of the semiconductor device is increased.

Since the conductor layer 128b is provided, the positions where the impurity regions 126 and the source electrode 142a are connected to each other and the positions where the source electrode 142a and the wiring 154 are connected to each other overlap each other. With this planar layout, it is possible to prevent the element area from increasing due to the contact area. In other words, the integration of the semiconductor device is increased.

Note that in the semiconductor device in FIGS. 15A and 15B, the layer including the transistor 160 corresponds to the element forming layer 301 in FIG. 1A. The semiconductor storage device described in this embodiment includes the memory cell in FIGS. 15A and 15B and a driving circuit portion (not shown) for driving the memory cell. The first wiring 302 in FIG. 1A corresponds to the wiring in the driving circuit portion, which is connected to the source electrode 142a (drain electrode 142b) of the transistor 162 (the source electrode 142a of the transistor 162 (drain The pole electrodes 142b) the wiring in the same layer) are formed by the same process. The first interlayer film 305 in FIG. 1A corresponds to the insulating layer in the driving circuit portion, which is formed through the same process as the gate insulating film 146 of the transistor 162. Note that the gate insulating film 146 that is not patterned may serve as the first interlayer film 305. The second wiring 303 in FIG. 1A corresponds to the wiring in the driving circuit portion, and the wiring passes through the same process as the gate electrode 148a of the transistor 162 form. The second interlayer film 306 in FIG. 1A corresponds to being formed through the same process as the insulating layer 150 of the transistor 162. Note that the unpatterned insulating layer 150 may serve as the second interlayer film 306. The third wiring 304 in FIG. 1A corresponds to the wiring in the driving circuit portion, which is formed through the same process as the wiring 154 of the transistor 162.

<Manufacturing method of SOI substrate>

Next, an embodiment of a method for manufacturing an SOI substrate for manufacturing the above-described semiconductor device will be described with reference to FIGS. 16A to 16G.

First, the semiconductor substrate 400 is prepared as a base substrate (see FIG. 16A). As the semiconductor substrate 400, a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate is used. Alternatively, a solar-grade silicon (SOG-Si) substrate is used as the semiconductor substrate. Alternatively, a polycrystalline semiconductor substrate can be used. In the case of using an SOG-Si substrate, a polycrystalline silicon semiconductor substrate, etc., the manufacturing cost is reduced compared to the case of using a single crystal silicon substrate or the like.

Note that various glass substrates used in the electronics industry such as aluminum silicate glass, aluminum borosilicate glass, and barium borosilicate glass substrates; quartz substrates; ceramic substrates; and sapphire substrates can be used to replace the semiconductor substrate 400. Alternatively, a ceramic substrate containing silicon nitride and aluminum nitride as main components and having a thermal expansion coefficient close to that of silicon is used.

The surface of the semiconductor substrate 400 is preferably cleaned in advance. Specifically, hydrochloric acid/hydrogen peroxide mixture (HPM), sulfuric acid/hydrogen peroxide mixture (SPM), ammonium hydroxide mixture (APM), diluted hydrofluoric acid (DHF), or the like, the surface of the semiconductor substrate 400 is preferably cleaned.

Next, a bonding substrate is prepared. Here, the single crystal semiconductor substrate 410 is used as a bonding substrate (see FIG. 16B). Note that although a substrate whose crystallinity is single crystal is used as a bonding substrate here, the crystallinity of the bonding substrate need not be limited to single crystal.

As for the single crystal semiconductor substrate 410, for example, a single crystal semiconductor substrate formed of a group 14 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate can be used. In addition, a compound semiconductor substrate of gallium arsenide, indium phosphide, or the like is used. Typical examples of commercial silicon substrates are round silicon substrates with diameters of 5 inches (125 mm), 6 inches (150 mm), 8 inches (200 mm), 12 inches (300 mm), and 16 inches (400 mm). Note that the single crystal semiconductor substrate 410 need not be circular, for example, it may be a substrate processed into a rectangle. In addition, the single crystal semiconductor substrate 410 is formed by the Tchaiski (CZ) method or the floating zone (FZ) method.

An oxide film 412 is formed on the surface of the single crystal semiconductor substrate 410 (see FIG. 16C). Considering the removal of contaminants, preferably, before the oxide film 412 is formed, hydrochloric acid/hydrogen peroxide mixture (HPM), sulfuric acid/hydrogen peroxide mixture (SPM), ammonium hydroxide mixture (APM ), diluted hydrofluoric acid (DHF), hydrofluoric acid, mixed solution of hydrogen peroxide water, and pure water (FPM), or the like, to clean the surface of the single crystal semiconductor substrate 410. The diluted hydrofluoric acid and ozone water are alternately discharged to clean the surface of the single crystal semiconductor substrate 410.

The oxide film 412 is formed to have a single-layer structure or a stacked-layer structure including any of a silicon oxide film, a silicon oxynitride film, and the like. As for the method for forming the oxide film 412, a thermal oxidation method, a CVD method, a sputtering method, or the like can be used. When the oxide film 412 is formed by the CVD method, an organic silane such as tetramethoxy silicon (abbreviation: TEOS) (chemical formula: Si(OC ₂ H ₅ ) ₄ ) is used, and a silicon oxide film is preferably formed so as to obtain advantages Combine.

In this embodiment, thermal oxidation treatment is performed on the single crystal semiconductor substrate 410 to form an oxide film 412 (here, SiO _x film). In a halogen-added oxidation atmosphere, thermal oxidation treatment is preferably performed.

For example, in an oxidizing atmosphere in which chlorine (Cl) is added, thermal oxidation treatment of the single crystal semiconductor substrate 410 is performed, and thus the oxide film 412 is formed via chlorine oxidation. In this case, the oxide film 512 is a film containing chlorine atoms. By this chlorine oxidation, heavy metals (for example, Fe, Cr, Ni, or Mo) that are not essential impurities are captured, and metal chlorides are formed and then moved to the outside, thus reducing the contamination of the single crystal semiconductor substrate 410 .

Note that the halogen atoms contained in the oxide film 412 are not limited to chlorine atoms. Fluorine atoms may be contained in the oxide film 412. Regarding the fluorine oxidation method on the surface of the single crystal semiconductor substrate 410, a method of immersing the single crystal semiconductor substrate 410 in an HF solution and then subjecting it to thermal oxidation treatment in an oxidizing atmosphere, and performing heat in an oxidizing atmosphere with NF ₃ added Oxidation treatment methods, etc.

Next, the ions are accelerated by the electric field and the single crystal semiconductor substrate 410 is exposed to the ions, so that the ions are added to the single crystal semiconductor substrate 410, thereby forming a brittle region with a damaged crystal structure at a predetermined depth in the single crystal semiconductor substrate 410 414 (see Figure 16D).

The depth of the brittle region 414 is controlled by the kinetic energy of the ions, the charge, or the angle of incidence, or the like. The brittle region 414 is formed at a depth almost the same as the average penetration depth of ions. Therefore, the thickness of the single crystal semiconductor layer to be separated from the single crystal semiconductor substrate 410 can be controlled by the depth of added ions. For example, the average penetration depth can be controlled so that the thickness of the single crystal semiconductor layer is about 10 nm to 500 nm, preferably 50 nm to 200 nm.

Perform ion exposure treatment with ion doping equipment or ion implantation equipment. Regarding a typical embodiment of the ion doping apparatus, there is a non-mass separation type apparatus in which plasma excitation of process gas is performed and objects to be treated are exposed with all kinds of ion species generated. In this equipment, there is no mass separation, and various objects of plasma are used to expose the object to be treated. In contrast, the ion implantation equipment is a mass separation equipment. In the ion implantation apparatus, mass separation of plasma ion species is performed and objects to be treated are exposed with ion species having a predetermined mass.

In this embodiment, an embodiment in which hydrogen is added to the single crystal semiconductor substrate 410 using ion doping equipment will be explained. Use hydrogen-containing gas as the source gas. Regarding the ions used for irradiation, the ratio of H ₃ ⁺ is preferably set to be high. Specifically, it is preferable that the ratio of H ₃ ⁺ is set to 50% or more (more preferably, 80% or more) relative to the total amount of H ⁺ , H ₂ ⁺ , and H ₃ ⁺ . . By increasing the proportion of H ₃ ⁺ , the efficiency of ion exposure is improved.

Note that the ions to be added are not limited to hydrogen ions. You can add helium ions and so on. In addition, the ion to be added is not limited to one kind of ion, and multiple kinds of ions can be added. For example, in the doping equipment with ions, hydrogen and In the case of helium exposure, the number of steps can be reduced and the surface roughness of the single crystal semiconductor layer to be performed later can be reduced as compared with the case where hydrogen and helium exposure are performed in different steps.

Note that when the brittle region 414 is formed using an ion doping apparatus, heavy metals can also be added; however, ion exposure is performed through the oxide film 412 containing halogen atoms, and therefore, a single crystal semiconductor substrate due to heavy metals can be prevented 410 pollution.

Then, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are arranged to face each other, and the oxide film 412 is provided therebetween to firmly adhere to each other. Therefore, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are bonded to each other (see FIG. 16E). Note that an oxide film, or a nitride film may be formed on the surface of the semiconductor substrate 400 to which the single crystal semiconductor substrate 410 is to be attached.

When performing bonding, it is preferable that a pressure greater than or equal to 0.001 N/cm ² and less than or equal to 100 N/cm ² , for example, a pressure greater than or equal to 1 N/cm ² and less than or equal to 20 N/cm ² is applied to the semiconductor substrate Part of 400 or part of single crystal semiconductor substrate 410. When the bonding surfaces are brought close to each other and firmly bonded to each other by applying pressure, the bonding between the semiconductor substrate and the oxide film 412 is firmly bonded to each other, and the bonding naturally spreads to almost The entire area. This bonding is performed under the influence of Van der Waals force, or hydrogen bonding is performed at room temperature.

Note that before the single crystal semiconductor substrate 410 and the semiconductor substrate 400 are bonded to each other, the surfaces to be bonded to each other are preferably subjected to surface treatment. Surface treatment can increase between single crystal semiconductor substrate 410 and semiconductor substrate 400 Joint strength at the interface.

As for the surface treatment, wet treatment, dry treatment, or a combination of wet treatment and dry treatment can be used. Alternatively, a wet treatment using a combination of different wet treatments, or a dry treatment using a combination of different dry treatments.

Note that after bonding, heat treatment for increasing the bonding strength may be performed. This heat treatment is performed at a temperature that does not extend away from the brittle region 414 (for example, a temperature higher than or equal to room temperature and lower than 400°C). Alternatively, the semiconductor substrate 400 and the oxide film 412 are bonded to each other and they are heated at a temperature in this range. A diffusion furnace, a heating furnace such as a resistance heating furnace, a rapid thermal annealing (RTA) equipment, a microwave heating equipment, etc. are used to perform heat treatment. The above temperature conditions are only examples, and the embodiment of the present invention should not be interpreted as being limited to this embodiment.

Next, heat treatment is performed to cause separation of the single crystal semiconductor substrate 410 in the brittle region, so that the single crystal semiconductor layer 416 is formed on the base substrate 400 with the oxide film 412 in between (see FIG. 16F).

Note that it is preferable that the heat treatment temperature at the time of separation is as low as possible. This is because the lower the temperature during separation, the more the surface roughness of the single crystal semiconductor layer 416 can be suppressed. Specifically, the heat treatment temperature at the time of separation may be higher than or equal to 300°C and lower than or equal to 600°C, and when the temperature is higher than or equal to 400°C and lower than or equal to 500°C, the heat treatment is more effective.

Note that after the single crystal semiconductor substrate 410 is separated, the single crystal semiconductor layer 416 may undergo a heat treatment at 500° C. or higher, so that the concentration of hydrogen remaining in the single crystal semiconductor layer 416 decreases.

Next, the surface of the single crystal semiconductor layer 416 is irradiated with laser light, so that a single crystal semiconductor layer 418 with improved surface flatness and reduced defects is formed (see FIG. 16G). Note that heat treatment may be performed instead of laser light irradiation treatment.

Although in the present embodiment, the laser light irradiation process is performed immediately after the heat treatment for the separation of the single crystal semiconductor layer 416, an embodiment of the present invention should not be construed as being limited thereto. After performing the separation heat treatment of the single crystal semiconductor layer 416 in this order and the etching process of removing the area containing many defects on the surface of the single crystal semiconductor layer 416, the laser light irradiation process is performed. Alternatively, after improving the surface flatness of the single crystal semiconductor layer 416, laser light irradiation processing is performed. Note that the etching process may be wet etching or dry etching. In addition, in the present embodiment, after the above laser light irradiation, the thickness reduction step of the single crystal semiconductor layer 416 may be performed. In order to reduce the thickness of the single crystal semiconductor layer 416, either or both of dry etching and/or wet etching may be used.

Through the above steps, an SOI substrate including the single crystal semiconductor layer 418 having favorable characteristics is obtained (see FIG. 16G).

<Manufacturing method of semiconductor device>

Next, a method of manufacturing a semiconductor device formed using an SOI substrate will be described with reference to FIGS. 17A to 17E, FIGS. 18A to 18D, FIGS. 19A to 19D, and FIGS. 20A to 20C.

<Manufacturing method of lower transistor>

First, the manufacturing method of the transistor 160 in the lower part will be explained with reference to FIGS. 17A to 17E and FIGS. 18A to 18D. Note that FIGS. 17A to 17E and FIGS. 18A to 18D show a part of the SOI substrate formed by the method described with reference to FIGS. 16A to 16G, and are processes for showing transistors in the lower part of FIG. 15A.

First, the single crystal semiconductor layer 418 is patterned to have an island shape, so that the semiconductor layer 120 is formed (see FIG. 17A). Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. In the case of using silicon as a semiconductor, phosphorus, arsenic, etc. can be used as impurity elements that impart n-type conductivity. On the other hand, boron, aluminum, gallium, etc. can be used as impurity elements that impart p-type conductivity.

Next, an insulating layer 122 is formed to cover the semiconductor layer 120 (see FIG. 17B). The insulating layer 122 will become a gate insulating film later. For example, by performing heat treatment (thermal oxidation treatment, thermal nitridation treatment, etc.) on the surface of the semiconductor layer 120, the insulating layer 122 is formed. Instead of heat treatment, high-density plasma treatment can be used. For example, a high-density plasma treatment is performed using a mixed gas of a rare gas such as He, Ar, Kr, or Xe and any gas of oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. Needless to say, the insulating layer is formed by the CVD method, the sputtering method, or the like. The insulating layer 122 preferably has a single-layer structure or a stacked structure. The single-layer structure or the stacked structure includes silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x>0, y>0)), nitrogen-added hafnium silicate (HfSi _x O _y (x>0, y>0)), nitrogen-added hafnium aluminate (HfAl _x O _y ( x>0, y>0)), etc. any of the films. For example, the thickness of the insulating layer 122 is greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 10 nm and less than or equal to 50 nm. In this embodiment, a single-layer insulating layer containing silicon oxide is formed by a plasma CVD method.

Next, a mask 124 is formed on the insulating layer 122 and an impurity element imparting a conductivity type is added to the semiconductor layer 120, so that an impurity region 126 is formed (see FIG. 17C). Note that the mask 124 is removed after the impurity element is added.

Next, a mask is formed on the insulating layer 122 and a part of the insulating layer 122 overlapping with the impurity region 126 is partially removed, so that a gate insulating layer 122a is formed (see FIG. 17D). By, for example, wet etching or dry etching, part of the insulating layer 122 is removed.

Next, a conductor layer for forming the gate electrode (including the wiring formed in the same layer as the gate electrode) is formed on the gate insulating layer 122a and processed so that the gate electrode 128a and the conductor layer 128b are formed (please (See Figure 17E).

Using a metal material such as aluminum, copper, titanium, tantalum, or tungsten, a conductor layer for the gate electrode 128a and the conductor layer 128b is formed. A semiconductor material such as polysilicon is used to form a layer containing a conductive material. The method for forming the layer containing the conductive material is not particularly limited, and various forming methods such as a vapor deposition method, a CVD method, a sputtering method, and a spin coating method can be used. The conductor layer is processed by etching using a photoresist mask.

Next, by using the gate electrode 128a and the conductor layer 128b as a mask The mask adds an impurity element imparting a conductivity type to the semiconductor layer, so that the channel formation region 134, the impurity region 132, and the impurity region 130 are formed (see FIG. 18A). For example, an impurity element such as phosphorus (P) or arsenic (As) is added to form an n-channel transistor, and an impurity element such as boron (B) or aluminum (Al) is added to form a p-channel transistor. Here, the concentration of the impurity element to be added is appropriately set. In addition, after the impurity element is added, heat treatment for activation is performed. Here, the descending order of the concentration of the impurity element in the impurity region among the impurity region 126, the impurity region 132, and the impurity region 130 is as follows: the impurity region 126, the impurity region 132, and the impurity region 130.

Next, an insulating layer 136, an insulating layer 138, and an insulating layer 140 are formed to cover the gate insulating layer 122a, the gate electrode 128a, and the conductor 128b (see FIG. 18).

The insulating layer 136, the insulating layer 138, and the insulating layer 140 are formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, or aluminum oxide. Using a low dielectric constant (low-k) material, it is particularly preferable to form the insulating layer 136, the insulating layer 138, and the insulating layer 140, which can sufficiently reduce the capacitance due to overlapping electrodes or wiring. Note that the insulating layer 136, the insulating layer 138, and the insulating layer 140 may be porous insulating layers formed using any of the above materials. Since the porous insulating layer has a lower dielectric constant than the dense insulating layer, the capacitance due to the electrode or wiring can be further reduced. Alternatively, the insulating layer 136, the insulating layer 138, and the insulating layer 140 are formed using an organic insulating material such as polyimide or acrylic acid. In this embodiment, silicon oxynitride will be explained It is used when the insulating layer 136, silicon oxynitride is used for the insulating layer 138, and silicon oxide is used for the insulating layer 140. Note that the stacked structure of the insulating layer 136, the insulating layer 138, and the insulating layer 140 is used here; however, an embodiment of the present invention is not limited to this. Alternatively, a single-layer structure, or a two-layer structure, or a stacked structure of four or more layers may be used.

Then, the insulating layer 138 and the insulating layer 140 are subjected to a chemical mechanical polishing (CMP) process or an etching process, so that the insulating layer 138 and the insulating layer 140 are planarized (see FIG. 18C). Here, the CMP process is performed until the insulating layer 138 is partially exposed. When silicon oxynitride is used for the insulating layer 138 and silicon oxide is used for the insulating layer 140, the insulating layer 138 serves as an etch stop.

Next, the insulating layer 138 and the insulating layer 140 are subjected to a CMP process or an etching process, so that the upper surfaces of the gate electrode 128a and the conductor layer 128b are exposed (see FIG. 18D). Here, etching is performed until the gate electrode 128a and the conductor layer 128b are partially exposed. Regarding the etching process, the dry etching process is preferably performed, but wet etching may be performed. In the step of partially exposing the gate electrode 128a and the conductor layer 128b, in order to enhance the characteristics of the transistor 162 to be formed later, the surfaces of the insulating layer 136, the insulating layer 138, and the insulating layer 140 are preferably only flat Change.

Through the above steps, the transistor 160 in the lower part is formed (see FIG. 18D).

Note that before or after the above steps, steps for forming added electrodes, wirings, semiconductor layers, insulating layers, etc. may be performed. For example, a multilayer wiring structure in which an insulating layer and a conductor layer are stacked can be used as The wiring structure provides a highly integrated semiconductor device.

<Manufacturing method of power-on crystal>

Next, a method of manufacturing the transistor 162 in the upper part will be described with reference to FIGS. 19A to 19D and FIGS. 20A to 20C.

First, an oxide semiconductor layer is formed and processed on the gate electrode 128a, the conductor layer 128b, the insulating layer 136, the insulating layer 138, the insulating layer 140, etc., so that the oxide semiconductor layer 144 is formed (please refer to FIG. 19A). Note that before forming the oxide semiconductor layer, an insulating layer as a base is formed on the insulating layer 136, the insulating layer 138, and the insulating layer 140. The insulating layer is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method.

The oxide semiconductor to be used preferably contains at least indium (In) or zinc (Zn). In particular, it preferably contains indium (In) and zinc (Zn). Preferably, it also contains gallium (Ga) as a stabilizer for reducing changes in electrical characteristics of transistors including oxide semiconductors. It preferably contains tin (Sn) as a stabilizer. It is preferable to contain hafnium (Hf) as a stabilizer. It preferably contains aluminum (Al) as a stabilizer.

It may contain, for example, lanthanum (La), cerium (Ce), palladium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), ytterbium (Tb), dysprosium (Dy), 鈥( One or more lanthanoid elements such as Ho), erbium (Er), strontium (Tm), ytterbium (Yb), and lutetium (Lu) are used as another stabilizer.

For example, the following can be used as an oxide semiconductor: oxidation Indium, tin oxide, zinc oxide, for example, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based Oxides, In-Mg-based oxides, or In-Ga-based oxides and other two-component metal oxides, such as In-Ga-Zn-based oxides (also known as IGZO), In-Al -Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxidation Compounds, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd- Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide , In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn Three-component metal oxides such as oxides based on In-Lu-Zn or oxides based on In-Sn-Ga-Zn or based on In-Hf-Ga-Zn Oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, or In-Hf-Al-Zn Based on oxides and other four-component metal oxides.

Note that, for example, here "In-Ga-Zn-based oxide" means an oxide containing In, Ga, and Zn as its main components and the ratio of In, Ga, and Zn is not particularly limited . The oxide based on In-Ga-Z contains another metal element plus In, Ga, and Zn.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m>0 is satisfied and m is not an integer) is used as the oxide semiconductor. Note that M represents selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₃ SnO ₅ (ZnO) _n (where n>0 is satisfied and n is an integer) is used as the oxide semiconductor.

For example, use In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/ 5: 1/5) atomic ratio of In-Ga-Zn based oxides, or any oxides whose composition is in the vicinity of the above composition. Alternatively, use In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio of In-Sn-Zn-based oxide, or the composition is in the above Any oxides near the ingredients.

Note that an embodiment of the present invention is not limited to this, and a material having an appropriate composition depending on semiconductor characteristics (mobility, critical value, variation, etc.) is used. In addition, it is preferable to appropriately set carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc., to obtain desired semiconductor characteristics.

For example, with In-Sn-Zn-based oxides, it is quite easy to achieve high mobility. However, even with In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

Note that, for example, the composition of an oxide having an atomic ratio of In:Ga:Zn=a:b:c (a+b+c=1) is having In:Ga:Zn=A:B:C (A+B+C=1) The atomic ratio of the vicinity of the oxide component” means that a, b, and c satisfy the following relationship: (aA) ² + (bB) ² + (cC) ² ≦r ² . For example, the variable r may be 0.05. The same can be applied to other oxides.

The oxide semiconductor can be a single crystal oxide semiconductor or non-single crystal oxygen Compound semiconductor. In the latter case, the non-single-crystal oxide semiconductor may be amorphous or polycrystalline. In addition, the oxide semiconductor may have an amorphous structure including a part of crystallinity, or an amorphous structure.

In an oxide semiconductor in an amorphous state, it is relatively easy to obtain a flat surface, so that when an oxide semiconductor is used to manufacture a transistor, interfacial scattering can be suppressed, and a relatively high mobility can be achieved relatively easily.

In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced, and when the surface flatness is improved, a higher mobility can be achieved than that of the oxide semiconductor layer in an amorphous state. In order to improve surface uniformity, the oxide semiconductor is preferably formed on a flat surface. Specifically, the oxide semiconductor may be formed when the average surface roughness (Ra) is less than or equal to 1 nm, preferably less than or equal to 0.3 nm, and more preferably less than or equal to 0.1 nm.

Note that in this specification, Ra means the centerline average roughness obtained by three-dimensionally expanding the centerline average roughness defined by JIS B0601 to the plane to be measured. R _a can be expressed as "the average value of the absolute value of the offset from the reference plane to the specified plane" and is defined by the following equation.

Note that in Equation 1, S ₀ represents the measurement surface (represented by coordination (x ₁ , y ₁ ), (x ₁ , y ₂ ), (x ₂ , y ₁ ), and (x ₂ , y ₂ ) The area defined by the four points of the rectangle), Z ₀ represents the average height of the measurement surface. Using atomic force microscopy (AFM) to measure R _a.

In this embodiment, an oxide containing a crystal having c-axis alignment (referred to as a C-axis alignment crystal (CAAC)) will be described. The C-axis alignment crystal has a triangle when viewed from the direction of the ab plane, surface, or interface Or hexagonal atom configuration. In the crystal, metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or b-axis changes in the a-b plane (the crystal rotates around the c-axis).

Broadly speaking, an oxide including CAAC means a non-single-crystal oxide, which includes a phenomenon in which, when viewed from a direction perpendicular to the ab plane, it has a triangle, hexagon, regular triangle, Or a regular hexagonal atom arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in the lamination direction or the metal atoms and the oxygen atoms are arranged in a lamination manner.

CAAC is not a single crystal, but this does not mean that CAAC consists only of amorphous components. Although CAAC includes a crystalline portion (crystalline portion), in some cases, the boundary between one crystalline portion and another crystalline portion is not clear.

In the case where oxygen is contained in CAAC, nitrogen may replace part of the oxygen contained in CAAC. The c-axis of the individual crystal parts included in the CAAC may be aligned in a direction (for example, a direction perpendicular to the surface of the substrate on which the CAAC is formed or the surface of the CAAC). Alternatively, the normals of the a-b planes of the individual crystal parts included in the CAAC may be aligned in one direction (for example, perpendicular to the direction of the substrate surface on which the CAAC is formed or the surface of the CAAC).

CAAC becomes a conductor, semiconductor, or insulator depending on its composition and the like. CAAC transmits or does not transmit visible light depending on its composition and the like.

Regarding this embodiment of the CAAC, there are crystals formed into a film shape and viewed as having a triangular or hexagonal atom configuration when viewed from a direction perpendicular to the surface of the film or the surface of the supporting substrate, wherein, when observing the cross section of the film, the metal atoms are stacked The metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a stacked manner.

An embodiment of the crystal structure of CAAC will be described in detail with reference to FIGS. 24A to 24E, FIGS. 25A to 25C, and FIGS. 26A to 26C. In FIGS. 24A to 24E, FIGS. 25A to 25C, and FIGS. 26A to 26C, unless otherwise specified, the vertical direction corresponds to the c-axis direction and the plane perpendicular to the c-axis direction corresponds to the a-b plane. When simply using "upper half" and "lower half", they mean the upper half above the ab plane and the lower half below the ab plane (relative to the upper and lower halves of the ab plane) unit).

FIG. 24A shows a structure including one six-coordinate In atom and six four-coordinate oxygen (hereinafter referred to as four-coordinate O) atoms close to the In atom. Here, a structure containing a metal atom and an oxygen atom close to it is called a small group. The structure in FIG. 24A is truly an octahedral structure, but is shown as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in the upper and lower halves in FIG. 24A. In the small group shown in FIG. 24A, the charge is zero.

FIG. 24B shows a three-configuration oxygen atom including a five-coordinate Ga atom, close to Ga atom (hereinafter referred to as three-coordinate O), and close to Ga The structure of two four-coordinate O atoms of an atom. All three coordinated O atoms exist on the a-b plane. A four-coordinate O atom exists in the upper and lower halves of FIG. 24B. Since the In atom has five ligands, the In atom also has the structure shown in FIG. 24B. In the small group shown in FIG. 24B, the charge is zero.

FIG. 24C shows four tetracoordinate O atoms including one tetracoordinate Zn atom and close to the Zn atom. In FIG. 24C, one four-coordinate O atom exists in the upper half, and three four-coordinate O atoms exist in the lower half. Alternatively, in FIG. 24C, three tetracoordinate O atoms are present in the upper half and one tetracoordinate O atom is present in the lower half. In the small group shown in FIG. 24C, the charge is zero.

FIG. 24D shows a six-coordinate Sn atom and six four-coordinate O atoms close to the Sn atom. In FIG. 24D, three tetracoordinate O atoms exist in the upper half and the lower half. In the small group shown in FIG. 24D, the charge is +1.

Figure 24E shows a small group containing two Zn atoms. In FIG. 24E, a four-coordinate O atom exists in the upper and lower halves. In the small group shown in Figure 24E, the charge is -1.

Here, many small groups form medium groups, and many medium groups form large groups (also called single cells).

Now, the bonding rules between the small groups will be explained. With respect to the three O atoms in the upper half of the six-coordinated In atom in FIG. 24A, each has three close In atoms in the downward direction, and the three O atoms in the lower half are all in the upward direction. There are three close In atoms. Relative to One O atom in the upper half of the five-coordinated Ga atom has one approaching Ga atom in the downward direction, and one atom in the lower half has one approaching Ga atom in the upward direction. Relative to one O atom in the upper half of the tetracoordinated Zn precursor, there is one approaching Zn atom in the downward direction, and the three O atoms in the lower half each have three approaching Zn atoms in the upward direction . In this way, the number of tetracoordinated O atoms above the metal atoms is equal to the number of metal atoms close to and below each tetracoordinated O atom. Similarly, the number of tetracoordinated O atoms below the metal atoms is equal to the number of metal atoms close to and above each tetracoordinated O atom. Since the number of axes of the four-coordinated O atoms is 4, the total number of metal atoms close to the O atom and below the O atom and the number of metal atoms close to the O atom and above the O atom is 4. Therefore, when the sum of the number of four-coordinate O atoms above a metal atom and the number of four-coordinate O atoms below another metal atom is 4, two small groups containing metal atoms can be joined. For example, in the case where six coordination metal (In or Sn) atoms are joined via three four coordination O atoms in the lower half, it is joined to a five coordination metal (Ga or In) or a four coordination metal (Zn) atoms.

A metal atom having an axis number of 4, 5, or 6 is bonded to another metal via the tetracoordinate O in the c-axis direction. In addition to the above, it is also possible to form medium groups in different ways by combining many small groups so that the total charge of the stacked structure is 0.

FIG. 25A shows a model of medium groups contained in a stack structure of In-Sn-Zn-O-based materials. Figure 25B shows a large group containing three groups group. Note that FIG. 25C shows the atomic configuration in the case of the stacked structure in FIG. 25B viewed from the c-axis direction.

In FIG. 25A, the tri-coordinate O atoms are omitted for simplicity, and the tetra-coordinate O atoms are shown in circles; the number of circles shows the number of tetra-coordinate O atoms. For example, the three tricoordinate O atoms present in the upper and lower halves with respect to Sn atoms are indicated by circle 3. Similarly, in FIG. 25A, a four-coordinate O atom present in the upper half and the lower half relative to the In atom is indicated by a circle 1. FIG. 25A also shows a Zn atom near a four-coordinate O atom in the lower half and three four-coordinate O atoms in the upper half, and a four-coordinate O atom in the upper half and the lower half The three four-coordinate O atoms in.

In the layered structure of the In-Sn-Zn-O-based material included in FIG. 25A, the Sn atoms that are close to the three tetracoordinate O atoms in the upper half and the lower half are joined in order from the top In atoms and In atoms that are close to one four-coordinate O atom in the upper and lower halves are joined to Zn atoms and Zn atoms that are close to the three four-coordinate O atoms in the upper half. One four-coordinate O atom in the lower half is bonded to the In atom near the upper half and three four-coordinate O atoms in the lower half, and the In atom is bonded to one containing the Zn atom and close to one of the upper half A small group of tetracoordinate O atoms, and the small group is joined to three tetracoordinates close to the upper half and the lower half via one tetracoordinate O atom in the lower half of the small group Sn atom at position O atom. Many of these small groups are joined so that large groups are formed.

Here, the charge of one bond of the three coordination O atom and the original of the four coordination O The charge of the one bond of the sub is assumed to be -0.667 and -0.5, respectively. For example, the charge of (hexa-coordinated or penta-coordinated) In atoms, the charge of (quad-coordinated) Zn atoms, and the charge of (pentad-or six-coordinated) Sn atoms are +3, +2, And +4. Therefore, the charge in the small group containing Sn atoms is +1. Therefore, it is necessary to cancel the +1 charge of -1 to form a stacked structure containing Sn atoms. Regarding the structure having a charge of -1, it may be a small group containing two Zn atoms as shown in FIG. 24E. For example, by a small group containing two Zn atoms, the charge of a small group containing Sn atoms can be cancelled, so that the total charge of the stacked structure is zero.

When the large group shown in FIG. 25B is repeated, an In-Sn-Zn-O-based crystal (In ₂ SnZn ₃ O ₈ ) is obtained. Note that the obtained In-Sn-Zn-O-based crystal lamination structure is expressed as the composition formula In ₂ SnZn ₂ O ₇ (ZnO) _m (m is 0 or a natural number).

The above rules also apply to the following oxides: for example In-Sn-Ga-Zn-based four-component metal oxides; for example In-Ga-Zn-based oxides (also known as IGZO), In-Al-Zn Based oxides, Sn-Ga-Zn based oxides, Al-Ga-Zn based oxides, Sn-Al-Zn based oxides, In-Hf-Zn based oxides, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn Basic oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In -Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based Oxides, or three-component metal oxides such as In-Lu-Zn-based oxides; for example, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn -Two-component metal oxides such as Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, or In-Ga-based oxides; etc.

For example, FIG. 26A shows a model of medium groups included in a stack structure of In-Ga-Zn-O-based materials.

In the middle group included in the stacked structure of the In-Ga-Zn-O-based material in FIG. 26A, the four tetracoordinate O atoms in the upper half and the lower half are sequentially approached from the top The In atom is bonded to a Zn atom near a four-coordinate O atom in the upper half, and the Zn atom is bonded to the upper half and the lower half via three four-coordinate O atoms in the lower half relative to the Zn atom. The Ga atom and Ga atom of one tetracoordinate O atom in the half are joined to the three tetracoordinates close to the upper half and the lower half via one tetracoordinate O atom in the lower half of the Ga atom In atom of O atom. Many of these groups are joined, so that large groups are formed.

Figure 26B shows a large group containing three medium groups. Note that FIG. 26C shows the atomic configuration in the case of the stacked structure in FIG. 26B viewed from the c-axis direction.

Here, since the charge of the (six-coordinate or five-coordinate) In atom, the charge of the (four-coordinate) Zn atom, and the charge of the (five-coordinate) Ga atom are +3, +2, and +3, respectively, including The charge of a small group of any of In atoms, Zn atoms, and Ga atoms is zero. As a result, the total charge of the group in the combination with these small groups is always zero.

In order to form a layered structure of In-Ga-Zn-O-based materials, not only the middle group shown in FIG. 26A but also the arrangement of In atoms, Zn atoms, and Ga atoms may be different from that in FIG. 26A To form large groups.

In addition, the oxide based on In-Sn-Zn is called ITZO, and an oxide target having the following composition ratio is used: For example, the composition ratio of In:Sn:Zn is 1:2:2, 2: Atom ratio of 1:3, 1:1:1 or 20:45:35.

In the case where the In-Zn-O-based material is used for an oxide semiconductor, an oxide target with the following composition ratio is used: In:Zn composition ratio is 50:1 to 1:2 atomic ratio (In ₂ O ₃ : ZnO=25:1 to 1:4 molar ratio), preferably 20:1 to 1:1 atomic ratio (In ₂ O ₃ :ZnO=10:1 to 1:2 molar ratio), better The ground is 15:1 to 1.5:1 atomic ratio (In ₂ O ₃ :ZnO=15:2 to 3:4 molar ratio). For example, the target used to form an In-Zn-O-based oxide semiconductor has the following atomic ratio: In:Zn:O atomic ratio is X:Y:Z, where Z>1.5X+ Y.

The thickness of the oxide semiconductor layer is preferably greater than or equal to 3 nm and less than or equal to 30 nm. This is because when the oxide semiconductor layer is too thick (for example, the thickness is 50 nm or more), the transistor may be normally open.

The oxide semiconductor layer is preferably formed in such a way that impurities such as hydrogen, water, hydroxyl, and hydride do not enter the oxide semiconductor layer. For example, the sputtering method is used.

In this embodiment, an oxide semiconductor layer is formed by a sputtering method using an oxide target based on In-Ga-Zn-O.

Regarding the oxide target based on In-Ga-Zn-O, for example, an oxide target having the following components is used: the composition ratio of In ₂ O ₃ , Ga ₂ O ₃ and ZnO is 1:1:1[ Morbi]. Alternatively, it is not necessary to limit the material and composition ratio of the target to the above. For example, an oxide target having the following composition ratio is used: In ₂ O ₃ , Ga ₂ O _3, and ZnO have a composition ratio of 1:1:2 [molar ratio].

The filling rate of the oxide target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. This is because a dense oxide semiconductor layer can be formed by using an oxide target with a high filling rate.

The deposition gas may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. In addition, in order to prevent hydrogen, water, hydroxyl, hydride, etc. from entering the oxide semiconductor layer, it is preferable to use an atmosphere of a high-purity gas in which impurities such as hydrogen, water, hydroxyl, and hydride are sufficiently removed.

For example, the oxide semiconductor layer is formed as described below.

First, the substrate is placed in a deposition chamber where the pressure is reduced and heating is performed so that the substrate temperature is higher than 200°C and lower than or equal to 500°C, preferably higher than 300°C and lower than or equal to 500°C, more preferably Ground is higher than or equal to 350 ℃ and lower than or equal to 450 ℃.

Then, a high-purity gas in which impurities such as hydrogen, water, hydroxyl, and hydride are sufficiently removed is introduced into the deposition chamber where the remaining moisture is being removed, and, by using a target, on the substrate An oxide semiconductor layer is formed. In order to remove the moisture remaining in the sedimentation chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, ion pump, or titanium sublimation pump. In addition, the vacuum pumping mechanism may be a turbo pump provided with a cold trap. In the deposition by vacuum pumping In the chamber, impurities such as hydrogen, water, hydroxyl, hydride (more preferably, compounds containing carbon atoms) are removed, thereby reducing the hydrogen oxide, water, hydroxyl, etc. in the oxide semiconductor layer formed in the deposition chamber And the concentration of impurities such as hydride.

When the substrate temperature is low during deposition (for example, less than or equal to 100° C.), a substance containing hydrogen atoms may enter the oxide semiconductor layer; therefore, the substrate is preferably heated to the above temperature. When the oxide semiconductor layer is formed at the substrate heated at the above temperature, the substrate temperature increases; therefore, hydrogen bonds are cut off due to heat and are less likely to be taken into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed with the substrate heated at the above temperature, and the concentration of impurities such as hydrogen, water, hydroxyl groups, and hydride in the oxide semiconductor layer is sufficiently reduced. In addition, the damage caused by sputtering is reduced.

Examples of deposition conditions are as follows: the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the substrate temperature is 400° C., and the deposition atmosphere is an oxygen atmosphere (oxygen flow rate is 100%) Atmosphere. Note that since a pulsed direct current (DC) power supply can reduce powder materials (also called particles or dust) and uniform film thickness during deposition, it is preferable to use a pulsed direct current (DC) power supply.

Note that before the oxide semiconductor layer is formed by sputtering, it is preferable to remove the material adhering to the surface (for example, particles or dust) formed on the oxide semiconductor layer to be formed by reverse sputtering In reverse sputtering, argon gas is introduced into the powder material and plasma is generated. Reverse sputtering is a method in which a voltage is applied to the substrate side to generate plasma in the vicinity of the substrate to modify the surface. Note that a gas such as nitrogen, helium, or oxygen may be used instead of argon.

After forming a mask having a desired shape on the oxide semiconductor layer, the oxide semiconductor layer is processed by etching. The photoresist mask is formed by a method such as lithography or inkjet method. In order to etch the oxide semiconductor, wet etching or dry etching may be used. Needless to say, you can use a combination of them.

Thereafter, the oxide semiconductor layer 144 is subjected to heat treatment (first heat treatment). Through heat treatment, the amount of hydrogen atoms in the oxide semiconductor layer 144 is further reduced. The heat treatment is performed in an inert gas atmosphere at a temperature equal to or higher than 250°C and lower than or equal to 700°C, preferably higher than or equal to 400°C and lower than or equal to 600°C or the strain point of the substrate. Regarding the inert gas atmosphere, an atmosphere containing nitrogen or a rare gas (such as helium, neon, or argon) as a main component and not containing water, hydrogen, etc. is preferably used. For example, the purity of nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment equipment is greater than or equal to 6N (99.9999%), preferably greater than or equal to 7N (99.99999%) (that is, the impurity concentration Less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).

For example, heat treatment is performed in the following manner: the object to be heat-treated is introduced into an electric furnace using a resistance heating element or the like, and then heated at 450° C. for one hour in a nitrogen atmosphere. During the heat treatment, the oxide semiconductor layer 144 is not exposed to air, so that impurities such as water and hydrogen are prevented from entering.

The above heat treatment is referred to as dehydration treatment or dehydrogenation treatment, etc. due to its advantageous effect of removing hydrogen, water, etc. For example, the heat treatment may be performed at an equal timing before the oxide semiconductor layer is processed to have an island shape or after the insulating film is formed. This dehydration treatment or dehydrogenation treatment can be executed One or more times.

Next, a conductor layer (including wiring formed in the same layer as the source electrode and the drain electrode) for forming the source electrode and the drain electrode is formed on the oxide semiconductor layer 144 and the like, and the processing is performed Conductor layer, so that source and drain electrodes 142a and 142b are formed (see FIG. 19B).

The conductor layer is formed by the PVD method or the CVD method. Regarding the material for the conductor layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of the foregoing elements as components; or the like can be used. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium, neodymium, and scandium may be used.

The conductor layer may have a single-layer structure or a stacked structure including two or more layers. For example, the conductor layer has a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a double-layer structure where a titanium film is stacked on the aluminum film, and a titanium film is stacked on the titanium nitride film The two-layer structure, or the three-layer structure in which titanium film, aluminum film, and titanium film are sequentially stacked. Note that the conductor layer having a single-layer structure of a titanium film or a titanium nitride film has an advantage that the source electrode 142a and the drain electrode 142b can be easily processed into a push-out shape.

Alternatively, a conductive metal oxide is used to form a conductive layer. Examples of conductive metal oxides are indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), an alloy of indium oxide and tin oxide (In ₂ O ₃ -SnO ₂ , sometimes called ITO), an alloy of indium oxide and zinc oxide (In ₂ O ₃ -ZnO), and this metal oxide material containing silicon or silicon oxide.

The conductor layer is preferably etched into the formed source electrode 142a and drain The end of the electrode 142b is pushed. Here, for example, it is preferable that the pushing angle is greater than or equal to 30° and less than or equal to 60°. When etching is performed so that the ends of the source electrode 142a and the drain electrode 142b are pushed out, the coverage of the gate insulating film 146 formed later is improved and prevented from breaking.

The channel length (L) of the transistor in the upper part is determined by the distance between the lower edge of the source electrode 142a and the lower edge of the drain electrode 142b. Note that in the exposure of a mask used in the case of forming a transistor with a channel length (L) shorter than 25 nm, it is preferable to use extreme ultraviolet light with a wavelength as short as several nanometers to several tens of nanometers. In exposure using extreme ultraviolet light, the resolution is high and the depth of focus is large. Therefore, the channel length (L) of the transistor formed later is in the range of greater than or equal to 10 nm and less than or equal to 1000 nm (1 μm), and therefore, the operation speed of the circuit can be increased. In addition, miniaturization can reduce power consumption of the semiconductor device.

Next, a gate insulating film 146 in contact with a part of the oxide semiconductor layer 144 is formed to cover the source and drain electrodes 142a and 142b (see FIG. 19C).

The gate insulating film 146 is formed by CVD method, sputtering method, or the like. The gate insulating film 146 preferably contains silicon oxide, silicon nitride, gallium oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x>0, y>0)), Hafnium silicate with added nitrogen (HfSi _x O _y N _z (x>0, y>0, z>0)), hafnium aluminate with added nitrogen (HfAl _x O _y N _z (x>0, y>0, z>0)), etc. The gate insulating film 146 may have a single-layer structure or a stacked structure using any of the above materials. The thickness is not particularly limited; however, in the case of miniaturization of the semiconductor device, the thickness is preferably thin in order to ensure the operation of the transistor. For example, in the case of using silicon oxide, the thickness may be set to be greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 10 nm and less than or equal to 50 nm.

When the gate insulating film is formed to be generally thin as described above, gate leakage due to tunneling effect or the like becomes a problem. In order to solve the problem of gate leakage, for example, hafnium nitride, tantalum oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x>0, y>0)), and nitrogen-added hafnium silicate (HfSi _x O _y N _z (x>0, y>0, z>0)), or nitrogen-added hafnium aluminate (HfAl _x O _y N _z (x>0, y>0, z>0)) and other high dielectric constants ( High-k) material to form the gate insulating film 146. Using a high-k material for the gate insulating film 146 can increase the thickness to suppress gate leakage and ensure electrical characteristics. Note that the laminated structure of a film containing a high-k material and a film containing silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, etc.

In addition, the insulating layer contacting the oxide semiconductor layer 144 (in this embodiment, the gate insulating film 146) may be an insulating material containing a group 13 element and oxygen. Many of the oxide semiconductor materials contain group 13 elements, and insulating materials containing group 13 elements work well with oxide semiconductors. Using an insulating material containing a group 13 element for contacting the insulating layer of the oxide semiconductor, the interface with the oxide semiconductor layer can be kept favorable.

An insulating material containing a group 13 element means an insulating material containing one or more group 13 elements. As for the insulating material containing the Group 13 element, it may be gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, and so on. Here, The aluminum gallium oxide contains gallium and aluminum, so that the aluminum content is higher than the gallium content in atomic percentage, and the gallium aluminum oxide contains gallium and aluminum, so that the gallium content is higher than the aluminum content in atomic percentage.

For example, in the case of forming a gate insulating film contacting an oxide semiconductor layer containing gallium, when a material containing gallium oxide is used for the gate insulating film, the interface between the oxide semiconductor layer and the gate insulating film Maintain favorable characteristics. When the oxide semiconductor layer and the insulating layer containing gallium oxide are disposed in contact with each other, the accumulation of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. Note that in the case where an element belonging to the same group as the constituent element of the oxide semiconductor is used for the insulating layer, a similar effect is obtained. For example, it is effective to form an insulating layer by using a material containing oxide. Note that water is less permeable to alumina. Therefore, from the viewpoint of preventing water from entering the oxide semiconductor layer, it is preferable to use a material containing aluminum oxide.

By heat treatment or oxygen doping in an oxygen atmosphere, the insulating material of the insulating layer in contact with the oxide semiconductor layer 144 preferably contains oxygen in a ratio higher than that in the stoichiometric composition. "Oxygen doping" means adding oxygen to the bulk. Note that the term "bulk" is used to make it clear that oxygen is added not only to the surface of the film but also to the inside of the film. In addition, "oxygen doping" includes "oxygen plasma doping", in which oxygen in the form of plasma is added to the bulk. Oxygen doping is performed by ion implantation method or ion doping method.

For example, in the case of using gallium oxide to form an insulating layer contacting the oxide semiconductor layer 144, by heat treatment or oxygen doping in an oxygen atmosphere, the composition of gallium oxide is set to Ga ₂ O _x (x= 3+α, 0<α<1). In the case of using aluminum oxide to form an insulating layer in contact with the oxide semiconductor layer 144, the composition of aluminum oxide is set to Al ₂ O _x (x=3+α, by heat treatment or oxygen doping in an oxygen atmosphere) 0<α<1). In the case of using gallium aluminum oxide to form an insulating film contacting the oxide semiconductor layer 144, the composition of the gallium aluminum oxide is set to Ga ₂ Al _2-x O by heat treatment in an oxygen atmosphere or oxygen doping _3+α (0<x<2, 0<α<1).

By oxygen doping or the like, an insulating layer is formed, the insulating layer including a region where the oxygen ratio is higher than that in the stoichiometric composition. When the insulating layer including this region contacts the oxide semiconductor layer, excess oxygen present in the insulating layer is supplied to the oxide semiconductor layer, and the dehydrated or dehydrogenated oxide semiconductor layer or the oxide semiconductor layer The lack of oxygen at the interface with the insulating layer can be reduced. Therefore, the oxide semiconductor layer is an i-type or substantially i-type oxide semiconductor.

An insulating layer including a region having an oxygen ratio higher than that in the stoichiometric composition can be applied to the insulating layer forming the base film of the oxide semiconductor layer 144 instead of the gate insulating film 146 or the gate insulating film 146 and Two films such as base insulating film.

After forming the gate insulating film 146, the second heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is higher than or equal to 200°C and lower than or equal to 450°C, preferably higher than or equal to 250°C and lower than or equal to 350°C. For example, heat treatment is performed at 250°C for one hour in a nitrogen atmosphere. By performing the second heat treatment, the electrical characteristic variation of the transistor can be reduced. In addition, in the case where the gate insulating film 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 144 which has undergone dehydration or dehydrogenation to fill the oxidation The oxygen in the semiconductor layer 144 is depleted, so that an oxide semiconductor layer of i-type (essential) or substantially i-type is formed.

In the present embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed; however, the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the gate electrode is formed. Alternatively, the first heat treatment and the second heat treatment are continuously performed, the first heat treatment may be used as the second heat treatment, or the second heat treatment may also be used as the first heat treatment.

Next, a conductor layer for the gate electrode (including the wiring formed in the same layer as the gate electrode) is formed and processed so that the gate electrode 148a and the conductor layer 148b are formed (see FIG. 19D).

The gate electrode 148a and the conductor layer 148b are formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component. Note that the gate electrode 148a and the conductor layer 148b may have a single-layer structure or a stacked-layer structure.

Next, an insulating layer 150 is formed on the gate insulating film 146, the gate electrode 148a, and the conductor layer 148b (see FIG. 20A). The insulating layer 150 is formed by a PVD method, a CVD method, or the like. The insulating layer 150 is formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that a material with a low dielectric constant or a structure with a low dielectric constant (for example, a porous structure) is preferably used for the insulating layer 150. This is because by lowering the dielectric constant of the insulating layer 150, the capacitance between wiring, electrodes, etc. can be reduced, resulting in an increase in operation speed. Note that although the insulating layer 150 has a single-layer structure in this embodiment, an embodiment of the present invention is not limited to this. Insulation 150 may have a stacked structure including two or more layers.

Next, an opening reaching the source electrode 142a is formed in the gate insulating layer 146 and the insulating layer 150. Then, a wiring 154 contacting the source electrode 142a is formed on the insulating layer 150 (see FIG. 20B). Using a mask or the like, the opening is formed by selective etching.

The conductor layer is formed by the PVD method or the CVD method, and then patterned so that the wiring 154 is formed. Regarding the material used for the conductor layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of the above elements as components; and the like are used. In addition, one or more materials selected from manganese, magnesium, zirconium, beryllium, neodymium, and scandium may be used.

Specifically, for example, a method can be adopted in which a thin titanium film (about 5 nm) is formed by a PVD method in a part of the insulating layer 150 in which the opening is formed, and then, an aluminum film is formed so as to be embedded in the opening . Here, the titanium film formed by the PVD method has a function of reducing the oxide film (for example, a natural oxide film) on the surface on which the titanium film is formed, and reducing the contact resistance with the lower electrode (here, the source electrode) Electrode 142a). In addition, prevent the hillocks of the aluminum film. After forming a barrier film of titanium, titanium nitride, or the like, a copper film is formed by an electroplating method.

An opening is preferably formed in the insulating layer 150 so as to overlap the conductor layer 128b. When the opening is formed in this way, it is possible to prevent the element area from increasing due to the contact area.

Here, a case where the position where the impurity region 126 and the source electrode 142a are connected to each other and the position where the source electrode 142a and the wiring 154 are connected to each other overlap without using the conductor layer 128b will be described. In this case, the shape An opening (also referred to as a contact in the lower part) is formed in the insulating layer 136, the insulating layer 138, and the insulating layer 140 formed on the impurity region 126, and the source electrode 142a is formed in the contact in the lower part. After that, openings (also referred to as contacts in the upper part) are formed in the gate insulating film 146 and the insulating layer 150 so as to overlap the contacts in the lower part, and then, the wiring 154 is formed. When the contact in the upper portion is formed to overlap the contact in the lower portion, the source electrode 142a in the contact formed in the lower portion may be disconnected due to etching. When the contact in the lower part and the upper part is formed so as not to overlap each other to avoid disconnection, a problem that the element area increases may occur.

As described in this embodiment, by using the conductor layer 128b, a contact in the upper portion is formed without disconnecting the source electrode 142a. Therefore, the contacts in the lower portion and the upper portion are formed to overlap each other, so that the element area can be prevented from increasing due to the contact area. In other words, the integration of the semiconductor device is increased.

Next, the insulating layer 156 is formed to cover the wiring 154 (see FIG. 20C).

Through the above process, the transistor 162 and the capacitor 164 including the highly purified oxide semiconductor layer 144 are completed (see FIG. 20C).

Note that the oxide conductor layer as the source and drain regions may be provided between the oxide semiconductor layer 144 and the source and drain electrodes 142a and 142b as a buffer layer in the transistor 162. 22A and 22B show transistors 162A and 162B, respectively. Both transistors 162A and 162B are obtained by providing an oxide conductor layer in the transistor 162 in FIG. 15A.

The transistors 162A and 162B in FIGS. 22A and 22B are provided with oxide conductor layers 404a and 404b as the oxide semiconductor layer 144 and the source Source and drain regions between the pole and drain electrodes 142a and 142b. The transistors 162A and 162B in FIGS. 22A and 22B differ from each other in the shape of the oxide conductor layers 404a and 404b depending on the process.

In the transistor 162A in FIG. 22A, an oxide semiconductor film and an oxide conductor film are formed, and the oxide semiconductor film and the oxide conductor film are processed through the same lithography process so that the oxide semiconductor layer 144 and the oxide The conductor film is formed to have an island shape. After the source electrode 142a and the drain electrode 142b are formed on the oxide semiconductor layer and the oxide conductor film, the source electrode 142a and the drain electrode 142b are used as masks to etch the oxide conductor film having an island shape, so that The oxide conductor layers 404a and 404b to be the source and drain regions are formed.

In the transistor 162B in FIG. 22B, an oxide conductor film is formed on the oxide semiconductor layer 144, a metal conductor film is formed thereon, and then the oxide conductor film and the metal conductor film are processed through the same lithography process, As a result, oxide conductor layers 404a and 404b, source electrodes 142a, and drain electrodes 142b to become source and drain regions are formed.

When performing etching to process the oxide conductor film, the etching conditions (type and concentration of etching material, etching time, etc.) are appropriately adjusted so that the oxide semiconductor layer will not be over-etched.

Regarding the formation method of the oxide conductor layers 404a and 404b, a sputtering method, a vacuum evaporation method (electron beam evaporation method, etc.), an arc discharge ion plating method, or a sputtering method is used. Regarding the materials of the oxide conductor layers 404a and 404b, a compound of silicon oxide and indium tin oxide, zinc aluminum oxide, zinc aluminum oxynitride, gallium zinc oxide, or the like is used. In addition, the above materials can To contain silicon oxide.

When the oxide conductor layer is provided as the source and drain regions between the oxide semiconductor layer 144 and the source and drain electrodes 142a and 142b, the resistance of the source and drain regions can be reduced, resulting in transistors 162A and 162B High-speed operation.

Including the oxide semiconductor layer 144, the oxide conductor layers 404a and 404b, and the source and drain electrodes 142a and 142b, the transistors 162A and 162B can each have a higher withstand voltage.

Since the oxide semiconductor layer 144 is highly purified in the transistor 162 described in this embodiment, the hydrogen concentration is 5×10 ¹⁹ atoms/cm ³ or less, preferably 5×10 ¹⁸ atoms/cm ³ Or lower, more preferably 5×10 ¹⁷ atoms/cm ³ or lower. In addition, the carrier concentration of the oxide semiconductor layer 144 is sufficiently lower than that of a general silicon wafer (about 1×10 ¹⁴ /cm ³ ) (for example, less than 1×10 ¹² /cm ³ , preferably lower than 1.45×10 ¹⁰ /cm ³ ). Therefore, the off-state current is also sufficiently low. For example, at room temperature (25°C), the off-state current of the transistor 162 (here, the current per micrometer (μm) of the channel width) is less than or equal to 100zA (1zA (Media Ampere) is 1×10 ^{− 21} A), preferably lower than or equal to 10zA.

By using the highly purified oxide semiconductor layer 144, the off-state current of the transistor can be reduced sufficiently. In addition, by using this transistor, a semiconductor device capable of holding stored data for a long time is obtained.

In addition, in the semiconductor device described in this embodiment, the wiring is shared; therefore, a semiconductor device having a sufficiently increased degree of integration is realized.

The structures, methods, etc. described in this embodiment can be combined with any structures, methods, etc. described in other embodiments as appropriate.

(Example 4)

In this embodiment, a case where any of the semiconductor devices described in the above embodiments is applied to an electronic device will be described with reference to FIGS. 21A to 21F. In this embodiment, the semiconductor devices described in the above embodiments will be applied to, for example, computers, mobile phones (also called mobile phones or mobile phone devices), portable information terminals (including portable game consoles, Audio players, etc.), cameras such as digital cameras or digital video cameras, electronic paper, or televisions (also called televisions or television receivers).

FIG. 21A shows a laptop personal computer including a case 707, a case 708, a display portion 709, a keyboard 710, and so on. At least one of the housing 707 and the housing 708 is provided with any of the semiconductor devices described in the above embodiments. Therefore, it is possible to realize a laptop personal computer that performs writing and reading of data at high speed, storing data for a long time, and sufficiently reducing power consumption.

Figure 21B shows a personal digital assistant (PDA). The main body 711 is provided with a display portion 713, an external interface 715, operation keys 714, and so on. In addition, a probe 712 and the like are provided for operating the personal digital assistant. In the main body 711, the semiconductor device described in any of the above embodiments is provided. Therefore, it is possible to realize a personal digital assistant that performs writing and reading of data at high speed, storing data for a long time, and sufficiently reducing power consumption.

FIG. 21C shows an e-book reader 720 containing electronic paper. The e-book reader 720 includes two casings: a casing 721 and a casing 723. Chassis 721 A display portion 725 and a display portion 727 are provided in the housing 723, respectively. The casing 721 and the casing 723 are joined by a hinge 737 and opened and closed with the hinge 737 as an axis. The cabinet 721 is provided with a power source 731, operation keys 733, a speaker 735, and so on. At least one of the housing 721 and the housing 723 is provided with any of the semiconductor devices described in the above embodiments. Therefore, an e-book reader capable of performing writing and reading of data at high speed, storing data for a long time, and sufficiently reducing power consumption can be realized.

FIG. 21D shows a mobile phone handset, which includes two casings: casing 740 and casing 741. In addition, the housing 740 and the housing 741 in the expanded state as shown in FIG. 21D can overlap each other by sliding; therefore, the size of the mobile phone handset can be reduced, making the mobile phone handset suitable for carrying. The casing 741 includes a display panel 742, a speaker 743, a microphone 744, operation keys 745, an index device 746, a camera lens 747, an external connection terminal 748, and so on. The case 740 contains a solar battery 749 for charging the mobile phone, an external memory slot 750, and so on. In addition, the antenna is incorporated in the housing 741. At least one of the casing 740 and the casing 741 is provided with any of the semiconductor devices described in the above embodiments. Therefore, it is possible to realize a mobile phone handset that performs data writing and reading at high speed, stores data for a long time, and sufficiently reduces power consumption.

21E is a digital camera including a main body 761, a display portion 767, an eyepiece 763, an operation switch 764, a display portion 765, a battery 766, and so on. In the main body 761, any semiconductor device described in the above embodiments is provided. Therefore, it is possible to realize a digital camera that performs data writing and reading at high speed, stores data for a long time, and sufficiently reduces power consumption.

FIG. 21F is a television 770 including a cabinet 771, a display portion 773, a stand 775, and so on. The television 770 is operated by the operation switch of the cabinet 771 or the remote controller 780. The semiconductor device described in any of the above embodiments is provided in the casing 771 and/or the remote controller 780. Therefore, it is possible to realize a television that performs writing and reading of data at high speed, storing data for a long time, and sufficiently reducing power consumption.

Therefore, the semiconductor device according to any of the above embodiments is provided in the electronic device described in this embodiment. Therefore, the power consumption of the electronic device can be reduced.

(Example 5)

An embodiment of the oxide semiconductor layer which is any semiconductor layer of the transistor 162 in the above-described embodiment will be described with reference to FIGS. 23A to 23C.

The oxide semiconductor layer of this embodiment has a structure including a first crystalline oxide semiconductor layer and a second crystalline oxide semiconductor layer. The second crystalline oxide semiconductor layer is stacked on the first crystalline oxide semiconductor layer and has a larger size than the first The thickness of the crystalline oxide semiconductor layer.

The insulating layer 437 is formed on the insulating layer 401. In this embodiment, an oxide insulating layer with a thickness greater than or equal to 50 nm and less than or equal to 600 nm is formed by the PCVD method or the sputtering method. For example, a single layer selected from a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon oxynitride film, an aluminum oxynitride film, and a silicon oxynitride film or a stack of any of these films is used.

Next, a first oxide semiconductor film with a thickness greater than or equal to 1 nm and less than or equal to 10 nm is formed on the insulating layer 437, and the sputtering The substrate temperature in the film formation of the method is set to be higher than or equal to 200°C and lower than or equal to 400°C.

In this embodiment, in an oxygen atmosphere, an argon atmosphere, or an atmosphere containing argon and oxygen, a first oxide semiconductor film with a thickness of 5 nm is formed under the following conditions: using a target for an oxide semiconductor (for containing 1 : 1: 2 [mole ratio] In ₂ O ₃ , Ga ₂ O ₃ , and ZnO In-Ga-Zn-O-based oxide semiconductor target), the distance between the substrate and the target is 170mm, The substrate temperature is 400°C, the pressure is 0.4 Pa, and the direct current (DC) power is 0.5 kW.

In the case where an In-Zn-O-based material is used for an oxide semiconductor, a target having the following composition ratio is used: In:Zn has a composition ratio of 50:1 to 1:2 atomic ratio (In ₂ O ₃ : ZnO=25:1 to 1:4 molar ratio), preferably 20:1 to 1:1 atomic ratio (In ₂ O ₃ :ZnO=10:1 to 1:2 molar ratio), more preferably It is an atomic ratio of 15:1 to 1.5:1 (In ₂ O ₃ :ZnO=15:2 to 3:4 molar ratio). For example, the target used to form an In-Zn-O-based oxide semiconductor has the following atomic ratio: In:Zn:O atomic ratio is X:Y:Z, where Z>1.5X+ Y.

In addition, the oxide based on In-Sn-Zn is called ITZO, and an oxide target having the following composition ratio is used as the target: For example, the composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or 20:45:35 atomic ratio.

Next, the first heat treatment is performed under the condition that the atmosphere of the chamber where the substrate is provided is a nitrogen or dry air atmosphere. The temperature of the first heat treatment is higher than or equal to 400°C and lower than or equal to 750°C. Through the first heat treatment, a first crystalline oxide semiconductor layer 450a is formed (see FIG. 23A).

Depending on the substrate temperature at the time of deposition or the temperature of the first heat treatment, the first heat treatment causes crystallization from the film surface and crystal growth from the film surface toward the film interior; therefore, c-axis aligned crystals are obtained. Through the first heat treatment, a large amount of zinc and oxygen accumulate on the film surface, and one or more layers of two-dimensional graphite-type crystals containing zinc and oxygen and having a hexagonal upper plane are formed on the outermost surface; on the outermost surface The layers are grown in the thickness direction to form a stack of multiple layers. By increasing the temperature of the heat treatment, crystal growth proceeds from the surface to the interior, and from the interior to the bottom.

By the first heat treatment, oxygen in the insulating layer 437 (which is an oxide insulating layer) diffuses to the interface between the insulating layer 437 and the first crystalline oxide semiconductor layer 450a or near the interface (within ±5 nm from the interface) ), thus the oxygen deficiency in the first crystalline oxide semiconductor layer is reduced. Therefore, it is preferable to include the amount in the insulating layer 437 as the base insulating film (in the bulk) or the interface between the first crystalline oxide semiconductor layer 450a and the insulating layer 437 at least greater than the stoichiometric composition ratio The amount of oxygen in the oxygen.

Next, a second oxide semiconductor film with a thickness greater than 10 nm is formed on the first crystalline oxide semiconductor layer 450a. The second oxide semiconductor film is formed by a sputtering method, and the substrate temperature at the time of film formation is set to be higher than or equal to 200°C and lower than or equal to 400°C. By setting the substrate temperature during film formation to be higher than or equal to 200°C and lower than or equal to 400°C, a precursor can be arranged in the oxide semiconductor layer formed on and in contact with the surface of the first crystalline oxide semiconductor layer Things and get what is called a neat line.

In this embodiment, in an oxygen atmosphere, an argon atmosphere, or an atmosphere containing argon and oxygen, a second oxide semiconductor film with a thickness of 25 nm is formed under the following conditions: using a target for an oxide semiconductor (for containing 1 : 1: 2 [mole ratio] In ₂ O ₃ , Ga ₂ O ₃ , and ZnO In-Ga-Zn-O-based oxide semiconductor target), the distance between the substrate and the target is 170mm, The substrate temperature is 400°C, the pressure is 0.4 Pa, and the direct current (DC) power is 0.5 kW.

Next, the second heat treatment is performed under the condition that the atmosphere of the chamber where the substrate is provided is a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen. The temperature of the second heat treatment is higher than or equal to 400°C and lower than or equal to 750°C. Through the second heat treatment, a second crystalline oxide semiconductor layer 450b is formed (see FIG. 23B). In a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen, the second heat treatment is performed, thereby increasing the density of the second crystalline oxide semiconductor layer and reducing the number of defects therein. With the second heat treatment, crystal growth is performed in the thickness direction using the first crystalline oxide semiconductor layer 450a as a crystal nucleus, that is, crystal growth proceeds from the bottom to the inside; therefore, the second crystalline oxide semiconductor layer 450b is formed.

It is preferable that the steps from the formation of the insulating layer 437 to the second heat treatment are continuously performed without being exposed to air. The steps from the formation of the insulating layer 437 to the second heat treatment are preferably performed in an atmosphere controlled to contain a small amount of hydrogen and moisture (such as an inert gas atmosphere, a reduced pressure atmosphere, or a dry air atmosphere); from the viewpoint of moisture For example, for example, a dry nitrogen atmosphere having a dew point of -40°C or lower, preferably -50°C or lower may be used.

Next, the stack of the oxide semiconductor layer, the first crystalline oxide semiconductor layer 450a, and the second crystalline oxide semiconductor layer 450b is processed into a stacked oxide semiconductor layer including a plurality of island-shaped oxide semiconductor layers 453 (see Figure 23C). In the drawing, the interface between the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b is indicated by a dotted line, and the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b are shown as A stack of multiple oxide semiconductor layers; however, the interface is actually not obvious, but the interface is shown for easy understanding.

After forming a mask having a desired shape on the stack of the plurality of oxide semiconductor layers, the stack of the plurality of oxide semiconductor layers is processed by etching. The mask is formed by methods such as lithography. Alternatively, the mask is formed by a method such as an inkjet method.

In order to etch the stack of plural oxide semiconductor layers, dry etching or wet etching may be used. Needless to say, a combination of the two can be used.

The first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above-described forming method are characterized in that they have c-axis alignment. Note that the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer include oxides including crystals having c-axis alignment (also referred to as C-axis alignment crystals (CAAC)). The crystalline structure does not have an amorphous structure. The first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer partially include grain boundaries.

The oxide semiconductor to be used preferably contains at least indium (In) or zinc (Zn). In particular, it preferably contains indium (In) and zinc (Zn). Preferably, it also contains gallium (Ga) as a stabilizer for reducing changes in electrical characteristics of transistors including oxide semiconductors. It preferably contains tin (Sn) as a stabilizer. It is preferable to contain hafnium (Hf) as a stabilizer. Preferably containing aluminum (Al) as a stable Fixed object.

It may contain, for example, lanthanum (La), cerium (Ce), palladium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), ytterbium (Tb), dysprosium (Dy), 鈥( One or more lanthanoid elements such as Ho), erbium (Er), strontium (Tm), ytterbium (Yb), and lutetium (Lu) are used as another stabilizer.

For example, the following can be used as an oxide semiconductor: indium oxide, tin oxide, zinc oxide, for example, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Two-component metal oxides such as Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, or In-Ga-based oxides, such as In-Ga-Zn Basic oxides (also called IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn Basic oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In -Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based Oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In- Tm-Zn-based oxide, In-Yb-Zn-based oxide, or In-Lu-Zn-based oxide and other three-component metal oxides, or, for example, In-Sn-Ga-Zn-based Oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn- Four-component metal oxides such as Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, or In-Hf-Al-Zn-based oxides.

Note that, for example, here "In-Ga-Zn-based oxide" means an oxide containing In, Ga, and Zn as its main components and the ratio of In, Ga, and Zn is not particularly limited . The oxide based on In-Ga-Z contains another metal element plus In, Ga, and Zn.

Not limited to the double-layer structure in which the second crystalline oxide semiconductor layer is formed on the first crystalline oxide semiconductor layer, after forming the second crystalline oxide semiconductor layer, by repeatedly performing the process for forming the third crystalline oxide semiconductor layer The process of film formation and heat treatment forms a stacked structure consisting of three or more layers.

The stacked oxide semiconductor layer 453 including the oxide semiconductor layer formed by the above-described forming method can be suitably used as the transistor 162 that can be applied to the semiconductor device disclosed in this specification.

In the transistor according to Embodiment 3 using the stack of plural oxide semiconductor layers of this embodiment as the oxide semiconductor layer, the electric field is not applied from one surface of the oxide semiconductor layer to the other surface and the current is not in the plural The thickness direction of the stack of oxide semiconductor layers (from one surface to the other surface; in particular, in the vertical direction in FIG. 15A) flows. The transistor has a structure in which current mainly flows through the stacked interface of the oxide semiconductor layer; therefore, even when the transistor is irradiated with light or even when BT stress is applied to the transistor, the deterioration of the transistor characteristics can be suppressed or reduced.

By using a stack of a first crystalline oxide semiconductor layer such as an oxide semiconductor layer 453 and a second crystalline oxide semiconductor layer to form an electric crystal Body, transistors can have stable electrical characteristics and high reliability.

This embodiment can be implemented in appropriate combination with any structure described in other embodiments.

(Example 6)

For various reasons, the measured field effect mobility of the insulated gate transistor is lower than its original mobility: this phenomenon not only occurs when an oxide semiconductor is used. One of the reasons is that the defect inside the semiconductor or the defect at the interface between the semiconductor and the insulating film reduces the mobility. When the Levinson model is used, it is theoretically possible to calculate the field-effect mobility under the assumption that no defects exist inside the semiconductor.

When assuming that the original mobility and the field effect mobility of a semiconductor measured μ _o and [mu], respectively, and a potential barrier (e.g., grain boundaries) is present in the semiconductor, the following equation represents the measured field-effect mobility.

Here, E represents the height of the potential barrier, k represents the Bozeman constant, and T represents the absolute temperature. When the potential barrier is assumed to be due to a defect, the height of the potential barrier can be expressed by the following equation according to the Lee Vinson model.

Here, e represents the basic charge, N represents the average defect density per unit area in the channel, ε represents the dielectric coefficient of the semiconductor, n represents the number of carriers per unit area in the channel, _Cox represents the capacitance per unit area, V _g represents the gate voltage and t represents the thickness of the channel. In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel is considered to be the same as the thickness of the semiconductor layer. The drain current I _d in the linear region is expressed by the following equation.

Here, L represents the channel length, W represents the channel length, and both L and W are 10 μm. In addition, V _d represents the drain voltage. When the two sides of the above equation are divided by V _g and then the logarithms of both sides are taken, the following equation is obtained.

The right side of equation 5 is a function of V _g . From the equation, it is found that the slope of the line in the graph obtained from the real measurement values plotted with ln(I _d /V _g ) as the vertical axis and 1/V _g as the horizontal axis can obtain the defect density N. That is, from the I _d -V _g characteristic curve of the transistor, the defect density is evaluated. An oxide semiconductor having a ratio of indium (In), tin (Sn), and zinc (Sn) of 1:1:1 has a defect density N of about 1×10 ¹² /cm ² .

The defect density is obtained in this manner and the like, from Equations 2 and 3, μ _o is calculated 120cm ² / Vs. The measured mobility of In-Sn-Zn-based oxides containing defects is about 35 cm ² /Vs. However, assuming that no defect exists in the interface between the inner semiconductor and the insulating film and the semiconductor, the mobility of the oxide semiconductor is expected μ _o is 120cm ² / Vs.

Note that even when no defects exist inside the semiconductor, scattering at the interface between the channel and the gate insulating film affects the transmission characteristics of the transistor. In other words, the mobility μ ₁ at a position x away from the interface between the channel and the gate insulating film is expressed by the following equation.

Here, D represents the electric field in the direction of the gate electrode, and B and G are constants. B and G are obtained from real measurement results; according to the above measurement results, B is 4.75×10 ⁷ cm/s and G is 10 nm (interface scattering affects the depth of arrival). When D increases (that is, when the gate voltage increases), the second term of Equation 6 increases, and the mobility μ ₁ thus decreases.

FIG. 27 shows the calculation result of the mobility μ ₂ of the transistor whose channel contains an ideal oxide semiconductor without defects inside the semiconductor. For calculation, the device simulation software Sentauraus Device manufactured by Synopsys Inc. was used, and the band gap, electron affinity, relative permittivity, and thickness of the oxide semiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and 15 nm, respectively. These values are obtained by measuring the thin film formed by the sputtering method.

In addition, the work functions of the gate electrode, the source electrode, and the drain electrode are assumed to be 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of the gate insulating film is assumed to be 100 nm, and its relative permittivity is assumed to be 4.1. The channel length and the channel width are both assumed to be 10 μm, and the drain voltage V _{d is} assumed to be 0.1V.

As shown in FIG. 27, the mobility has a peak value greater than 100 cm ² /Vs where the gate voltage slightly exceeds 1 V and decreases as the gate voltage becomes higher due to the increased influence of interface scattering. Note that in order to reduce interfacial scattering, it is preferable that the surface of the semiconductor layer is atomically flat (the atomic layer is flat).

The results of the characteristics of the minute transistors manufactured using the oxide semiconductor having this mobility are shown in FIGS. 28A to 28C, FIGS. 29A to 29C, and FIGS. 30A to 30C. 31A and 31B show the cross-sectional structure of the transistor used for calculation. The transistors shown in FIGS. 31A and 31B each include a semiconductor region 2103a and a semiconductor region 2103c, and the semiconductor region 2103a and the semiconductor region 2103c have n ⁺ type conductivity in the oxide semiconductor layer. The resistivity of the semiconductor region 2103a and the semiconductor region 2103c is 2×10 ^-3 Ω cm.

The transistor shown in FIG. 31A is formed on the base insulating film 2101 and the embedded insulator 2102, and the embedded insulator 2102 is embedded on the base insulating film 2101 and formed of aluminum oxide. The transistor includes a semiconductor region 2103a, a semiconductor region 2103c, an essential semiconductor region 2103b serving as a channel formation region therebetween, and a gate electrode 2105. The width of the gate electrode 2105 is 33 nm.

The gate insulating film 2104 is formed between the gate electrode 2105 and the semiconductor region 2103b. In addition, the side wall insulator 2106a and the side wall insulator 2106b are formed on both side surfaces of the gate electrode 2105, and the insulator 2107 is formed on the gate electrode 2105 to prevent a short circuit between the gate electrode 2105 and another wiring. The sidewall insulator has a width of 5 nm. The source electrode 2108a and the drain electrode 2108b are provided to contact the semiconductor region 2103a and the semiconductor region 2103c, respectively. Note that the channel width of this transistor is 40nm.

The transistor of FIG. 31B is the same as the transistor of FIG. 31A in that it is formed on a base insulating film 2101 and an embedded insulator 2102 formed of alumina The upper and it includes a semiconductor region 2103a, a semiconductor region 2103c, an intrinsic semiconductor region 2103b provided therebetween, a gate electrode 2105 having a width of 33 nm, a gate insulating film 2104, a sidewall insulator 2016a, a sidewall insulator 2106b, an insulator 2107, a source The pole electrode 2108a and the drain electrode 2108b.

The transistor shown in FIG. 31A differs from the transistor shown in FIG. 31B in the conductivity type of the semiconductor region under the sidewall insulator 2106a and the sidewall insulator 2106b. In the transistor shown in FIG 31A, a sidewall insulator 2106a and the semiconductor region under the sidewall insulator 2106b is part of a semiconductor region having a n ⁺ -type conductivity portion of the semiconductor region 2103a and 2103c having n ⁺ conductivity type, In the transistor shown in FIG. 31B, the semiconductor region under the sidewall insulator 2106a and the sidewall insulator 2106b is part of the intrinsic semiconductor region 2103b. In other words, in the semiconductor layer of FIG. 31B, a region with a width L _off that neither overlaps the semiconductor region 2103a (semiconductor region 2103c) nor the gate electrode 2105 is provided. This area is called the offset area, and the width L _{off is} called the offset length. As seen in the figure, the offset length is equal to the width of the side wall insulator 2106a (side wall insulator 2106b).

The other parameters used in the calculation are as described above. For calculation, the device simulation software Sentaurus Device manufactured by Synopsys Inc. was used. FIGS. 28A to 28C show the drain current (I _d , solid line) and mobility (μ, dashed line) and gate voltage (V _g : gate electrode and source electrode) of the transistor having the structure shown in FIG. 31A Between the potential difference). Under the assumption that the drain voltage (the potential difference between the drain and the source) is +1V, the drain current I _{d is} obtained by calculation, and under the assumption that the drain voltage is +0.1V, the migration is obtained by calculation率μ.

FIG. 28A shows the gate voltage dependency of the transistor in the case where the thickness of the gate insulating film is 15 nm, FIG. 28B shows the gate voltage dependency of the transistor in the case where the thickness of the gate insulating film is 10 nm, and FIG. 28C shows the gate In the case where the thickness of the electrode insulating film is 5 nm, the gate voltage dependence of the transistor is dependent. As the gate insulating film becomes thinner, the drain electrode I _d (off-state current) particularly in the off-state significantly decreases. In contrast, the peak value of the mobility μ and the drain current I _d (on state current) in the on state do not change significantly. The graph shows that the drain current of the gate voltage near 1V exceeds 10μA, which is required in memory cells and the like.

FIGS. 29A to 29C show the dependence of the drain current (I _d , solid line) and mobility (μ, dashed line) of the transistor having the offset length L _off of the structure shown in FIG. 31B of 5 nm on the gate voltage . Under the assumption that the drain voltage is +1V, the drain current I _{d is} obtained by calculation, and under the assumption that the drain voltage is +0.1V, the mobility μ is obtained by calculation. FIG. 29A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating film is 15 nm, FIG. 29B shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating film is 10 nm, and FIG. 29C shows the gate In the case where the thickness of the electrode insulating film is 5 nm, the gate voltage dependence of the transistor is dependent.

In addition, FIGS. 30A to 30C show the drain current (I _d , solid line) and mobility (μ, broken line) of the transistor with the offset length L _off of the structure shown in FIG. 31B and a gate voltage of 15 nm and the gate voltage. Interdependence. Under the assumption that the drain voltage is +1V, the drain current I _{d is} obtained by calculation, and under the assumption that the drain voltage is +0.1V, the mobility μ is obtained by calculation. FIG. 30A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating film is 15 nm, FIG. 30B shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating film is 10 nm, and FIG. 30C shows the gate In the case where the thickness of the electrode insulating film is 5 nm, the gate voltage dependence of the transistor is dependent.

In any structure, as the gate insulating film becomes thinner, the off-state current significantly decreases, and the peak value of the mobility μ and the on-state current do not change significantly.

Note that the peak value of the mobility μ in FIGS. 28A to 28C is about 80 cm ² /Vs, about 60 cm ² /Vs in FIGS. 29A to 29C, and about 40 cm ² /Vs in FIGS. 30A to 30C; therefore, The peak of the mobility μ decreases as the offset length L _off increases. In addition, the same reasoning can be used for off-state current. The on-state current also decreases as the offset length L _off increases; however, the on-state current decreases more gently than the off-state current. In addition, the graph shows that in any structure, at a gate voltage near 1V, the drain current exceeds the required 10μA in a memory cell or the like.

[Example 1]

By depositing an oxide semiconductor when heating the substrate, or performing a heat treatment after forming the oxide semiconductor film, the transistor using an oxide semiconductor containing In, Sn, and Zn as main components as the channel formation region can have advantageous characteristics. Note that the main component means that the composition of the contained element is 5 atomic% or more.

In the formation of oxide semiconductors containing In, Sn, and Zn as main components After the body, the substrate is intentionally heated to improve the field effect mobility of the transistor. In addition, the critical voltage of the transistor is positively shifted to make the transistor normally off.

For example, FIGS. 32A to 32C all show the characteristics of a transistor in which an oxide semiconductor film containing In, Sn, and Zn as main components and having a channel length L of 3 μm and a channel width W of 10 μm, and a thickness of 100 nm are used Gate insulating film. Note that V _{d is} set at 10V.

FIG. 32A shows the characteristics of a transistor in which the substrate is intentionally heated by a sputtering method to form an oxide semiconductor film containing In, Sn, and Zn as main components of the transistor. The field-effect mobility of the transistor is 18.8 cm ² /Vsec. On the other hand, when an oxide semiconductor film containing In, Sn, and Zn as main components is formed when the substrate is intentionally heated, the field effect mobility is improved. FIG. 32B shows the characteristics of a transistor that forms an oxide semiconductor film containing In, Sn, and Zn as main components when the substrate is heated at 200°C. The field-effect mobility of the transistor is 32.2cm ² /Vsec.

By performing heat treatment after forming an oxide semiconductor film containing In, Sn, and Zn as main components, the field effect mobility is further improved. FIG. 32C shows the characteristics of a transistor in which an oxide semiconductor containing In, Sn, and Zn as main components is formed by sputtering at 200°C, and then the oxide semiconductor film is subjected to a heat treatment at 650°C. The field-effect mobility of the transistor is 34.5cm ² /Vsec.

The deliberate heating of the substrate is expected to have the effect of reducing the moisture absorbed into the oxide semiconductor film during sputtering formation. In addition, the heat treatment after film formation can release and remove hydrogen, hydroxyl groups, or moisture from the oxide semiconductor film. In this way, the field effect mobility can be improved. It is assumed that this field effect mobility improvement is obtained not only by removing impurities by dehydration or dehydrogenation, but also by reducing the reduction in the distance between atoms due to the increased density. It is highly purified by removing impurities from the oxide semiconductor to crystallize the oxide semiconductor. In the case of using this highly purified non-single-crystal oxide semiconductor, ideally, it is expected to realize field-effect mobility exceeding 100 m ² /Vsec.

An oxide semiconductor containing In, Sn, and Zn as main components is crystallized in the following manner: oxygen ions are implanted into the oxide semiconductor, and heat treatment is used to release hydrogen, hydroxyl, or moisture contained in the oxide semiconductor, and, The oxide semiconductor is crystallized via heat treatment or another heat treatment performed later. By this crystallization treatment or recrystallization treatment, a non-single-crystal oxide semiconductor having favorable crystallinity is obtained.

The deliberate heating of the substrate during film formation and/or the heat treatment after film formation not only helps to improve the field effect mobility, but also helps to keep the transistors off. In a transistor using an oxide semiconductor film containing In, Sn, and Zn as main components and not intentionally heating the substrate as a channel formation region, the critical voltage tends to shift toward the negative direction. However, when the oxide semiconductor film formed when the substrate is intentionally heated is used, the problem of negative shift of the threshold voltage can be solved. That is, the threshold voltage is shifted so that the transistor becomes normally closed; by comparing FIGS. 32A and 32B, this trend can be confirmed.

Note that by changing the ratio of In, Sn, and Zn, the critical voltage can also be controlled; when the composition ratio of In, Sn, and Zn is 2:1:3, it is expected that a normally-off transistor is formed. In addition, by setting the composition ratio of the target as follows, an oxide semiconductor film having high crystallinity is obtained: In:Sn:Zn= 2:1:3.

The temperature of intentional heating or heat treatment of the substrate is 150°C or higher, preferably 200°C or higher, and preferably 400°C or higher. When film formation or heat treatment is performed at a high temperature, the transistor is normally off.

By deliberately heating the substrate during film formation and/or performing heat treatment after film formation, the stability against gate bias stress can be improved. For example, when the gate bias voltage is applied at 150 ℃ at a strength of 2 MV/cm for one hour, the drift of the critical voltage is less than ±1.5V, preferably less than ±1.0V.

The BT test was performed on the following two transistors: Sample 1 that did not perform heat treatment after the oxide semiconductor film was formed, and Sample 2 that performed heat treatment at 650°C after the oxide semiconductor film was formed.

First, the V _g -I _d characteristics of these transistors were measured at a substrate temperature of 25° C. and a V _d of 10 V. Note that V _d represents the drain voltage (the potential difference between the drain and the source). Then, the substrate temperature was set at 150° C., and V _{d was} set at 0.1V. Thereafter, the application of V _g 20V, so that the intensity of an electric field applied to the gate electrode insulating film is 2MV / cm, and the conditions were maintained for one hour. Next, V _{g is} set to 0V. Then, at a substrate temperature of 25° C. and a V _d of 10 V, the V _g -I _d characteristics of these transistors were measured. This process is called a positive BT test.

In a similar manner, the V _g -I _d characteristics of these transistors were measured at a substrate temperature of 25° C. and a V _d of 10 V. Then, the substrate temperature was set at 150° C., and V _{d was} set at 0.1V. Thereafter, the application of -20V V _g, so that the electric field intensity applied to the gate electrode insulating film is -2MV / cm, and the conditions were maintained for one hour. Next, V _{g is} set to 0V. Then, at a substrate temperature of 25° C. and a V _d of 10 V, the V _g -I _d characteristics of these transistors were measured. This process is called a negative BT test.

33A and 33B show the positive BT test result of Sample 1 and the negative BT test result of Sample 1, respectively. 34A and 34B show the positive BT test result of Sample 2 and the negative BT test result of Sample 2, respectively.

The critical voltage offsets of Sample 1 due to the positive BT test and negative BT test were 1.80V and -0.42V, respectively. The critical voltage offsets of Sample 2 due to the positive BT test and negative BT test were 0.79V and 0.76V, respectively. It was found that in samples 1 and 2, the shift in the threshold voltage between before and after the BT test is small and its reliability is high.

The heat treatment is performed in an oxygen atmosphere; alternatively, in a nitrogen or inert gas atmosphere, or under reduced pressure and then in an oxygen-containing atmosphere, the heat treatment is first performed. Oxygen is supplied to the oxide semiconductor after dehydration or dehydrogenation, thus further increasing the effect of heat treatment. As for the method of supplying oxygen after dehydration or dehydrogenation, a method in which oxygen ions are accelerated by an electric field and implanted into the oxide semiconductor film can be used.

In the oxide semiconductor or the interface between the oxide semiconductor and the film in contact with the oxide semiconductor, it is easy to cause defects caused by insufficient oxygen; however, when heat treatment contains excessive oxygen in the oxide semiconductor At this time, the oxygen defects caused by the fixed can be compensated by excess oxygen. Excess oxygen is mainly present between the crystal lattices. When the concentration of excess oxygen is set to be higher than or equal to 1×10 ¹⁶ /cm ³ and lower than or equal to 2×10 ²⁰ /cm ³ , excessive oxygen can be contained in the oxide semiconductor without causing crystal distortion, etc. Wait.

When heat treatment is performed so that at least part of the oxide semiconductor includes crystals At this time, a more stable oxide semiconductor film can be obtained. For example, when X-ray diffraction (XRD) is used to analyze an oxide semiconductor film formed by sputtering but not intentionally heating the substrate using a target with a composition ratio of In:Sn:Zn=1:1:1 , A halo pattern was observed. The formed oxide semiconductor film is crystallized by subjecting it to heat treatment. The temperature of the heat treatment is appropriately set: for example, when the heat treatment is performed at 650°C, a clear diffraction peak is observed in X-ray diffraction analysis.

Perform XRD analysis of In-Sn-Zn-O. An X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used to perform XRD analysis, and measurement was performed by an out-of-plane method.

Prepare Sample A and Sample B and perform XRD analysis on them. In the following, the manufacturing methods of Sample A and Sample B will be explained.

An In-Sn-Zn-O film with a thickness of 100 nm was formed on the quartz substrate that had undergone the dehydrogenation treatment.

In an oxygen atmosphere, an In-Sn-Zn-O film was formed with a sputtering device of 100W (DC) power. As the target, an In-Sn-Zn-O target having an atomic ratio of In:Sn:Zn=1:1:1 is used. Note that the substrate heating temperature at the time of film formation is set at 200°C. The sample manufactured in this way was used as sample A.

Next, the sample prepared in a similar manner to Sample A was subjected to a heat treatment at 650°C. Regarding the heat treatment, first, heat treatment in a nitrogen atmosphere is performed for one hour, and, again, heat treatment in an oxygen atmosphere is performed for one hour without lowering the temperature. The sample manufactured in this way is referred to as sample B.

Figure 35 shows the XRD spectrum of sample A and sample B. No peaks due to crystals were observed in sample A, but in sample B, when 2 θ is about 35 degrees, and from 37 degrees to 38 degrees, peaks due to crystals are observed.

As described above, by deliberately heating the substrate during the deposition of the oxide semiconductor containing In, Sn, and Zn as main components, and/or by performing heat treatment after deposition, the characteristics of the transistor can be improved.

These substrate heating and heat treatments have the effect of preventing impurities such as hydrogen and hydroxyl groups that are detrimental to the oxide semiconductor from being contained in the film or the effect of removing hydrogen and hydroxyl groups from the film. That is, by removing hydrogen as the donor impurity from the oxide semiconductor, the oxide semiconductor is highly purified, thereby obtaining a normally-off transistor. The high purity of the oxide semiconductor enables the off-state current of the transistor to be 1 aA/μm or lower. In addition, the unit of off-state current is used to indicate the current per micrometer of the channel width.

Fig. 36 shows the relationship between the off-state current of the transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. Here, for the sake of simplicity, the horizontal axis represents the value (1000/T) obtained by multiplying 1000 by the reciprocal of the substrate temperature at the time of measurement.

Specifically, as shown in FIG. 36, when the substrate temperature is 125°C, 85°C, and room temperature (27°C), the off-state current is 1 aA/μm (1×10 ^-18 A/μm) or lower , 100zA/μm (1×10 ^-19 A/μm) or lower, and 1zA/μm (1×10 ^-21 A/μm) or lower. Preferably, when the substrate temperature is 125°C, 85°C, and room temperature (27°C), the off-state current is 0.1aA/μm (1×10 ^-19 A/μm) or lower, 10zA/μm ( 1×10 ^-20 A/μm) or lower, and 0.1zA/μm (1×10 ^-22 A/μm) or lower.

Note that in order to prevent hydrogen and moisture from being contained in the oxide semiconductor film during the formation of the oxide semiconductor film, by sufficiently suppressing leakage from the outside of the deposition chamber and degassing through the inner wall of the deposition chamber, it is preferable Increase the purity of the sputtering gas. For example, a gas having a dew point of -70°C or lower is preferably used as a sputtering gas to prevent moisture from being contained in the film. In addition, it is preferable to use a highly purified target so as not to contain impurities such as hydrogen and moisture. Although it is possible to remove moisture from the oxide semiconductor film containing In, Sn, and Zn as main components by heat treatment, since moisture is removed from the film containing In, Sn, and Zn at higher temperatures The oxide semiconductor of the component is released rather than the oxide semiconductor containing In, Ga, and Zn as the main components, so it is preferable to form a film that does not originally contain moisture.

The relationship between the substrate temperature and the electrical characteristics of the transistor formed by the sample B performing heat treatment at 650°C after the formation of the oxide semiconductor film was evaluated.

The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, a L _OV of 0 μm, and a dW of 0 μm. Note that V _{d is} set at 10V. Note that the substrate temperature is -40°C, -25°C, 25°C, 75°C, 125°C, and 150°C. Here, in the transistor, the width of the portion where the gate electrode overlaps with one of the paired electrodes is called L _OV , and the width of the portion of the paired electrode that does not overlap with the oxide semiconductor film is called Is dW.

Figure 37 shows the dependence of I _d (solid line) and field effect mobility (dashed line) on V _g . Fig. 38A shows the relationship between the substrate temperature and the critical voltage, and Fig. 38B shows the relationship between the substrate temperature and the field effect mobility.

From Figure 38A, it is found that the threshold voltage changes as the substrate temperature increases low. Note that in the range of -40°C to 150°C, the critical voltage drops from 1.09V to -0.23V.

From FIG. 38B, it is found that the field effect mobility becomes lower as the substrate temperature increases. Note that in the range of -40°C to 150°C, the field-effect mobility decreases from 36 cm ² /Vs to 32 cm ² /Vs. Therefore, it was found that the variation in electrical characteristics was small in the above temperature range.

In the transistor using this oxide semiconductor containing In, Sn, and Zn as the main components as the channel formation region, in order to maintain the off-state current of 1 aA/μm or lower, 30 cm ² /Vsec or higher is achieved. A field effect mobility of 40 cm ² /Vsec or higher and 60 cm ² /Vsec or higher is better, which can achieve the on-state current required by the LSI. For example, in a FET with an L/W of 33 nm/40 nm, when the gate voltage is 2.7 V and the drain voltage is 1.0 V, an on-state current of 12 μA or higher can flow. In addition, in the temperature range required for transistor operation, sufficient electrical characteristics can be ensured. According to these features, an integrated circuit having a novel function can be realized, but even if a transistor including an oxide semiconductor is provided in an integrated circuit formed using a Si semiconductor, the operation speed is not reduced.

[Example 2]

In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be described below with reference to FIGS. 39A and 39B.

39A and 39B are a top view and a cross-sectional view of a coplanar transistor having a top gate top contact type structure. Figure 39A is a top view of the transistor Figure. Fig. 39B shows the A-B section in Fig. 39A.

The transistor shown in FIG. 39B includes a base 3100; a base insulating film 3102 provided on the base 3100; a protective insulating film 3104 provided in the periphery of the base insulating film 3102; an oxide semiconductor film 3106 provided on the base insulating film 3102 And the protective insulating film 3104, including the high-resistance region 3106a and the low-resistance region 3106b; the gate insulating film 3108 provided on the oxide semiconductor film 3106; the gate electrode 3110, arranged to overlap the oxide semiconductor film 3106 to The gate insulating film 3108 is interposed therebetween; the side wall insulating film 3112 is arranged to contact the side surface of the gate electrode 3110; the pair of electrodes 3114 is arranged to contact at least the low resistance region 3106b; the interlayer insulating film 3116 is arranged to at least cover the oxide The semiconductor film 3106, the gate electrode 3110, and the pair of electrodes 3114; and, the wiring 3118 is provided to be connected to at least one of the pair of electrodes 3114 via an opening formed in the interlayer insulating film 3116.

Although not shown, a protective film may be provided to cover the interlayer insulating film 3116 and the wiring 3118. With the protective film, a small amount of leakage current caused by the conduction of the surface of the interlayer insulating film 3116 can be reduced, and thus the off-state current of the transistor can be reduced.

[Example 3]

In this example, another example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be explained below.

40A and 40B are top and cross-sectional views showing the structure of the transistor manufactured in this example. Fig. 40A is a top view of the transistor. Figure 401B It is A-B cross section in FIG. 40A.

The transistor shown in FIG. 40B includes a base 3600; a base insulating film 3602 provided on the base 3600; an oxide semiconductor film 3606 provided on the base insulating film 3602; a pair of electrodes 3614 contacting the oxide semiconductor film 3606; The gate insulating film 3608 on the oxide semiconductor film 3606 and the pair of electrodes 3614; the gate electrode 3610 is arranged to overlap the oxide semiconductor film 3606 with the gate insulating film 3608 in between; the interlayer insulating film 3616 is provided The gate insulating film 3608 and the gate electrode 3610 are covered; the wiring 3618 is connected to the pair of electrodes 3614 through the opening formed in the interlayer insulating film 3616; and the protective film 3620 is provided to cover the interlayer insulating film 3616 and the wiring 3618 .

As the substrate 3600, a glass substrate is used. A silicon oxide film is used as the base insulating film 3602. As the oxide semiconductor film 3606, an In-Sn-Zn-O film is used. A tungsten film is used as the paired electrode 3614. A silicon oxide film is used as the gate insulating film 3608. The gate electrode 3610 has a stacked structure of a tantalum nitride film and a tungsten film. The interlayer insulating film 3616 has a stack structure of a silicon oxynitride film and a polyimide film. The wirings 3618 each have a stacked structure in which a titanium film, an aluminum film, and a titanium film are sequentially formed. As the protective film 3620, a polyimide film was used.

Note that in a transistor having the structure shown in FIG. 40A, the width of a portion where the gate electrode 3610 overlaps one of the paired electrodes 3614 is called L _OV . Similarly, the width of the portion of the pair of electrodes 3614 that does not overlap with the oxide semiconductor film 3606 is called dW.

This application is based on the application of Japanese Patent Application Serial No. 2010-178045 filed with the Japanese Patent Office on August 6, 2010 and May 5, 2011 The application for Japanese Patent Application Serial No. 2011-108416 filed with the Japanese Patent Office on May 13 is incorporated by reference.

800‧‧‧Signal line

802‧‧‧Reverse gate

803a‧‧‧transistor

803b‧‧‧transistor

804‧‧‧Signal line

805‧‧‧Region

Claims (4)

A semiconductor device having: a first transistor; a capacitor; a driver including a first wiring, a second wiring, an insulating layer, and a second transistor; and a third transistor, wherein the first transistor has: including a channel An oxide semiconductor layer, a gate electrode, a source electrode, and a drain electrode of the forming region, the capacitor is electrically connected to one of the source electrode or the drain electrode of the first transistor, the driver and the first The gate electrode of a transistor is electrically connected, the first wiring has an area overlapping the second wiring via the insulating layer, the first wiring and the gate electrode of the first transistor are subjected to the same process Forming, the second wiring is formed through the same process as the source electrode or the drain electrode of the first transistor, the film thickness of the first wiring is smaller than the film thickness of the second wiring, the second wiring Longer than the first wiring described above, the first wiring is connected to the gate electrode of the second transistor through the second wiring, the third transistor has silicon including a channel formation region, and the first transistor is provided on the first wiring Three transistors. A semiconductor device having: a first transistor; a capacitor; a driver including a first wiring, a second wiring, an insulating layer, and a second transistor; and a third transistor, wherein the first transistor has: including a channel An oxide semiconductor layer, a gate electrode, a source electrode, and a drain electrode of the forming region, the capacitor is electrically connected to one of the source electrode or the drain electrode of the first transistor, the driver and the first The gate electrode of a transistor is electrically connected, the first wiring has a region overlapping the second wiring via the insulating layer, the first wiring is on the same layer as the gate electrode of the first transistor, the first The second wiring is on the same layer as the source electrode or the drain electrode of the first transistor. The film thickness of the first wiring is smaller than that of the second wiring, and the second wiring is longer than the first wiring. The first wiring is electrically connected to the gate of the second transistor through the second wiring, the third transistor has silicon including a channel formation region, and the first transistor is provided on the third transistor. The semiconductor device according to claim 1 or 2, wherein the oxide semiconductor layer has c-axis aligned crystals. The semiconductor device according to claim 1 or 2, wherein the oxide semiconductor layer has In, Ga, and Zn.

Images