TWI684277B - Semiconductor devices and methods for forming the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a first-type well, a second-type buried layer, a first second-type well, a first second-type doping region, a second second-type well, and a second second-type doping region. The first-type well is deposited on the substrate. The second-type buried layer is deposited in the first-type well and away from the substrate with a first predetermined distance. The first second-type well is deposited in the first-type well, above the second-type buried layer, and connected to the second-type buried layer. The first second-type doping region is deposited in the first second-type well. The second second-type well is deposited in the first-type well, above the second-type buried layer, and away from the second-type buried layer with a second predetermined distance. The second second-type doping region is deposited in the second second-type well.

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor device, and in particular to a semiconductor device having a high current and a low pinch junction voltage field effect transistor and a manufacturing method thereof.

In the semiconductor industry, there are two main types of field effect transistors (FETs), namely insulated gate field effect transistors (IGFETs), commonly known as metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistor, MOSFET), and junction field effect transistor (JFET). The structure and configuration of the metal oxide semiconductor field effect transistor and the junction field effect transistor are basically different. For example, the gate of a metal oxide semiconductor field effect transistor includes an insulating layer, that is, a gate oxide layer, between the gate and the other electrodes of the transistor. Therefore, the channel current in the metal oxide semiconductor field effect transistor is controlled by the electric field passing through the channel to enhance and deplete the channel region as required. The gate electrode of the junction field effect transistor forms a P-N junction with the other electrodes of the transistor. By applying a predetermined gate voltage, the junction field effect transistor can be reverse biased. Therefore, by changing the size of the depletion zone in the channel, the gate P-N junction of the junction field effect transistor can be used to control the channel current.

Generally speaking, the junction field effect transistor can be used as a voltage controlled resistor or an electronically controlled switch. P-type junction field effect transistors containing doped semiconductor materials have a large number of positive carriers or holes, while N-type junction field effect transistors containing doped semiconductor materials have a large number of negative carriers or electronic. At each end of the junction field effect transistor, the source electrode and the drain electrode are formed by ohmic contact, and the current flows through the channel between the source electrode and the drain electrode. In addition, the current can be blocked or cut off by applying a reverse bias to the gate, also known as "pinch-off".

Although the junction field effect transistors and manufacturing methods of existing semiconductor devices have gradually satisfied their intended uses, there is always a trade-off relationship between the conduction current and the clamping voltage of the junction field effect transistors. Generally speaking, it needs to be improved When the current is turned on, the pinch-off voltage also tends to rise, and the pinch-off voltage cannot be kept low, which causes design difficulties.

In view of this, the present invention provides a semiconductor structure including: a substrate, a first conductivity type well region, a second conductivity type buried layer, a first second conductivity type well region, a first second conductivity type doping Region, a second second conductivity type well region and a second second conductivity type doped region. The first conductivity type well region is provided in the substrate. The second conductive type buried layer is disposed in the first conductive type well area, and is at a first predetermined distance from the substrate. The first and second conductivity type well regions are disposed in the first and second conductivity type well regions and are located on the second and second conductivity type buried layers, and are connected to the second and second conductivity type buried layers. The first and second conductivity type doped regions are disposed in the first and second conductivity type well regions. The second conductivity type well region is disposed above the first conductivity type well region and above the second conductivity type buried layer, and is separated from the second conductivity type buried layer by a second predetermined distance. The second second conductivity type doped region is disposed in the second second conductivity type well region.

According to an embodiment of the present invention, the semiconductor structure further includes: a first first conductivity type doped region, a second first conductivity type doped region, and a third first conductivity type doped region. The first first conductivity type doped region is disposed in the first conductivity type well region, and is located between the first second conductivity type well region and the second second conductivity type well region. The second first conductivity type doped region is disposed in the first conductivity type well region, wherein the first first conductivity type doped region and the second first conductivity type doped region are respectively disposed in the second Two sides of the two conductivity type well area. The third first conductivity type doped region is disposed in the first conductivity type well region, wherein the first first conductivity type doped region and the third first conductivity type doped region are respectively disposed in the first Two sides of the two conductivity type well area.

According to an embodiment of the present invention, the first and second conductivity type doped regions and the second and second conductivity type doped regions are connected to a first electrode, wherein the first and first conductivity type doped regions and the above The third first conductivity type doped region is connected to a second electrode, wherein the second first conductivity type doped region is connected to a third electrode.

According to an embodiment of the invention, the semiconductor structure is a first conductivity type junction field effect transistor, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode It is an extreme.

According to an embodiment of the present invention, the second second conductivity type well region has an effective length, wherein at least half of the effective length of the second second conductivity type well region overlaps with the second conductivity type buried layer.

The invention further provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first conductivity type well region in the substrate; forming a second conductivity type buried layer in the first conductivity type well region, located in the above A first conductive type well area, and a first predetermined distance from the substrate; forming a first second conductive type well area in the first conductive type well area and above the second conductive type buried layer, Wherein the first and second conductivity type well regions are connected to the second conductivity type buried layer; forming a second second conductivity type well region in the first conductivity type well region and located in the second conductivity type buried layer Above, wherein the second second conductivity type well region and the second conductivity type buried layer are separated by a second predetermined distance; forming a first second conductivity type doped region in the first second conductivity type well region; And forming a second second conductivity type doped region in the second second conductivity type well region.

According to an embodiment of the present invention, the manufacturing method further includes: forming a first first conductivity type doped region in the first conductivity type well region, and located in the first and second conductivity type well regions and the second Between two conductivity type well regions; forming a second first conductivity type doped region in the first conductivity type well region, wherein the first first conductivity type doped region and the second first conductivity type doped region The regions are respectively located on both sides of the second and second conductivity type well regions; and a third first conductivity type doped region is formed in the first conductivity type well region, wherein the first first conductivity type doped region and the above The third first conductivity type doped regions are respectively disposed on both sides of the first and second conductivity type well regions.

According to an embodiment of the invention, the manufacturing method further includes: coupling the first and second conductivity-type doped regions and the second and second conductivity-type doped regions to a first electrode; and coupling the first and first conductivity The doped region of the type and the third doped region of the first conductivity type are connected to a second electrode; and the doped region of the second first conductivity type is connected to a third electrode.

According to an embodiment of the invention, the semiconductor structure is a first conductivity type junction field effect transistor, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode It is an extreme.

According to an embodiment of the invention, the second second conductivity type well region has an effective length, wherein at least half of the effective length of the second second conductivity type well region overlaps with the second conductivity type buried layer.

The following is a detailed description of the device substrate, the semiconductor device, and the manufacturing method of the semiconductor device of some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different embodiments of the disclosed embodiments. The specific elements and arrangements described below are simply and clearly describing some embodiments of the present disclosure. Of course, these are only examples and not limitations of this disclosure. In addition, repeated reference numbers or labels may be used in different embodiments. These repetitions are merely to briefly describe some embodiments of the present disclosure, and do not mean that there is any correlation between the different embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, it includes the case where the first material layer and the second material layer are in direct contact. Alternatively, there may be a situation where one or more other material layers are spaced apart, in which case, the first material layer and the second material layer may not be in direct contact.

In addition, embodiments may use relative terms, such as "lower" or "bottom" and "higher" or "top" to describe the relative relationship of one element of the drawing to another element. It is understandable that if the device of the figure is turned upside down, the element on the "lower" side will become an element on the "higher" side.

Here, the terms “about”, “approximately” and “approximately” generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, if there is no specific description of "about", "approximate", or "approximately", the meaning of "approximate", "approximate", and "approximately" may still be implied.

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions , Layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, or without departing from the teachings of some embodiments of the present disclosure And/or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in this article. Understandably, these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be in an idealized or excessively formal manner Interpretation, unless specifically defined in the disclosed embodiments.

Some embodiments of the present disclosure can be understood together with the drawings. The drawings of the disclosed embodiments are also regarded as part of the description of the disclosed embodiments. It should be understood that the drawings of the disclosed embodiments are not shown in proportion to actual devices and components. The shape and thickness of the embodiment may be exaggerated in the drawings so as to clearly show the features of the disclosed embodiment. In addition, the structures and devices in the drawings are shown in a schematic manner so as to clearly show the features of the disclosed embodiments.

In some embodiments of the disclosure, relative terms such as "down", "up", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be treated as It is understood as the orientation shown in this paragraph and related drawings. This relative term is only for convenience of description, it does not mean that the device described in it needs to be manufactured or operated in a specific orientation. Terms such as "connection" and "interconnection", etc., for joints and connections, unless specifically defined, may refer to two structures directly contacting, or may refer to two structures not directly contacting, where other structures are located here Between the two structures. In addition, the term “joining and connecting” may also include a case where both structures are movable or both structures are fixed.

FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in FIG. 1, the semiconductor structure 100 includes a substrate 110, a first conductivity type well region 120, a second conductivity type buried layer 131, a first second conductivity type well region 132, a second second conductivity type well region 133, The first first conductivity type doped region 141, the second first conductivity type doped region 142, the third first conductivity type doped region 143, the first second conductivity type doped region 144, and the second second conductivity type Doped region 145.

The first conductivity type well region 120 is formed in the substrate 110 and has the first conductivity type. According to an embodiment of the invention, the substrate 110 is a silicon substrate. According to another embodiment of the present invention, the substrate 110 has a second conductivity type, where the first conductivity type is different from the second conductivity type. According to an embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type. According to another embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type. According to other embodiments of the present invention, the substrate 110 may also be a lightly doped substrate, such as a lightly doped N-type substrate or a P-type substrate.

According to an embodiment of the present invention, the first conductive well 120 may be formed by an ion implantation step. For example, when the first conductivity-type well region 120 is N-type, phosphorus ions or arsenic ions may be implanted in the region where the first conductivity-type well region 120 is to be formed to form the first conductivity-type well region 120. However, when the first conductivity-type well region 120 is P-type, boron ions or indium ions can be implanted in the region where the first conductivity-type well region 120 is to be formed to form the first conductivity-type well region 120. In some embodiments, the first conductive well region 120 is a high-pressure well region.

The second conductive type buried layer 131, the first second conductive type well region 132 and the second second conductive type well region 133 are formed in the first conductive type well region 120, wherein the second conductive type buried layer 131, the first The second conductivity type well region 132 and the second second conductivity type well region 133 have a second conductivity type. According to an embodiment of the present invention, the second conductive type buried layer 131, the first and second conductive type well regions 132, and the second and second conductive type well regions 133 and the substrate 110 have the same conductivity type.

According to an embodiment of the present invention, the second conductive type buried layer 131, the first second conductive type well region 132 and/or the second second conductive type well region 133 may also be formed by an ion implantation step. For example, when the second conductivity type is N type, the second conductivity type buried layer 131, the first and second conductivity type well regions 132 and/or the second and second conductivity type well regions 133 may be implanted Phosphorus ions or arsenic ions form a second conductivity type buried layer 131, a first second conductivity type well region 132 and/or a second second conductivity type well region 133.

However, when the second conductivity type is P-type, it can be implanted in the area where the second conductivity type buried layer 131, the first second conductivity type well region 132 and/or the second second conductivity type well region 133 are to be formed Boron ions or indium ions form the second conductive type buried layer 131, the first second conductive type well region 132 and/or the second second conductive type well region 133. According to an embodiment of the present invention, the doping concentration of the second conductive type buried layer 131, the first second conductive type well region 132 and/or the second second conductive type well region 133 is higher than that of the substrate 110 .

As shown in FIG. 1, the substrate 110 and the first conductivity type well region 120 have an interface S, and the second conductivity type buried layer 131 is a first predetermined distance d1 from the interface S. The first and second conductivity type well regions 132 are disposed in the first and second conductivity type well regions 120 and are located above the second conductivity type buried layer 131 and connected to the second conductivity type buried layer 131. The second and second conductivity type well regions 133 are disposed in the first and second conductivity type well regions 120 and above the second conductivity type buried layer 131 and are separated from the second conductivity type buried layer 131 by a second predetermined distance d2. According to an embodiment of the invention, the first predetermined distance d1 is the same as the second predetermined distance d2. According to another embodiment of the present invention, the first predetermined distance d1 is different from the second predetermined distance d2.

The first doped region 141 of the first conductivity type is disposed in the well region 120 of the first conductivity type, and has the first conductivity type. As shown in FIG. 1, the first and first conductivity-type doped regions 141 are located between the first and second conductivity-type well regions 132 and the second and second conductivity-type well regions 133. According to an embodiment of the present invention, the doping concentration of the first doping region 141 of the first conductivity type is higher than the doping concentration of the well region 120 of the first conductivity type.

The second first conductivity type doped region 142 is disposed in the first conductivity type well region 120 and has the first conductivity type. As shown in FIG. 1, the first first conductivity type doped region 141 and the second first conductivity type doped region 142 are respectively disposed on both sides of the second second conductivity type well region 133. According to an embodiment of the invention, the doping concentration of the second first conductivity type doped region 142 is higher than that of the first conductivity type well region 120.

The third first conductivity type doped region 143 is disposed in the first conductivity type well region 120 and has the first conductivity type. As shown in FIG. 1, the first first conductivity type doped region 141 and the third first conductivity type doped region 143 are respectively disposed on both sides of the first and second conductivity type well regions 132. According to an embodiment of the invention, the doping concentration of the third first conductivity type doped region 143 is higher than that of the first conductivity type well region 120.

The first and second conductivity type doped regions 144 are formed in the first and second conductivity type well regions 132 and have a second conductivity type. According to an embodiment of the invention, the doping concentration of the first and second conductivity type doped regions 144 is higher than that of the first and second conductivity type well regions 132. The second and second conductivity type doped regions 145 are formed in the second and second conductivity type well regions 133. According to an embodiment of the invention, the doping concentration of the second and second conductivity type doped regions 145 is higher than that of the second and second conductivity type well regions 133.

According to an embodiment of the present invention, the semiconductor structure 100 further includes a first isolation structure 151, a second isolation structure 152, a third isolation structure 153, a fourth isolation structure 154, a fifth isolation structure 155, and a sixth isolation structure 156. The first isolation structure 151 contacts the third doped region 143 of the first conductivity type, but it is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure 151 and the third first conductivity type doped region 143 are spatially separated from each other.

As shown in FIG. 1, the second isolation structure 152 directly contacts the third first conductivity type doped region 143 and the first second conductivity type doped region 144 to separate the third first conductivity type doped region 143 and The first and second conductivity type doped regions 144. According to other embodiments of the present invention, the second isolation structure 152 does not directly contact at least one of the third first conductivity type doped region 143 and the first second conductivity type doped region 144.

As shown in FIG. 1, the third isolation structure 153 directly contacts the first first conductivity type doped region 141 and the first second conductivity type doped region 144 to separate the first first conductivity type doped region 141 and The first and second conductivity type doped regions 144. According to other embodiments of the present invention, the third isolation structure 153 does not directly contact at least one of the first first conductivity type doped region 141 and the first second conductivity type doped region 144.

As shown in FIG. 1, the fourth isolation structure 154 directly contacts the first first conductivity type doped region 141 and the second second conductivity type doped region 145 to separate the first first conductivity type doped region 141 and Second second conductivity type doped region 145. According to other embodiments of the present invention, the fourth isolation structure 154 does not directly contact at least one of the first first conductivity type doped region 141 and the second second conductivity type doped region 145.

As shown in FIG. 1, the fifth isolation structure 155 directly contacts the second first conductivity type doped region 142 and the second second conductivity type doped region 145 to separate the second first conductivity type doped region 142 and Second second conductivity type doped region 145. According to other embodiments of the present invention, the fifth isolation structure 155 does not directly contact at least one of the second first conductivity type doped region 142 and the second second conductivity type doped region 145.

As shown in FIG. 1, the sixth isolation structure 156 contacts the second doped region 142 of the first conductivity type, but it is not intended to limit the present invention. According to other embodiments of the present invention, the sixth isolation structure 156 and the second first conductivity type doped region 142 are spatially separated from each other.

According to other embodiments of the present invention, the semiconductor structure 100 further includes an insulating layer 160, a first interconnect structure 171, a second interconnect structure 172, a third interconnect structure 173, a fourth interconnect structure 174, and a fifth interconnect structure 175. According to an embodiment of the present invention, the first interconnect structure 171 and the second interconnect structure 172 respectively connect the first and second conductivity-type doped regions 144 and the second and second conductivity-type doped regions 145 to the first electrode S1 , The third interconnection structure 173 and the fifth interconnection structure 175 respectively connect the first first conductivity type doped region 141 and the third first conductivity type doped region 143 to the second electrode S2, and the fourth interconnection structure 174 The second first conductivity type doped region 142 is connected to the third electrode S3.

According to an embodiment of the present invention, when the first conductivity type is N type and the second conductivity type is P type, that is, when the first conductivity type well region 120 is N type and the first second conductivity type well When the region 132 and the second second conductivity type well region 133 are P-type, the semiconductor structure 100 is an N-type junction field effect transistor, wherein the first electrode S1 is the gate terminal and the second electrode S2 is the source terminal The third electrode S3 is the drain terminal, and the effective channels of the N-type junction field effect transistor are respectively the first predetermined distance d1 and the second predetermined distance d2.

According to another embodiment of the present invention, when the first conductivity type is P type and the second conductivity type is N type, that is, when the first conductivity type well region 120 is P type and the first second conductivity type When the well region 132 and the second second conductivity type well region 133 are N-type, the semiconductor structure 100 is a P-type junction field effect transistor, where the first electrode S1 is the gate terminal and the second electrode S2 is the In the extreme, the third electrode S3 is the source terminal, and the effective channels of the P-type junction field effect transistor are respectively the first predetermined distance d1 and the second predetermined distance d2.

According to an embodiment of the present invention, the second and second conductivity type well regions 133 have an effective length L133. As shown in FIG. 1, the second conductive type buried layer 131 completely overlaps the effective length L133 of the second second conductive type well region 133. In other words, the second conductive type buried layer 131 is aligned with the edge E of the second second conductive type well 133.

FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. As shown in FIG. 2, the second conductive type buried layer 131 of the semiconductor structure 200 overlaps with half of the effective length L133 of the second second conductive type well region 133. According to other embodiments of the present invention, the second conductive type buried layer 131 overlaps at least half of the effective length L133 of the second second conductive type well region 133.

FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. As shown in FIG. 3, the second conductive type buried layer 131 of the semiconductor structure 300 exceeds the edge E of the second second conductive type well region 133.

FIGS. 4A to 4D are schematic diagrams showing a method of manufacturing a semiconductor structure according to an embodiment of the invention. As shown in FIG. 4A, a substrate 110 is provided, such as a silicon substrate or other suitable semiconductor substrate. According to other embodiments of the present invention, the substrate 110 may also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate. In this embodiment, the substrate 110 has the second conductivity type.

Then, the first conductive well 120 may be formed in a predetermined area of the substrate 110 by a doping process (for example, ion distribution) and thermal diffusion. According to an embodiment of the present invention, the first conductivity type well region 120 has a first conductivity type, where the first conductivity type is different from the second conductivity type.

Then, a second conductivity type buried layer 131 and a first second conductivity can be formed in a predetermined area in the first conductivity type well region 120 by a doping process (for example, ion distribution) and thermal diffusion processes in sequence The well region 132 and the second and second conductivity well regions 133. According to an embodiment of the present invention, the second conductive type buried layer 131, the first second conductive type well region 132, and the second second conductive type well region 133 have a second conductive type. According to other embodiments of the present invention, the doping concentration of the second conductivity type buried layer 131, the first second conductivity type well region 132 and the second second conductivity type well region 133 is higher than that of the first conductivity type well region 120 Doping concentration.

According to one embodiment of the present invention, the first conductivity type well region 120 with a first predetermined distance d1 may be formed first, and then the second conductivity type buried layer 131 may be formed in the first conductivity type well region 120, and then the second The thickness of the first conductive type well region 120 is increased on the conductive type buried layer 131, and the first and second conductive type well regions 132 and 133 are formed in the first conductive type well region 120, respectively. As shown in FIG. 4A, the second conductive type well region 133 and the second conductive type buried layer 131 are separated by a second predetermined distance d2.

According to an embodiment of the present invention, the second conductive type buried layer 131 completely overlaps the second second conductive type well region 133. According to other embodiments of the present invention, the second conductive type buried layer 131 overlaps at least half of the second second conductive type well region 133 (as shown in FIG. 2).

As shown in FIG. 4B, a first isolation structure 151, a second isolation structure 152, a third isolation structure 153, a fourth isolation structure 154, a fifth isolation structure 155, and a sixth isolation structure 156 are formed on the substrate 110. The first isolation structure 151 and the sixth isolation structure 156 extend into the first conductivity type well region 120; the second isolation structure 152 extends into the first conductivity type well region 120 and the first and second conductivity type well regions 132; the third isolation structure 153 extends into the first conductivity type well region 120 and the first and second conductivity type well regions 132; the fourth isolation structure 154 extends into the first conductivity type well region 120 and the second and second conductivity type well regions 133; the fifth isolation structure 155 extends into the second and second conductivity-type well regions 133 and the first conductivity-type well region 120.

According to an embodiment of the present invention, the first isolation structure 151, the second isolation structure 152, the third isolation structure 153, and the fourth isolation structure 154 are used to define the first first conductivity type doped regions 141, the second Spaces of the first conductive type doped region 142, the third first conductive type doped region 143, the first second conductive type doped region 144, and the second second conductive type doped region 145.

As shown in FIG. 4C, a first first conductivity type doped region 141, a second first conductivity type doped region 142, and a third first conductivity type doped region can be formed by a doping process (such as ion distribution) The impurity region 143, the first and second conductivity type doped regions 144, and the second and second conductivity type doped regions 145. According to an embodiment of the invention, the first doped region 141 of the first conductivity type is formed in the well region 120 of the first conductivity type, and is located between the third isolation structure 153 and the fourth isolation structure 154. The second first conductivity type doped region 142 is formed in the first conductivity type well region 120 and is located between the fifth isolation structure 155 and the sixth isolation structure 156.

The third first conductivity type doped region 143 is formed in the first conductivity type well region 120 and is located between the first isolation structure 151 and the second isolation structure 152. The first and second conductivity type doped regions 144 are located in the first and second conductivity type well regions 132 and between the second isolation structure 152 and the third isolation structure 153. The second and second conductivity type doped regions 145 are located in the second and second conductivity type well regions 133 and between the fourth isolation structure 154 and the fifth isolation structure 155.

As shown in FIG. 4D, an insulating layer 160 is formed on the first isolation structure 151, the second isolation structure 152, the third isolation structure 153, the fourth isolation structure 154, the fifth isolation structure 155, the sixth isolation structure 156 and the first The first conductivity type doped region 141, the second first conductivity type doped region 142, the third first conductivity type doped region 143, the first second conductivity type doped region 144, and the second second conductivity type doped region Above area 145.

Next, a first interconnect structure 171, a second interconnect structure 172, a third interconnect structure 173, a fourth interconnect structure 174, and a fifth interconnect structure 175 may be formed on the insulating layer 160 through a metallization process. The first interconnection structure 171 connects the first and second conductivity type doped regions 144 to the first electrode S1, and the second interconnection structure 172 connects the second and second conductivity type doped regions 145 to the first electrode S1 and the third The interconnection structure 173 connects the first first conductivity type doped region 141 to the second electrode S2, the fourth interconnection structure 174 connects the second first conductivity type doped region 142 to the third electrode S3, and the fifth interconnection The structure 175 and the third first conductivity type doped region 143 are respectively connected to the second electrode S2. In this way, the fabrication of the semiconductor structure 100 is completed.

According to an embodiment of the invention, the semiconductor structure 100 is an N-type junction field effect transistor. The first electrode S1 is the gate terminal, the second electrode S2 is the source terminal, the third electrode S3 is the drain terminal, and the effective channels of the N-type junction field effect transistor are the first predetermined distance d1 and the second The given distance d2.

According to another embodiment of the present invention, the semiconductor structure 100 is a P-type junction field effect transistor. The first electrode S1 is the gate terminal, the second electrode S2 is the drain terminal, the third electrode S3 is the source terminal, and the effective channels of the P-type junction field effect transistor are the first predetermined distance d1 and the second The given distance d2.

The invention here proposes a semiconductor structure of a junction field effect transistor and a manufacturing method thereof. Since the effective channel of the junction field effect transistor is divided into the first predetermined distance d1 and the second predetermined distance d2, the junction field effect transistor does not need to increase the pinch voltage when increasing the on-current. Therefore, the semiconductor structure and its manufacturing method proposed by the present invention will effectively break the trade-off relationship between the on-current and the pinch-off voltage of the junction field effect transistor.

Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary knowledge in the technical field can make changes, substitutions, and retouching without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the technical field can implement some implementations from the present disclosure. In the disclosure of the examples, understand the current or future development of processes, machines, manufacturing, material composition, devices, methods and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. This disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above processes, machines, manufacturing, material composition, devices, methods and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes a combination of each patent application scope and embodiment.

100‧‧‧Semiconductor structure

200‧‧‧Semiconductor structure

300‧‧‧Semiconductor structure

110‧‧‧ substrate

120‧‧‧The first conductivity type well area

131‧‧‧Second conductivity type buried layer

132‧‧‧The first and second conductivity wells

133‧‧‧Second and second conductivity type well area

141‧‧‧ First and first conductivity type doped regions

142‧‧‧Second first conductivity type doped region

143‧‧‧The third first conductivity type doped region

144‧‧‧ First and second conductivity type doped regions

145‧‧‧Second and second conductivity type doped regions

151‧‧‧The first isolation structure

152‧‧‧Second isolation structure

153‧‧‧The third isolation structure

154‧‧‧ Fourth isolation structure

155‧‧‧ fifth isolation structure

156‧‧‧Sixth isolation structure

160‧‧‧Insulation

171‧‧‧The first interconnected structure

172‧‧‧Second interconnection structure

173‧‧‧The third interconnection structure

174‧‧‧ fourth interconnected structure

175‧‧‧The fifth interconnected structure

S1‧‧‧First electrode

S2‧‧‧Second electrode

S3‧‧‧third electrode

d1‧‧‧ First set distance

d2‧‧‧Second established distance

L133‧‧‧effective length

E‧‧‧edge

S‧‧‧Interface

Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention; Figure 3 is a display according to the present invention A cross-sectional view of a semiconductor structure according to another embodiment of the invention; and FIGS. 4A to 4D are schematic views showing a method of manufacturing a semiconductor structure according to an embodiment of the invention.

100‧‧‧Semiconductor structure

110‧‧‧ substrate

120‧‧‧The first conductivity type well area

131‧‧‧Second conductivity type buried layer

132‧‧‧The first and second conductivity wells

133‧‧‧Second and second conductivity type well area

141‧‧‧ First and first conductivity type doped regions

142‧‧‧Second first conductivity type doped region

143‧‧‧The third first conductivity type doped region

144‧‧‧ First and second conductivity type doped regions

145‧‧‧Second and second conductivity type doped regions

151‧‧‧The first isolation structure

152‧‧‧Second isolation structure

153‧‧‧The third isolation structure

154‧‧‧ Fourth isolation structure

155‧‧‧ fifth isolation structure

156‧‧‧Sixth isolation structure

160‧‧‧Insulation

171‧‧‧The first interconnected structure

172‧‧‧Second interconnection structure

173‧‧‧The third interconnection structure

174‧‧‧ fourth interconnected structure

175‧‧‧The fifth interconnected structure

S1‧‧‧First electrode

S2‧‧‧Second electrode

S3‧‧‧third electrode

d1‧‧‧ First set distance

d2‧‧‧Second established distance

L133‧‧‧effective length

E‧‧‧edge

S‧‧‧Interface

Claims (10)

A semiconductor structure includes: a substrate; a first conductivity type well region disposed in the substrate, wherein the first conductivity type well region and the substrate have an interface; a second conductivity type buried layer disposed in the above A first conductivity type well area, and a first predetermined distance from the interface; a first second conductivity type well area, disposed in the first conductivity type well area and located in the second conductivity type buried layer And connected to the buried layer of the second conductivity type; a doped region of the first and second conductivity type, disposed in the well region of the first and second conductivity types; a well region of the second and second conductivity type, disposed in the above A first conductivity type well region and above the second conductivity type buried layer, and a second predetermined distance from the second conductivity type buried layer; and a second second conductivity type doped region, disposed in the first 2. Inside the second conductivity type well area. The semiconductor structure as described in item 1 of the scope of the patent application further includes: a first first conductivity type doped region disposed in the first conductivity type well region and located in the first second conductivity type well region and Between the second and second conductivity type well regions; a second first conductivity type doped region disposed in the first conductivity type well region, wherein the first first conductivity type doped region and the second A conductive type doped region is disposed on both sides of the second and second conductive type well regions; and a third first conductive type doped region is disposed on the first conductive type well region, wherein the first A conductive type doped region and the third first conductive type doped region are respectively disposed on both sides of the first and second conductive type well regions. The semiconductor structure as described in item 2 of the patent application scope, wherein the first and second conductivity-type doped regions and the second and second conductivity-type doped regions are connected to a first electrode, wherein the first and first conductivity The type doped region and the third first conductivity type doped region are connected to a second electrode, wherein the second first conductivity type doped region is connected to a third electrode. The semiconductor structure as described in item 3 of the patent application scope, wherein the semiconductor structure is a first conductivity type junction field effect transistor, wherein the first electrode is a gate terminal, and the second electrode is a source Extreme, the third electrode system is a drain. The semiconductor structure according to item 1 of the patent application scope, wherein the second second conductivity type well region has an effective length, wherein at least half of the second second conductivity type well region has at least half of the effective length and the second conductivity type The buried layers overlap. A manufacturing method of a semiconductor device includes: providing a substrate; forming a first conductivity type well region in the substrate, wherein the first conductivity type well region and the substrate have an interface; forming a second conductivity type buried layer Within the first conductivity type well region and a first predetermined distance from the interface; forming a first and second conductivity type well region within the first conductivity type well region and located in the second conductivity type buried layer Above, wherein the first and second conductivity type well regions are connected to the second and second conductivity type buried layers; forming a second and second conductivity type well regions in the first and second conductivity type well regions and located in the second and second conductivity type On the buried layer, wherein the second and second conductivity type wells and the second conductivity The buried layer is at a second predetermined distance; forming a first and second conductivity type doped regions in the first and second conductivity type well regions; and forming a second and second conductivity type doped regions in the second and second regions Within the two-conductivity well area. The manufacturing method described in item 6 of the patent application scope further includes: forming a first first conductivity type doped region in the first conductivity type well region, and located in the first and second conductivity type well regions and the above Between the second and second conductivity type well regions; forming a second first conductivity type doped region in the first conductivity type well region, wherein the first first conductivity type doped region and the second first conductivity region Type doped regions are located on both sides of the second and second conductivity type well regions; and a third first conductivity type doped region is formed in the first conductivity type well region, wherein the first and first conductivity type doped regions The region and the third first conductivity type doped region are respectively disposed on both sides of the first and second conductivity type well regions. The manufacturing method as described in item 7 of the patent application scope further includes: connecting the first and second conductivity-type doped regions and the second and second conductivity-type doped regions to a first electrode; A conductive type doped region and the third first conductive type doped region are connected to a second electrode; and the second first conductive type doped region is connected to a third electrode. The manufacturing method as described in item 8 of the patent application scope, wherein the semiconductor structure is a first conductivity type junction field effect transistor, wherein the first electrode is a gate terminal, and the second electrode is a source Extreme, the third electrode system is a drain. The manufacturing method as described in item 6 of the patent application scope, in which the above The two second conductivity type well regions have an effective length, wherein at least half of the effective length of the second second conductivity type well region overlaps with the second conductivity type buried layer.

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