TWI681502B - Contacting soi substrates - Google Patents

Abstract

An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

Description

Contact SOI substrate

The present invention relates generally to the field of integrated circuits and semiconductor devices, and in particular to the formation of contacts to semiconductor bulk substrates of SOI devices.

Manufacturing advanced integrated circuits such as CPUs (central processing units), storage devices, ASICs (application specific integrated circuits) requires the formation of a large number of circuit elements on a given wafer area according to a specific circuit layout. In various electronic circuits, field effect transistors represent an important type of circuit element, which basically determines the performance of the integrated circuit. Generally speaking, a variety of manufacturing methods and technologies are currently implemented to form field effect transistors (FETs). For many types of complex circuits, the MOS technology is based on operating speed and/or power consumption and/or cost efficiency. The superior characteristics have become one of the most promising methods at present. During the manufacture of complex integrated circuits using, for example, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.

At present, FETs are usually built on silicon-on-insulator (SOI) substrates, especially on fully depleted silicon-on-insulator (FDSOI) substrates. The channel of the FET is formed in a thin semiconductor layer, usually including or made of silicon material or other semiconductor materials, wherein the semiconductor layer is formed on an insulating layer, a buried oxide (BOX) layer, the insulating layer, The buried oxide layer is formed on the semiconductor bulk substrate. A serious problem caused by the radical size reduction of semiconductor devices must be the occurrence of leakage current. Since the leakage current depends on the threshold voltage of the FET, the substrate bias (back biasing) can reduce the leakage power. Through this advanced technology, the substrate or appropriate well is biased to raise the transistor threshold, thereby reducing leakage current. In a PMOS device, the body of the transistor is biased to a voltage higher than the positive supply voltage V _DD . In the NMOS device, the base body of the transistor is biased to a voltage lower than the negative supply voltage V _SS .

FIG. 1a shows an SOI configuration having a semiconductor bulk substrate 10 in which N ⁺ doped regions 11 and P ⁺ doped regions 12 are formed in the bulk substrate 10. In addition, the SOI configuration includes a BOX layer 13 formed on the semiconductor bulk substrate 10 and a semiconductor layer 20 formed on the BOX layer 13 and providing a channel region. FIG. 1a also shows a layer 14 of gate electrode material (eg, polysilicon) formed above the semiconductor layer 20. The N ⁺ doped region 11 and the P ⁺ doped region 12 are used to reverse bias the P-channel FET gate or the N-channel FET gate, respectively. In an integrated circuit (IC), a cell structure is formed by a gate electrode line (polycrystalline line) 14a, which defines a standard cell of an active semiconductor device as the cell shown in FIG. 1a . In general, polysilicon (polysilicon) lines 14a (Figures 1b and 1e) are parallel to each other. It should be noted that, in addition to the polycrystalline material, the gate of the FET may include a metal material. In advanced ICs, the gate structure is so small that with current technology, they cannot be manufactured as arbitrarily arranged gates. Instead, a regular grid of polycrystalline lines 14a composed of parallel polycrystalline line shapes 14a with precisely defined widths and pitches must be fabricated, as shown in Figure 1b. Afterwards, in an additional manufacturing step, the mask will be cut with a poly line (poly line; PC) to remove the unwanted poly line 14a. The regular polycrystalline wire grid ("gate sea") must be surrounded by boundary cells that contain parallel polycrystalline wire shapes 15 with larger widths to protect the regular polycrystalline wires of the standard cell during manufacturing 14a is free from polishing defects.

In order to reduce the time required to execute the design manufacturing method, a cell library has been created in which standard cell designs can be obtained. Of course, some applications may require one or more special units. In this case, the designer will create a custom unit for layout or change the library unit in the manner required by the desired design. The resulting layout is used to manufacture the desired integrated circuit. Depending on the design and library used, PMOS or NMOS devices or both can be reverse biased. The NMOS and PMOS blocks that bias standard cells generate voltages through a charge pump, which is a custom block that outputs V _DDbias and V _SSbias voltages. Each standard cell row must have at least one (body-or well-) tap cell. However, designers are sometimes accustomed to arranging a connection well in the standard cell array at regular intervals and every specific distance.

Similar to this standard cell grid, the connection well grid is usually used in integrated circuit design to provide the substrate bias of the transistor. The connection well must establish an electrical connection between the network providing the bias voltage and the P ⁺ /N ⁺ region (regions 11 and 12 shown in Figure 1a). Since the bias voltage network is implemented on a metal layer that is routed to several layers above the BOX layer 13 shown in FIG. 1a, and resides in the bulk substrate 10 in the P ⁺ /N ⁺ regions 11 and 12 In the case below the BOX layer 13, the part of the BOX layer 13 (which is a good insulator) must be removed to form a contact to the regions 11, 12. Since the BOX layer 13 is thick, the opening etched into the BOX layer 13 must be large. Therefore, there are specific problems in the conventional technology, as shown in Figs. 1c to 1e.

FIG. 1c shows a configuration similar to that shown in FIG. 1a, in which, after patterning the semiconductor layer 20, an opening is formed in the BOX layer 13 and a polycrystalline material layer used to form the gate electrode 14a of the FET is used 14 Fill the opening. The opening of the BOX layer 13 is formed in the regular polyline grid area shown in FIG. 1b. After forming the opening in the BOX layer 13, a polycrystalline material layer 14 is formed to form a reverse bias contact. A mask layer 16 is formed over the polycrystalline material layer 14, as shown in Figure 1c. As shown in FIG. 1d, the mask layer 16 is patterned by standard lithography to obtain a patterned mask 17, which is used to form a polycrystalline line (gate) 14a above the BOX layer 13 (see (Figure 1e).

However, during execution of the etching manufacturing method for forming the polycrystalline gate electrode 14a, a thin polycrystalline ridge 19 is formed in the opening of the BOX layer 13. Actually, the formation of the polycrystalline ridge 19 cannot be properly controlled because the focus of the lithography device used is where the polycrystalline gate 14a must be formed. On the other hand, due to the regular grid of polycrystalline lines formed, the formation of polycrystalline ridges 19 cannot be avoided. Polycrystalline ridge 19 in this opening of BOX layer 13 The undesirable formation of ZnO leads to wafer contamination because the unstable polycrystalline ridge structure 19 is easily broken during further processing.

In view of the above situation, the present invention provides a technique for forming substrate contacts to avoid wafer contamination caused by polycrystalline residues caused by forming thin polycrystalline ridges in large BOX openings in the prior art manufacturing method.

The following provides a brief summary of the invention to provide a basic understanding of some aspects of the invention. The summary of the invention is not an exhaustive overview of the invention. It is not intended to identify key or important elements of the invention or to delineate the scope of the invention. Its sole purpose is to provide some simplified concepts as a prelude to the more detailed description that is discussed later.

In general, the inventive subject matter disclosed herein relates to the formation of semiconductor devices including transistor devices, especially products having (MOS) FETs including tap cells for back biasing the transistor devices体电路。 Body circuit.

The present invention provides an integrated circuit having: a semiconductor bulk substrate; a buried oxide layer formed on the semiconductor bulk substrate; a plurality of units, each unit having a transistor device formed in the buried Above the oxide layer; a plurality of gate electrode lines passing through the cell and providing gate electrodes for the transistor device of the cell; and a plurality of connection cells configured to electrically contact the semiconductor bulk substrate and be arranged At a position different from the position below or above the plurality of units having the transistor device, wherein at least one of the plurality of connection units is arranged at the buried boundary Between units. For example, the integrated circuit may also include a plurality of fill cells in an area that may or may not contain transistors to connect the PC line.

Moreover, the present invention provides an integrated circuit having: a standard cell grid, each of the standard cells having a field effect built on a fully depleted silicon-on-insulator (FDSOI) substrate A transistor; and a plurality of tap cells configured to provide a reverse bias voltage for at least some of the field effect transistor. At least some of the connection units are not constructed above or below any standard units of the standard unit grid.

In addition, the present invention provides a method of manufacturing an integrated circuit, the method comprising: providing a silicon-on-insulator (SOI) substrate having a semiconductor bulk substrate and a buried oxide layer formed on the bulk substrate; on the SOI substrate Forming a transistor device; forming at least one of an N-doped region and a P-doped region in the bulk substrate; the buried oxide above the at least one of the N-doped region and the P-doped region Forming an opening in the layer and filling the opening with a contact material; and forming a plurality of gate electrode lines above the SOI substrate without filling any material of the grid in the opening. The SOI substrate may be an FDSOI substrate including a thin semiconductor layer formed on the buried oxide layer and providing a channel region of the transistor device. A connection unit may be formed to provide electrical connection between the N-doped region and the P-doped region and a bias voltage network that provides a voltage for reverse biasing the transistor device.

In all the above examples, the connection unit is between the N-doped region/P-doped region of the semiconductor bulk substrate (on which the transistor device is formed) and the bias voltage network used to reverse bias the transistor device Provide electrical connection. The transistor device may have a gate electrode made of a metal material and a polysilicon material, wherein the polysilicon material is provided in the form of (polycrystalline) gate electrode lines passing through a regular (standard) cell grid.

10‧‧‧Semiconductor block substrate, block substrate

11‧‧‧N+ doped region, region, P+/N+ region

12‧‧‧P+ doped area, area, P+/N+ area

13‧‧‧BOX layer

14‧‧‧Gate electrode material layer, polycrystalline material layer

14a‧‧‧Gate electrode wire, polysilicon wire, polycrystalline wire, gate electrode, polycrystalline gate electrode, parallel polycrystalline wire shape

15‧‧‧Parallel polyline shape, boundary element

16‧‧‧Mask layer

17‧‧‧patterned mask

19‧‧‧Polycrystalline ridge, polycrystalline structure

20‧‧‧semiconductor layer

100‧‧‧ unit outline

110‧‧‧Connection unit/BOX opening

120‧‧‧Embedded boundary cells/polycrystalline lines, boundary cells

130‧‧‧P doped region

135‧‧‧N-doped area

210‧‧‧ opening

220‧‧‧Bottom boundary unit

220’‧‧‧top boundary unit

230‧‧‧P doped region

235‧‧‧N doped region

300‧‧‧Connecting unit-standard unit design

310‧‧‧BOX

315‧‧‧Boundary polyline, boundary polyline shape

318‧‧‧Polycrystalline line

320‧‧‧Wide polycrystalline shape, embedded boundary cell/polycrystalline line

350‧‧‧Standard unit

355‧‧‧ Standard unit

400‧‧‧Design, layout

410‧‧‧ opening

420‧‧‧Embedded boundary element, structure

430‧‧‧P doped region

435‧‧‧N doped region

440‧‧‧Structure

500‧‧‧Design, layout

510‧‧‧ opening

515‧‧‧Boundary cell/poly line

518‧‧‧Polycrystalline line

520‧‧‧Buried boundary cell/polycrystalline

600‧‧‧Layout

610‧‧‧ opening

620‧‧‧Buried boundary cell/poly

630‧‧‧P doping

635‧‧‧N doping

640‧‧‧Embedded top/bottom unit structure

The present invention can be understood by referring to the following description in conjunction with the accompanying drawings. The same element symbols in these drawings represent similar elements, and among them: FIGS. 1a to 1e show the conventional reverse bias of a standard cell grid, where FIG. 1a shows Including the SOI configuration of the doped regions in the semiconductor bulk substrate used for reverse biasing, Figure 1b shows the regular standard cells including parallel polylines and boundary cells, and Figures 1c to 1e show the Wafer contamination issues associated with thin poly ridges formed in the formed larger openings; Figures 2a to 2c show integrated circuit (IC) connection cell-standard cell design where substrate contacts are moved to regular poly lines The outside of the grid; Figures 3a and 3b show an alternative connection unit for an integrated circuit-a standard cell design, where the substrate contacts are moved outside the regular polyline grid; and Figure 4 shows another of the integrated circuit Alternative connection cell-standard cell design, where substrate contacts are moved outside the regular polyline grid.

Although the inventive subject matter disclosed herein allows for various modifications and alternative forms, specific embodiments of the inventive subject matter are shown in the drawings in the form of examples and are described in detail herein. However, it should be understood that this article The description of the specific embodiments is not intended to limit the invention to the disclosed specific forms, but on the contrary, it is intended to cover all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention defined by the scope of the appended patent application.

Various exemplary embodiments of the present invention are explained below. For clarity, not all features in actual implementation are described in this specification. Of course, it should be understood that in the development of any such actual embodiment, a large number of specific implementation decisions must be made to meet the developer’s specific goals, such as compliance with system-related and business-related constraints, which differ from one to the other. Implementation varies. Moreover, it should be understood that such development efforts may be complicated and time-consuming, but it is still a routine procedure performed by a person of ordinary skill in the art with the help of the present invention.

The following examples are sufficiently illustrated to enable those skilled in the art to use the present invention. It should be understood that based on the present invention, other embodiments will be apparent, and that system, structure, manufacturing method, or mechanical changes may be made without departing from the scope of the present invention. In the following description, the details of specific reference numerals are given to fully understand the present invention. However, it is obvious that the embodiments of the present invention can be implemented without these specific details. In order to avoid obscuring the present invention, some known circuits, system configurations, structural configurations, and manufacturing method steps are not disclosed in detail.

The invention will now be explained with reference to the drawings. The various structures, systems and devices shown in the drawings are for explanatory purposes only and to avoid obscuring the invention with details known to those skilled in the art, but these drawings are still included to illustrate and explain examples of the invention. Words and words used in this article The meaning of the group should be understood and interpreted as consistent with the understanding of those words and phrases by those skilled in the relevant art. The coherent use of terms or phrases herein is not intended to imply a particular definition, that is, a definition that is different from the usual customary meaning understood by those skilled in the art. If a term or phrase is intended to have a specific meaning, that is, a meaning that is different from those understood by those skilled in the art, such special definitions will be clearly expressed in the description in a way that directly and specifically provides a specific definition of the specific definition of the term or phrase.

After reading this application in full, it is easy for those skilled in the art to understand that the method can be applied to various technologies, such as NMOS, PMOS, CMOS, etc., and can be easily applied to various devices, including but not limited to logic devices, SRAM devices, etc. , Especially in the context of FDSOI technology for manufacturing integrated circuits (ICs). In general, manufacturing techniques and semiconductor devices in which reverse (substrate) biased N-channel transistors and/or P-channel transistors can be formed are described herein. This manufacturing technology can be integrated into the CMOS manufacturing method. After reading this application in full, it is easy for those skilled in the art to understand that, in principle, this method can be applied to various technologies, such as NMOS, PMOS, CMOS, etc., and is easily applied to various devices, including but not limited to logic devices, Memory devices, SRAM devices, etc. The techniques and processes described herein can be used to manufacture MOS integrated circuit devices, including NMOS integrated circuit devices, PMOS integrated circuit devices, and CMOS integrated circuit devices. In detail, the manufacturing method steps described herein are used in conjunction with any semiconductor device manufacturing method for forming gate structures of integrated circuits (including planar and non-planar integrated circuits). Although the term "MOS" generally refers to a device with a metal gate electrode and an oxide gate insulator, the The term is used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) above a gate insulator (whether oxide or other insulator) above the semiconductor substrate.

Generally speaking, the present invention provides techniques for forming contacts to the bulk substrate of the FDSOI device to promote the reverse bias of the bulk substrate, and the design of the connection unit and the standard unit, where it will be formed to manufacture polycrystalline The polycrystalline material of the gate line is not formed in the opening of the BOX layer of the FDSOI substrate.

An example connection unit-standard unit design of an integrated circuit according to the present invention is shown in Figures 2a to 2c. The substrate contacts provided for the reverse bias of the FET are moved to the outside of the regular grid of standard cells each including the FET. The feature of the cell outline 100 shown in FIG. 2a is that the connection cell/BOX opening 110 is provided in an area of the wafer that is not formed of polycrystalline material as part of a regular polycrystalline wire grid or polycrystalline gate. The wafer substrate may be contacted in the P-doped region 130 and the N-doped region 135, which may be similar to the regions 11 and 12 shown in FIG. 1a. The connection unit/BOX opening 110 is arranged between the buried boundary cell/poly line 120. The embedded boundary cells 120 may be similar to the conventionally designed boundary cells 15 (see FIG. 1b), but they are formed in a regular grid of other standard cells, rather than at the edge of that grid.

The standard cell can represent any type of logic cell including FETs, such as inverters, NAND gate cells, multiplexers, and so on. As shown in FIG. 2b, specific bottom boundary cells 220 (top graph in FIG. 2b) and top boundary cells 220' (bottom graph in FIG. 2b) may be formed. The wafer substrate can be contacted in the P-doped region 230 and the N-doped region 235 through the opening 210. due to In the design shown, the polyline of this standard cell grid will always be sufficiently separated from the opening in the BOX layer (that is, outside the boundary cell 120) so that it will not be separated by these as described above in the prior art Undesirable formation of unstable polycrystalline structures in the openings causes polycrystalline residues.

Due to the wider polycrystalline shape 320 in the buried boundary cells in contact with the adjacent substrate, the connection cells may no longer be above or below the regular standard cells, because these standard cells use a regular polycrystalline line grid. Conversely, the connection unit may be placed in the connection unit row that starts at the lower standard cell boundary column and ends at the upper standard cell boundary column, as shown in Figure 2c. In more detail, FIG. 2c shows the connection unit-standard cell design 300 of the integrated circuit, the standard cell 350 is located at the lower boundary of the specific region of the wafer, and the standard cell 355 is located at the upper boundary of the specific region of the wafer. Similar to the traditional design, the boundary cell and the boundary poly line 315 are provided on the left and right boundaries of the area. The boundary poly line shape 315 has a larger width compared to the standard cell poly line 318 to protect these regular poly lines 318 from polishing defects during manufacturing.

The polycrystalline lines 318 of the standard cell are parallel to each other. The conventional regularity of this polycrystalline line grid is broken by the arrangement of rows of buried (internal) boundary cells/polycrystalline lines 320. Between two rows of buried boundary cells/poly lines 320, the openings and connection units in the BOX layer 310 are arranged to contact the N-doped and P-doped regions of the semiconductor bulk substrate of the wafer. The N-doped region may be a region heavily doped with N-type impurities such as phosphorus and arsenic. The P-doped region may be a region heavily doped with P-type impurities such as boron and indium. For example, "heavy concentration doping" may include any impurity concentration higher than 10 ¹⁹ /cm ³ . The connection unit provides an electrical connection between the N-doped/P-doped region of the bulk substrate on which the transistor device is formed and the bias voltage network used to reverse bias the piezoelectric crystal device.

It should be noted that in the design shown in Fig. 2c, the connection units may be arranged at equal intervals in the row of the IC configuration. Preferably, the distance between the connection units does not exceed the maximum allowable distance obtained using the design rules associated with the IC. Specifically, the design rule may specify the maximum distance from any point in the substrate or well region to the closest substrate or well connection, respectively. Moreover, it should be noted that in addition to providing coupling of the doped regions of the semiconductor bulk substrate, the connection unit may provide a decoupling capacitor for the power line to more effectively use the area occupied by the connection unit.

The connection unit can be arranged within the IC design layout before, after, or simultaneously with the standard cell layout. The reduction and control of power leakage can be optimized by the number and positioning of the connection units. The pitch of the connection unit may be based on the geometric dimensions of the associated FET and other devices, so that as the geometry size continues to shrink, the frequency and pitch of the connection unit may increase or decrease as desired.

Each of the connection units may also have a bias voltage source and/or controller independent of the voltage source and/or controller of the associated device. The voltage source and/or controller of the connection unit may be located locally or remotely relative to the associated device, possibly even on a separate die or wafer. Each connection unit may have an independent voltage source. Alternatively, all connection units can be controlled by a single voltage source. The connection unit clusters in the IC may have a common voltage, so that each connection unit cluster in the IC can be connected to a corresponding voltage source and/or controller.

Here, and in the following example, the disclosed layout may be integrated into an IC design tool, which may include one or more of various databases (eg, semiconductor wafer foundries and/or wafer foundries The customer's database) is coupled to multiple electronic software design tools. In particular, the IC design tool may include a plurality of device libraries accessible through a graphical user interface, whereby units from each device library may be arranged in the IC design layout.

In this example, and in the examples described below with reference to FIGS. 3a, 3b, and 4, the disclosed connection cell-standard cell design can be used in the context of semiconductor device manufacturing including SOI or FDSOI FETs. The FET that can be reverse-biased through the connection unit may include a FET having a configuration similar to that shown in FIG. 1a. In more detail, the FET reverse-biased by the design disclosed herein can be formed on an FDSOI substrate including a bulk substrate, a BOX layer formed on the bulk substrate, and a BOX layer formed on the BOX layer Semiconductor layer.

The bulk semiconductor substrate may be a silicon substrate, especially a single crystal silicon substrate. Other materials can be used to form the semiconductor substrate, such as germanium, silicon germanium, potassium phosphate, gallium arsenide, and the like. The bulk semiconductor substrate includes N ⁺ /P ⁺ doped regions for reverse bias. The BOX layer may include a dielectric material, such as silicon dioxide, and may have a thickness of, for example, at least 50 nanometers. The semiconductor layer can provide the channel region of the FET and can be composed of any suitable semiconductor material, such as silicon, silicon/germanium, silicon/carbon, other group II-VI or group III-V semiconductor compounds, and the like. The semiconductor layer may have a thickness suitable for forming a fully depleted field effect transistor, for example, a thickness in the range of about 5 to 8 nanometers.

The FET includes a gate electrode formed above the semiconductor layer. The gate electrode may include metal gate and polysilicon gate material. The material of the metal gate may depend on whether the transistor device to be formed is a P-channel transistor or an N-channel transistor. In embodiments where the transistor device is an N-channel transistor, the metal may include La (lanthanum), LaN (lanthanum nitride), or TiN (titanium nitride). In an embodiment where the transistor device is a P-channel transistor, the metal may include Al (aluminum), AlN (aluminum nitride), or TiN (titanium nitride).

The metal gate may include a work function adjusting material, such as TiN. In detail, the metal gate electrode may include work function adjusting materials including suitable transition metal nitrides, such as those of Group IV-VI of the periodic table, including, for example, titanium nitride (TiN), Tantalum nitride (TaN), aluminum titanium nitride (TiAlN), aluminum tantalum nitride (TaAlN), niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN) and the like, having about 1 To a thickness of 60 nm. Moreover, the effective work function of the metal gate can be adjusted by adding impurities such as aluminum, carbon or fluorine. The poly gate can be formed on top of the metal gate.

The gate electrode can be separated from the semiconductor layer of the FDSOI substrate by a gate dielectric. The gate dielectric may include a high-k material layer having a dielectric constant k higher than 4. The high-k material layer may include a transition metal oxide, such as at least one of hafnium oxide, hafnium dioxide, and hafnium silicon oxynitride, and may be directly formed on the semiconductor layer of the FDSOI substrate.

Other example connection unit-standard cell designs of the integrated circuit according to the present invention are shown in Figures 3a and 3b. Designs 400 and 500 integrate elements from the top and bottom boundary cells, equivalent to 2a to The design shown in Figure 2c, but with increased cell width, can be seen from Figures 3a and 3b.

Compared with the connection units shown in Figs. 2a to 2c, the connection units of the layouts 400 and 500 consume more area per unit, but they can be arbitrarily arranged inside the layout. Therefore, the arrangement of the connection unit can be realized in a more flexible manner, and when arranged in a checker-board design, fewer connection units are required. In addition, no specific boundary cell is needed to adjust the grid of connection cell polycrystalline lines at the arrangement boundary.

As shown in Figure 3a, the layout 400 includes buried boundary cells 420 and top/bottom cell structures 440. The opening 410 in the BOX layer is arranged between the structures 420 and 440. The opening 410 allows electrical contact with the P-doped region 430 and the N-doped region 435, which are formed in the bulk semiconductor substrate and formed on the semiconductor layer and the semiconductor layer with a reverse bias Transistor device above the semiconductor bulk substrate. Such a connection unit layout 400 can be used in the connection unit-standard unit layout 500 shown in FIG. 3b.

Similar to the layout shown in Fig. 2c, the layout shown in Fig. 3b includes a row of boundary cells/poly lines 515 and poly lines 518 arranged in parallel. Furthermore, a buried boundary cell/poly line 520 is provided, between which the opening 510 in the BOX layer and thus the connection unit can be arranged.

According to another example shown in Figure 4, through appropriate selection of post-design compensation (repositioning) and the corresponding design rules can be avoided for the wider buried poly line as shown in Figures 3a and 3b need. Thereby, the space required for implementing the connection unit suitable for arbitrary arrangement can be reduced. 4th The layout 600 shown in the figure includes a buried boundary cell/poly line 620 and a buried top/bottom cell structure 640, and an opening 610 is formed in the BOX layer to contact the P-doped 630 and N-doped 635 regions, as described above .

Therefore, the present invention provides a connection cell-standard cell layout to avoid forming polycrystalline material in the opening formed in the BOX layer of the FDSOI substrate to contact the doped region of the bulk substrate of the FDSOI substrate required by the reverse bias FET . Thereby, wafer contamination due to polycrystalline residues caused by the unstable polycrystalline structure formed in the opening of the BOX layer can be avoided.

Since those skilled in the art can easily modify and implement the present invention in different but equivalent ways with the help of the teachings herein, the above specific embodiments are merely exemplary. For example, the above-mentioned manufacturing method steps can be performed in a different order. Moreover, the present invention is not limited to the details of the architecture or design shown here, but as described in the patent application scope below. Therefore, it is obvious that the specific embodiments disclosed above can be modified or changed, and all such changes fall within the scope and spirit of the present invention. It should be noted that the terms "first", "second", "third", or "fourth" used to describe various manufacturing methods or structures within the scope of this specification and the attached patent applications are used only as The quick reference of such steps/structures does not necessarily mean that such steps/structures are executed/formed in the order of arrangement. Of course, depending on the language of the exact scope of the patent application, the order of such manufacturing methods may or may not be required. Therefore, the following patent application scope defines the protection scope of the present invention.

300‧‧‧Connecting unit-standard unit design

310‧‧‧BOX

315‧‧‧Boundary polyline, boundary polyline shape

318‧‧‧Polycrystalline line

320‧‧‧Wide polycrystalline shape, embedded boundary cell/polycrystalline line

350‧‧‧Standard unit

355‧‧‧ Standard unit

Claims (15)

An integrated circuit includes: a semiconductor bulk substrate; a buried oxide layer formed on the semiconductor bulk substrate; a plurality of units, each unit having a transistor device formed above the buried oxide layer; a plurality of A gate electrode line passing through the plurality of cells and providing a first gate electrode line for the transistor device of the cell; a plurality of connection units configured to electrically contact the semiconductor bulk substrate and arranged in Different positions below or above the plurality of cells of the transistor device, wherein at least one of the plurality of connection cells is arranged between buried boundary cells having a second gate electrode line, wherein, The second gate electrode line in the buried boundary cell has a width greater than the first gate electrode line; and the boundary cell, which is arranged at the outermost cell adjacent to the plurality of cells and has a width greater than the first The third gate electrode line with the width of the gate electrode line. The integrated circuit as described in item 1 of the patent application range, wherein the semiconductor bulk substrate includes one associated with one of the plurality of connection units and passes through the contact via an opening formed in the buried oxide layer At least one of the N-doped region or the P-doped region in which one of the connection units is electrically connected to the bias voltage source. The integrated circuit as described in item 1 of the patent application scope, wherein the plurality of connection units are arranged in a plurality of units with the transistor device The rows of the element are parallel in at least one row, so that the connection units are arranged adjacent to each other in the at least one row. The integrated circuit according to item 1 of the patent application scope, wherein the buried oxide layer and the semiconductor bulk substrate are part of a fully depleted silicon-on-insulator (FDSOI) substrate. The integrated circuit as described in item 1 of the patent application range, wherein the gate electrode line is at least partially made of polysilicon material. An integrated circuit includes: a semiconductor bulk substrate; a buried oxide layer formed on the semiconductor bulk substrate; a plurality of units, each unit having a transistor device formed above the buried oxide layer; a plurality of A gate electrode line passing through the plurality of cells and providing a first gate electrode line for the transistor device of the cell; a plurality of connection units configured to electrically contact the semiconductor bulk substrate and arranged in Different positions below or above the plurality of cells of the transistor device, wherein at least one of the plurality of connection cells is arranged between buried boundary cells having a second gate electrode line, wherein, The second gate electrode line in the buried boundary cell has the same width as the first gate electrode line; and the boundary cell, which is arranged adjacent to the outermost cell of the plurality of cells and has a width greater than the first A third gate electrode line with the width of one gate electrode line. An integrated circuit includes: a grid of standard cells, each of the standard cells having a field effect transistor built on a fully depleted silicon-on-insulator (FDSOI) substrate; a plurality of connection units configured for the field effect transistor At least some of them provide a reverse bias; wherein, at least some of the connection cells are not built above or below the standard cells of the standard cell grid; and wherein at least some of the connection cells are broken by the standard cell grid Regular buried boundary cells are surrounded; buried boundary cells are arranged between the connection cells; boundary cells are arranged near the outermost cells of the standard cell; the first polysilicon line passes through the standard cell; second A polysilicon line passing through the buried boundary cell; and a third polysilicon line passing through the boundary cell, wherein the second and third polysilicon lines have a width greater than the first polysilicon line The width. The integrated circuit as described in item 7 of the patent application range, wherein the FDSOI substrate has a bulk substrate having an N-doped region and a P-doped region, and a buried oxide layer formed above the bulk substrate, and Wherein, contacts are formed through the buried oxide layer and reach the N-doped and P-doped regions, thereby allowing the reverse bias. The integrated circuit as described in item 7 of the patent application scope, wherein a polysilicon line providing a gate electrode for the field effect transistor passes through the standard cell. The integrated circuit as described in item 7 of the patent application scope, wherein the field effect transistor is formed on the gate dielectric layer, the gate dielectric layer is formed on the semiconductor layer of the FDSOI substrate, and the field effect The transistor includes a gate electrode formed of a metal material and a polysilicon material above the dielectric layer, and wherein the polysilicon material is formed as a polysilicon gate line passing through the standard cell grid. An integrated circuit includes: a grid of standard cells, each of the standard cells having a field effect transistor built on a fully depleted silicon-on-insulator (FDSOI) substrate; a plurality of connection units configured for the field effect transistor At least some of them provide a reverse bias; wherein, at least some of the connection cells are not built above or below the standard cells of the standard cell grid; and wherein at least some of the connection cells are broken by the standard cell grid Regular buried boundary cells are surrounded; buried boundary cells are arranged between the connection cells; boundary cells are arranged near the outermost cells of the standard cell; the first polysilicon line passes through the standard cell; and the first Two polysilicon lines pass through the buried boundary cell; wherein, the second polysilicon line has a width greater than that of the first polysilicon line. A method for manufacturing an integrated circuit, the method comprising: providing a silicon-on-insulator substrate having a semiconductor bulk substrate and a buried oxide layer formed on the bulk substrate; Forming a transistor device on the silicon-on-insulator substrate; forming at least one of an N-doped region and a P-doped region in the semiconductor bulk substrate; the at least one of the N-doped region and the P-doped region Forming an opening in the buried oxide layer above; filling the opening with a contact material; forming a plurality of gate electrode lines above the silicon substrate on the insulator without filling any material of the gate electrode lines in the opening; Define a grid of standard cells, each of which includes a transistor device having a first gate electrode line; form a buried boundary cell that includes a second gate electrode line; and form a plurality of connection units to allow the plurality of connections At least some of the cells are not located above or below any of the plurality of gate electrode lines, and at least one of the plurality of connection cells is arranged between some of the buried boundary cells; and a boundary cell is formed, which is Arranged adjacent to the outermost cell of the standard cell, the boundary cell has a third gate electrode line, wherein the second and third gate electrode lines have a width greater than that of the first gate electrode line. The method as described in item 12 of the patent application scope further includes contacting the at least one of the N-doped region and the P-doped region with a bias voltage network through one of the plurality of connection units. The method according to item 12 of the patent application scope, wherein each standard cell of the standard cell grid is divided by one of the plurality of gate electrode lines Through, and wherein, the connection units are arranged adjacent to each other in at least one row, which is parallel to the row of the standard cell grid. The method according to item 12 of the patent application scope, further comprising: wherein each standard cell of the standard cell grid is crossed by one of the plurality of gate electrode lines; wherein, the buried boundary cell includes a first A group of embedded boundary cells and a second group of embedded boundary cells; wherein, the standard cells of the standard cell grid separate the second set of embedded boundary cells from the first set of embedded boundary cells; A first connection unit of the plurality of connection units is arranged between the buried boundary units of the first group; and a second connection unit of the plurality of connection units is arranged between the buried boundary units of the second group .

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