TWI680579B - Transistor device - Google Patents

Abstract

A semiconductor device includes a substrate, the substrate being of a first conductivity type. A buried layer of the second conductivity type is formed in a surface layer region in the substrate. The buried layer of the second conductivity type includes a center region, a plurality of separation regions are distributed outward from the center region, and a peripheral region is on the periphery of the plurality of separation regions. An epitaxial layer is formed on the substrate. The high-voltage well region of the first conductivity type is formed in the epitaxial layer. The first conductivity type gold-oxide semiconductor transistor is formed on the high-voltage well region. The center region of the buried layer of the second conductivity type is below a drain region of the gold-oxide semiconductor transistor.

Description

Transistor element

The present invention relates to a semiconductor manufacturing technology, and more particularly to a structure of a transistor element.

Increasing emphasis on energy efficiency. In response to market changes, high-voltage integrated circuit (HVIC) chips with higher performance and economic benefits have been gradually adopted. Semiconductor integrated circuits will include high voltage transistors operating at high voltages.

The high voltage transistor will operate at high voltage, but if the breakdown voltage of the high voltage transistor is not high enough, for example, it is lower than the breakdown voltage of 120v, then the high voltage transistor cannot effectively operate at a larger voltage. High voltage electric range. High-voltage transistors are typically designed, for example, with P-conductive metal-oxide-semiconductor (MOS) transistors.

How to increase the breakdown voltage of high-voltage transistors is one of the issues to be considered when designing transistor structures.

The invention provides a structure of a transistor element, which can increase the breakdown voltage of the transistor. The transistor element can effectively operate in a high voltage range, such as a voltage range higher than 120V or higher.

In one embodiment, a transistor device of the present invention includes a substrate, and the substrate is of a first conductivity type. The buried layer of the second conductivity type is disposed in a surface layer region in the substrate. The buried layer of the second conductivity type includes: a center region; a plurality of separation regions distributed outward from the center region; and a peripheral region on the periphery of the plurality of separation regions. An epitaxial layer is formed on the substrate. A high-voltage well region of the first conductivity type is disposed in the epitaxial layer. The gold-oxide semiconductor transistor of the first conductivity type is formed on the high-voltage well region. The center region of the buried layer of the second conductivity type is below a drain region of the gold-oxide semiconductor transistor.

In an embodiment, in the transistor device, the plurality of separated regions are separated blocks or separated annular blocks.

In an embodiment, in the transistor element, the widths of the plurality of separated regions of the buried layer of the second conductivity type extend from the central region toward the source region of the gold-oxide semiconductor transistor. The extension direction is the same.

In an embodiment, in the transistor device, wherein the widths of the plurality of separated regions of the second conductive type buried layer extend from the center region to the source region of the gold-oxide semiconductor transistor. The direction is gradually increasing.

In an embodiment, in the transistor device, the plurality of separated regions of the buried layer of the second conductivity type are annular.

In an embodiment, in the transistor device, the second conductive type The peripheral region of the buried layer is below a source region of the gold-oxide semiconductor transistor.

In an embodiment, in the transistor element, the buried layer of the second conductivity type forms a doped diffusion region on the substrate, and the doped diffusion region constitutes a plurality of separate regions according to a doping amount. Doped rings or multiple doped blocks, the doped rings or the two adjacent doped regions of the multiple doped blocks have a doping amount relative to the doping of the adjacent two The doping amount of the ring or the middle region of the doped block is low.

In one embodiment, the transistor element further includes an insulating layer. On the surface of the epitaxial layer and above the high-voltage well region, a gate structure is on the epitaxial layer and the insulating layer and the source. The electrode region is on the surface layer of the epitaxial layer, above the peripheral region of the buried layer of the second conductivity type, and opposite to the drain region and the source region are on both sides of the gate structure.

In an embodiment, in the transistor device, a width of the plurality of separation regions is less than or equal to a distance between two adjacent separation regions.

In an embodiment, in the transistor device, a width of the plurality of separation regions is between 0.4 times and 1.0 times a distance between two adjacent separation regions.

In an embodiment, in the transistor device, an average doping amount of the buried layer of the second conductivity type in the peripheral region is larger than an average doping amount of the plurality of separation regions.

In an embodiment, in the transistor device, the first conductivity type is a P type, and the second conductivity type is an N type.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

50‧‧‧High Voltage MOS Transistor

60‧‧‧High Voltage MOS Transistor

100‧‧‧ substrate

102‧‧‧Buried oxide layer

104‧‧‧N Well Area

106‧‧‧N-type buried area

108‧‧‧P well area

110‧‧‧Source structure

112‧‧‧ Drain Structure

114‧‧‧Gate structure

116‧‧‧Insulation structure

200‧‧‧ substrate

202‧‧‧N-type buried area

202a‧‧‧ central area

202b, 202c, 202d, 202d’‧‧‧ separation area

202e‧‧‧ Outer area

204‧‧‧High-voltage P-type well area

206‧‧‧Epitaxial layer

207, 208, 210, 212, 213‧‧‧ doped regions

214‧‧‧oxide

216‧‧‧Source Structure

218‧‧‧Drain structure

220‧‧‧Gate structure

224‧‧‧field board structure

300, 304‧‧‧N-type buried layer

302, 306‧‧‧‧doped diffusion regions

FIG. 1 is a schematic cross-sectional structure diagram of a general high-voltage transistor.

FIG. 2 is a schematic cross-sectional structure of a high-voltage transistor according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a top-view structure of an N-type buried layer of a high-voltage transistor in a substrate according to an embodiment of the present invention.

4 is a schematic cross-sectional structure diagram of an N-type buried layer of a high-voltage transistor and a doped amount diffusion distribution structure thereof in a substrate according to an embodiment of the present invention.

The invention relates to the structure of a high-voltage metal-oxide-semiconductor (HVMOS) transistor of the first conductivity type, and its breakdown voltage can be effectively increased by the design of the buried layer of the second conductivity type, which can be applied to higher voltage Operating range. In an embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. Or in another embodiment, the first conductivity type is an N type, and the second conductivity type is a P type.

Some examples and conventional high-voltage metal-oxide-semiconductor (HVMOS) transistors of the P conductivity type used for exploration and comparison are listed below, but the present invention is not limited to the many examples.

The following describes the investigation of the conventional high voltage transistor of the present invention. FIG. 1 is a schematic cross-sectional structure diagram of a general high-voltage transistor. Referring to FIG. 1, a high-voltage transistor can be manufactured by using a substrate of silicon on insulator (SOI). For the P-conducting substrate 100, a buried oxide layer 102 is formed on the substrate 100. For the structure of the SOI substrate, an epitaxial layer of silicon material is formed on the buried oxide layer 102, which is the structure of the SOI substrate. Various doped regions required for the high-voltage MOS transistor 50 may be formed in the epitaxial layer, which includes, for example, an N-type well region 104 on the buried oxide layer 102. The N-type well region 104 includes an extended N-type buried region 106 formed on the buried oxide layer 102.

Here, from the perspective of the manufacturing process, the P-type well region 108 is formed in the N-type well region 104 by an implantation process. The N-shaped region under the P-type well region 108 constitutes an N-type buried region 106.

Next, deeper surface doped regions will be formed in the N-type well region 104 and the P-type well region 108 to apply an operating voltage. In addition, a gate will be formed on the N-type well region 104 and the P-type well region 108 The electrode structure (G) 114, the source structure (S) 110, the drain structure (D) 112, and the insulation structure 116, and so on.

As for the structure of the high-voltage MOS transistor, it is completed according to generally known manufacturing techniques. The present invention is not particularly limited, and the manufacturing process is also omitted here. However, the present invention is exploring the structure of this general high-voltage MOS transistor. After a detailed study of the performance and corresponding structure, the present invention indicates that the N-type buried region 106 is a monolithic structure, and its breakdown voltage is affected by the N-type buried. Area 106 affects and may not be effectively promoted. In addition, it is the base of SOI and is relatively high in manufacturing cost.

Some examples are given below to illustrate the structure of the semiconductor device provided by the present invention. For example, the application in a P-conductive high-voltage MOS transistor can effectively increase the breakdown voltage value and increase the operating range of the transistor voltage.

FIG. 2 is a schematic cross-sectional structure of a high-voltage transistor according to an embodiment of the present invention. Referring to FIG. 2, taking a P-conductive high-voltage MOS transistor 60 as an example, for a P-type substrate 200, the surface layer in the substrate 200 of the present invention uses an implantation process to form an N-type buried region 202. Thereafter, an epitaxial layer 206 of silicon is formed on the substrate 200 for subsequent formation of a required doped region, such as a high-voltage P-type well region 204. The epitaxial layer 206 is, for example, N-type, and can provide an N-type well region. From another point of view, with the N-type epitaxial layer 206, the high-voltage P-type well region 204 is completed in the epitaxial layer 206 using an implantation process. In this embodiment, the P-type and N-type of the present invention refer to different conductivity types of semiconductor characteristics. Structurally, the P-type is an embodiment of the first conductivity type, and the N-type is an embodiment of the second conductivity type. In the following description, the first conductivity type is an example of a P type, and the second conductivity type is an example of an N type. As for the doped structure, the two can also be interchanged. The present invention is not limited to the P-type and N-type described in the embodiments.

After the structure of the N-type buried region 202 is completed in the substrate 200, an epitaxial layer 206 is formed first. The epitaxial layer 206 is used as a semiconductor substrate of the MOS transistor to complete the manufacture of the MOS transistor. The epitaxial layer 206 may be doped into an N-type epitaxial layer 206 first. Thereafter, the epitaxial layer 206 is re-doped to form a high-voltage P-type well region 204. The depth of this doping to form the high-voltage P-type well region 204 may extend to the substrate 200 on the N-type buried region 202. After that, various doped regions 207, 208, 210, 212, and 213 can be completed according to the structure of the P-conducting high-voltage MOS transistor 60, of which, The doped region 213 is a part of the source region, and includes P-type and N-type heavily doped regions, represented by P + and N +, and can be connected to an external source structure (S / B) 216. The doped region 210 is regarded as a part of the drain region and is connected to the external drain structure (D) 218. In addition, an oxide layer 214 is formed on the high-voltage P-type well region 204, and a gate structure (G) 220 is formed on the epitaxial layer 206 and extends to the oxide layer 214. In response to the high-voltage structure, a field plate structure 224 may be further formed on the gate structure (G) 220.

The aforementioned high-voltage MOS transistor 60 of the P-conduction type is only one embodiment, and the present invention is not limited to the structure, and may have different variations. The detailed description of the high-voltage MOS transistor 60 and other changes are omitted here. In accordance with the structure of the high-voltage MOS transistor 60, the present invention proposes a structure of the N-type buried region 202 to increase the breakdown voltage of the high-voltage MOS transistor 60.

The structure of the N-type buried region 202 is described in more detail below. The N-type buried region 202 of the present invention may be a bulk or ring-shaped doped structure before the doping diffusion process. FIG. 3 is a schematic diagram of a top-view structure of an N-type buried layer of a high-voltage transistor in a substrate according to an embodiment of the present invention. At the same time, referring to FIG. 3, the N-type buried region 202 includes a central region 202a, which is also denoted by D and represents the position of the drain electrode. The central region 202a is, for example, a disk shape, and corresponds to the lower side of the drain structure of the transistor. The plurality of separated regions 202b, 202c, 202d, 202d ', ... are distributed outward from the central region 202a. The peripheral region 202e is on the periphery of the plurality of separated regions 202b, 202c, 202d, and 202d '. The number of separation regions 202b, 202c, 202d, 202d 'depends on actual needs.

In one embodiment, the plurality of separated regions 202b, 202c, 202d are, for example, Is it a separate block or a separate circular block. FIG. 3 is an example of separating circular blocks, and more specifically, it is a separated circular block. However, the present invention is not limited to the illustrated embodiments.

Regarding the sizes of the plurality of separation regions 202b, 202c, 202d, the widths of these separation regions are the same. Here, the width refers to the length along the distribution direction in the cross-sectional structure. The distribution direction is the direction from the drain to the source. In one embodiment, the widths of the plurality of separated regions 202b, 202c, 202d, 202d 'of the N-type buried layer 202 gradually increase outward from the central region 202a.

In one embodiment, the plurality of separated regions 202b, 202c, 202d, 202d 'of the N-type buried layer 202 are annular and surround the central region 202a. In one embodiment, the peripheral region 202e of the N-type buried layer 202 is below the doped region 213 (source region) of the P-type metal-oxide semiconductor transistor. In one embodiment, the widths of the plurality of separation regions 202b, 202c, 202d, 202d 'are less than or equal to the distance between two adjacent separation regions. In one embodiment, the width of the separation regions 202b, 202c, 202d, 202d 'is, for example, 0.4 times to 1.0 times the distance between two adjacent separation regions, but the present invention is not limited to this range.

After the N-type buried layer 202 is formed in the substrate 200 through the implantation process, there will be a diffusion process before the transistor is actually completed subsequently. The separated regions in the N-type buried layer 202 will be connected into one, but the doping amount Will decrease. 4 is a schematic cross-sectional structure diagram of an N-type buried layer of a high-voltage transistor and a doped amount diffusion distribution structure thereof in a substrate according to an embodiment of the present invention.

Referring to FIG. 4, in an embodiment, the N-type buried layer 300 is on the substrate 200. The cross-sectional structure constitutes the cross-sectional structure of the doped diffusion region 302 after the diffusion process. In this embodiment, the widths of the separation regions 202b, 202c, 202d, and 202d 'are the same as an example. The doped diffusion region corresponding to the doping amount forms a plurality of doped rings or a plurality of doped regions corresponding to the plurality of separated regions. Block. The doping amount of a plurality of doped rings or the adjacent two connecting regions of the plurality of doped blocks is relative to the doping of the adjacent two doped rings or the intermediate regions of the plurality of doped blocks. Miscellaneous is low. That is, the doped amount regions are connected after diffusion, but the overall average doped amount is reduced.

In another embodiment, the N-type buried layer 304 corresponds to the distribution of the N-type buried layer 202 in FIG. 3, and the width of the separation region is gradually increased outward from the center region of the drain region D. In this way, after the diffusion, the doped diffusion regions 306 generated by the N-type buried layer 304 are connected as a whole, but the doping amount distribution gradually decreases toward the drain region D.

The N-type buried layer 202 of the present invention has a separated structure from the central region 202a to the peripheral region 202e. After diffusion, the overall average doping amount will decrease, so the breakdown voltage of the transistor can be effectively increased. The N-type buried layer 202 can be directly formed in the substrate 200, and no SOI substrate is needed.

The present invention adopts a separate N-type buried layer 202. After simulation verification, for example, the collapse voltage can be improved by about 100V (the overall layered structure) compared to the case of an overall layered structure of the N-type embedded layer To about 140V (separated structure) or more.

In summary, for the P-type high-voltage MOS transistor, the N-type buried layer required by the present invention has a separate structure, so that the doping amount after diffusion is reduced.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope defined by the scope of patent application.

Claims (11)

A transistor element includes: a substrate, the substrate is a first conductivity type; a buried layer of a second conductivity type, in a surface layer region in the substrate, wherein the first conductivity type is a P type and the second conductivity type The type is N-type, wherein the buried layer of the second conductivity type includes: a central region; a plurality of separated regions distributed outward from the central region; and a peripheral region on the periphery of the plurality of separated regions; an epitaxial Layer on the substrate; a high-voltage well region of the first conductivity type in the epitaxial layer; a peripheral well region of the second conductivity type adjacent to the high-voltage well region; and the first A conductive metal oxide semiconductor transistor is formed on the high voltage well region, and the gate structure of the metal oxide semiconductor transistor also covers the interface of the peripheral well region adjacent to the high voltage well region. The center region of the buried layer of the second conductivity type is below a drain region of the gold-oxide semiconductor transistor. The transistor device according to item 1 of the scope of patent application, wherein the plurality of separated regions are separated blocks or separated annular blocks. The transistor element according to item 1 of the patent application scope, wherein the widths of the plurality of separated regions of the buried layer of the second conductivity type extend from the center region to the source region of the gold-oxide semiconductor transistor. The extension direction is the same. The transistor element according to item 1 of the patent application scope, wherein the widths of the plurality of separated regions of the buried layer of the second conductivity type extend from the center region to the source region of the gold-oxide semiconductor transistor. Gradually increases in the direction of extension. The transistor element according to item 1 of the patent application scope, wherein the plurality of separated regions of the buried layer of the second conductivity type are annular. The transistor device according to item 1 of the patent application scope, wherein the peripheral region of the buried layer of the second conductivity type is below a source region of the gold-oxide semiconductor transistor. The transistor element according to item 1 of the scope of patent application, wherein the buried layer of the second conductivity type forms a doped diffusion region on the substrate, and the doped diffusion region is formed according to a doping amount corresponding to a plurality of separation regions. The multiple doped rings or multiple doped blocks, the multiple doped rings or the adjacent two of the multiple doped blocks have a doping amount relative to the doped amount of the adjacent two. The doping amount of the heterocyclic ring or the middle region of the doped block is low. According to the transistor element described in item 1 of the patent application scope, the metal-oxide semiconductor transistor includes: an insulating layer on the surface of the epitaxial layer and above the high-voltage well region; the gate structure on the epitaxial layer And on the insulating layer; the source region, on the surface layer of the epitaxial layer, above the peripheral region of the buried layer of the second conductivity type, opposite the drain region and the source region is on the gate Both sides of the pole structure. The transistor element according to item 1 of the scope of the patent application, wherein the width of the plurality of separation regions is less than or equal to a distance between two adjacent separation regions. The transistor device according to item 1 of the scope of patent application, wherein the width of the plurality of separation regions is between 0.4 times and 1.0 times the distance between two adjacent separation regions. The transistor element according to item 1 of the patent application scope, wherein an average doping amount of the buried layer of the second conductivity type in the peripheral region is greater than an average doping amount of the plurality of separation regions.